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We have successfully developed a 128Gb MLC (or 192Gb TLC) 3D NAND Flash using 16-layer SGVC architecture. The produced memory density is 1.6 Gb/mm2 for MLC or 2.4 Gb/mm2 for TLC (including CMOS peripheral area, spared BL's and blocks). Such memory density is comparable to 48-layer 3D NAND using the popular gate-all-around (GAA) structures. SGVC has the important advantage of much smaller cell size and pitch scaling capability which allows very high-density memory at much lower stacking layer number. SGVC possesses very robust read disturb immunity (>120M read) and long-retention (> 40 years at room temperature) at fresh state that can suppress the very frequent wear-leveling and refresh operations needed for other 3D NAND Flash devices and is very suitable for read-intensive memory. With further stacking/scaling, it is possible to realize low-cost 1Tb single-chip solution at merely 48 layers.

The resistance of phase-change-memory (PCM) cells measured during RESET programming (dynamic resistance, Rd) is found to be inversely proportional to the amplitude of the programming current, as Rd = [A/I] + B. We show that parameters A and B are related to the intrinsic properties of the memory cell, and demonstrate by means of experimental data that they could be used to characterize the cell-to-cell process-induced variability of PCM cells.

We demonstrate a novel vertical channel 3D NAND Flash architecture — SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array decoding method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ∼10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BL's (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform C BL 's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL's in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL's are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.

The high current density induced failure in Ge 2 Sb 2 Te 5 (GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.

Selective Chemical Vapor Deposition of Crystalline Ge-Sb-Te alloys initiating at the bottom metal contact of vias of various sizes has been accomplished. The method is based on selecting Sb and Te precursors which do not decompose on dielectric surfaces in the utilized temperature range.

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.

Recent interest in phase change materials (PCMs) for non-volatile memory applications has been fueled by the promise of scalability beyond the limit of conventional DRAM and NAND flash memory [1]. However, for such solid state device applications, Ge2Sb2Te5 (GST), GeSb, and other chalcogenide PCMs require doping. Doping favorably modifies crystallization speed, crystallization temperature, and thermal stability but the chemical role of the dopant is not yet fully understood. In this work, X-ray Absorption Fine Spectroscopy (XAFS) is used to examine the chemical and structural role of nitrogen doping (N-) in as-deposited and crystalline GST thin films. The study focuses on the chemical and local bonding environment around each of the elements in the sample, in pre and post-anneal states, and at various doping concentrations. We conclude that the nitrogen dopant forms stable Ge-N bonds as deposited, which is distinct from GST bonds, and remain at the grain boundary of the crystallites such that the annealed film is comprised of crystallites with a dopant rich grain boundary.

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.

A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective physical dimensions of the memory element. We demonstrate that these two parameters provide characterization and insight into the degradation mechanisms of memory cells during operation.

We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformal deposition. Fully integrated 256 kbit test chips have been fabricated in 180nm CMOS technology. We report SET times of 80 ns, RESET currents less than 250 muA, and accurate sub-lithographic CDs that can be less than 20% the size of the lithographically -defined diameter.

A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900muA at 75nm diameter and multilevel operation are reported

A new concept for non-volatile memory is demonstrated. This new technique controls the threshold voltage of the chalcogenide storage device by varying the height and duration of the write pulse. Consequently, the chalcogenide device serves as both the access element and the memory element. Therefore, it does not need any access transistor in the memory array. The new memory achieves the requirement of non-volatility, fast writing/reading, random access, high scalability, compact cell size, and low cost.

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention