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A calibration methodology for the optimized minimum inductor (OMI) bandpass filter (BPF) to compensate passive components' inherent loss, such as resistances and reactances, is presented. OMI BPF prevails conventional elliptic and Chebyshev BPFs by introducing fewer inductors for the same stopband rejection requirement. Given design specifications (bandwidth, stopband rejection) at a specific center frequency, the calibration flow optimizes the approach to offset the inaccuracy of center frequency, bandwidth, and stopband rejection due to the discrepancy between the actual and ideal prototype passive components. Two OMI BPF designs before and after calibration are presented for demonstration and comparison. They are 1) a 3rd order centered at 2.388 GHz, 35.54% fractional bandwidth (FBW), 29.97 dB stopband rejection, and 2) a 7th order centered at 2.333 GHz, 17.40% FBW, 62.29 dB stopband rejection.

Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

In electronic-warfare (EW) receiver applications, real-time measurement of the radar signals' carrier frequencies is mandatory and considered to be one of the most important radar parameters. Accurate frequency detection can be used to sort and deinterleave signals in a dense signal environment where multiple signals arrive simultaneously presenting severe problems unless they can be differentiated appropriately. Researchers and engineers are actively looking for new algorithms for high resolution wideband receivers with easier implementation. This paper presents an adaptive gain control and dynamic thresholding wideband digital receiver to accurately detect two simultaneous high dynamic range signals, even when their signal frequencies are very close. The proposed fast Fourier transform (FFT) based receiver examines incoming signal characteristics and provides real-time accomplishment of these tasks, by way of using an adaptive gain-control amplifier, a squarer, two analog-to-digital converters, and two FFT's. The wideband receiver offers high probability of intercept over wide instantaneous RF bandwidths, high dynamic ranges and sensitivity. Two simultaneous signal accommodations and their characteristics are provided to demonstrate the improvements over presently used receivers in this field.

The use of chirp signals in modern radar and ranging systems have numerous benefits. They are extensively used to improve signal-to-noise ratio and range resolution. The performance capabilities of these signals are directly related to their time-bandwidth product, i.e., the duration and bandwidth of the pulse. Ultra-wideband chirp signals are further desirable because they span a large bandwidth, making them resistant to narrowband environmental interference. The accurate detection and measurement of high chirp signals is difficult due to the necessity of a high-sampling analog-digital converter, a target measurement platform with high computational power, and a time-of-arrival (TOA) estimator with high temporal resolution. The difficulty of the problem is further compounded with the requirement that no a priori knowledge of the signal, noise, or operating environment is known. This paper presents a practical approach and implementation of a high linear chirp rate receiver and TOA estimator pair capable of detecting and measuring stationary radio frequency pulses as well as linear chirp rates up to 1.18 GHz in 400 ns. The high-resolution TOA algorithm and linear chirp receiver have been prototyped, synthesized, and placed and routed for a Virtex 6 SX475 FPGA.

Compressed sensing has been applied in various areas of signal processing, image processing, and RF. It is attractive due to wideband coverage with reduced sampling rate. Nyquist sampling data can be approximately restored from the compressed sensing reduced sampling data using reconstruction algorithms. These algorithms usually require several optimizations to control accuracy and convergent speed in Nyquist sampling data reconstruction. Foreseeing the future hardware implementation performing the reconstruction, one needs to identify and optimize the relevant parameters in reconstruction algorithms for the best performance. In this paper, we present performance analysis of a compressed-sensing based digital wideband receiver. The compressed sensing scheme is non-uniform sampling and the subsequent reconstruction algorithm is NESTA. The restored Nyquist sampling data is analyzed with conventional frame-based fast Fourier transform FFT) to calculate sensitivity and spurious-free dynamic range. The signal detection threshold is determined from probability density function and false alarm rate. The effect of parameters controlling convergence and accuracy in Nyquist sampling data reconstruction on the receiver performance is presented. Comparison of sensitivity and dynamic range with the conventional Nyquist based FFT receiver is also presented.

A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor Q of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB.

Compressed sensing (CS) technique has been applied in various areas of signal processing including RF signal processing. It is attractive due to its potential wideband coverage with reduced sampling rate. We conduct performance analysis of compressed sensing in receiver application. The compressed sensing uses two modulations and sampling schemes: non-uniform sampling (NUS), and Pseudo Random Code (PRC). Two algorithms are used to process the compressed signals: OMP (Orthogonal Matching Pursuit) and PE (Parameter Estimation). Signal's detection sensitivity is analyzed through probability density function and the detection threshold according to the predetermined false alarm rate. Methods to remedy issue caused by modulations are proposed, and the sensitivity simulation results are also presented. The comparison of the one-signal detection sensitivity using remedy version of OMP and PE on the NUS modulation schemes are also presented and discussed. Sensitivity analysis for variable measurement matrices is then presented.

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.

A primary concern in the current radar-receiver design involves the critical issue of setting a threshold level that is optimal for all operating conditions. A novel adaptive thresholding technique is presented to maximize both the receiver sensitivity and the dual-tone signal instantaneous dynamic range (IDR) for digital microwave receivers. The additional constraint placed for signal detection improves the false-alarm rate with a minimal firmware increase due to the simplicity of the proposed algorithm. Using our adaptive thresholding technique, the receiver's maximum IDR varies between 34 and 24 dB below the primary signal for primary-signal strengths between -4 and -32 dBm. Our adaptive thresholding technique was realized in firmware through two receiver designs, i.e., the initial-scaling-stage (ISS) and multistage-scaling (MSS) receiver designs. Both receiver designs show significant improvement in weak-signal spurious-free dynamic range (SFDR) performance. The MSS receiver design shows a nearly 3-dB improvement in weak-signal SFDR performance. Performance evaluations show a well-coordinated effort for adaptive thresholding system integration into the existing radar-receiver system.

This paper presents a biologically-inspired signal processor, which allows selective amplification of signals, and signal channeling mechanism to increase the contrast and sharpness of the perceived signals. The processor draws influence from lateral inhibition and integrative function mechanisms of the human nervous system. The uniqueness of the proposed design is that it combines two intelligent signal transmission mechanisms of the human nervous system with desirable capabilities: 1) wide input bandwidth, and 2) high instantaneous dynamic range. The simulations results demonstrate that the proposed design can selectively amplify weak signals among four existing strong signals and suppress noise and spurs to expose and detect weak signals, which is 58 dB below the strong ones if 4096-point FFT is used.

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

A 2.56-gigasample-per-second (GSPS) fixed-point fixed-precision dynamic kernel function fast Fourier transform (FFT) with a variable truncation scheme (VTS) is designed for real-time wideband signal detection. Using an Atmel 10-bit analog-to-digital converter (ADC), the two-tone real-time signal detection is verified for a bandwidth of 1.14 GHz with 20-MHz channelization and output throughput rates of 50 ns. The proposed design has an averaged single-signal spurious-free dynamic range (SFDR) of 27.7 dB and the ability to detect a weak input signal at -45 dBm. The overall dynamic range (DR) of the system is 40.6 dB. This is possible for a fixed-precision FFT design due to the embedded VTS to extend the total DR while preserving the instantaneous DR (IDR) relationship. In addition, with an ideal 8-bit ADC, the averaged single-signal SFDR of 32.60 dB and the two-tone signal IDR of 22 dB are achieved. The overall DR is 48.3 dB. The dynamic kernel FFT uses about 57% of the slices available on a Xilinx XC4VSX55 Virtex 4 field-programmable gate array (FPGA). In comparison with alternative implementations based on Xilinx LogicCORE 256-point IP FFT for 8-bit data, the processing time and the overall DR are considerably superior. Additional case studies that applying the windowing function and the Taylor-series-based square root approximation show favorable results utilizing the VTS for real-time data acquisition and signal-enhancement algorithms for computing high-bit-width data while minimizing the hardware.

A system-on-a-chip (SoC) built with embedded intellectual property (IP) cores offers attractive methodology design reuse, reconfigurability, and customizability. However, the integration of the design-for-testability (DfT) structures of the IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time to market by taking core test data from the design environment and automatically generating DfT structures that can easily be integrated into the SoC. A novel automated synthesis methodology to generate an SoC built-in self-test (BIST) to test the IP and custom logic cores is proposed. The proposed technique, i.e., NonExclusive Xor Test of 2D linear feedback shift register (NEXT 2D LFSR), is modeled after the principle of configurable 2D LFSR design, which generates a deterministic sequence of test vectors for random-vector-resistant faults and then random test vectors for random-vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2D LFSR while embedding the test patterns by nonexclusively considering xor gates as the conventional LFSR does but including a simple logic solution for minimal hardware optimization. Moreover, the proposed approach is capable of optimizing the 2D LFSRs with consideration of the don't-care bits in the incompletely specified test patterns.

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.

This paper addresses the optimization of very large scale integration testing systems, specifically the structure design and optimization of a built-in self-test (BIST) design based on two-dimensional (2D) linear feedback shift registers (LFSRs). The 2D LFSRs can generate both precomputed test patterns (for detecting random-pattern-resistant faults) and random patterns (for detecting random-pattern-detectable faults) and have the advantages of high fault coverage and at-speed testing. To guarantee solutions, it is necessary and desirable to generate subsequences of the precomputed test patterns through the 2D LFSRs, where these subsequences retain the order of the test patterns, particularly for testing sequential circuits. For the design and optimization of the 2D LFSRs, the following two problems need to be solved: 1) the good partitioning of the precomputed test patterns into disjoint subsequences in order to achieve a minimal hardware and 2) the structure design and optimization of the 2D LFSRs to generate the test patterns in each partitioned subsequence. The optimization of the 2D LFSRs is modeled as an integer program (a logic optimization model) that determines the coefficients of the recursive Boolean equations that govern the generation of the test patterns. For a sequence of the test patterns, this model finds the minimal-hardware implementation of the 2D LFSRs. This logic optimization model can be applied to both test-per-scan (serial BIST) and test-per-clock (parallel BIST). This paper presents how this model is embedded in a heuristic framework to partition the test patterns into subsequences from the configurable 2D LFSRs. The testing hardware is small as the configurable architecture allows the tester to incrementally generate the precomputed test patterns by modification to the feedback of the 2D LFSRs. Results of benchmark circuits show that significant hardware reduction and higher fault coverage are achieved. The resulting multisequence test generator is a regular structure and is easy to implement. The logic optimization model is applicable to both completely and partially specified test patterns and can be adopted for other LFSR-based structure design and optimization.

A band pass filter (BPF) for center frequency over a wide frequency span and pass band is presented, which uses an efficient synthesis via two design stages: 1) the transconductance stage and 2) the transimpedance stage. Changing design parameters in the two design stages in 1.8 V 180 nanometer TSMC CMOS process, a BPF for a tuning frequency range of 1.0–2.04 GHz and a controllable pass band of 5.5–51.2 MHz is designed, which achieves a high pass band gain of 45.2–65.1 dB and a stopband rejection of 25 db. The noise figure is kept low to a range of 1.49–5.88 dB when pass band is 12 MHz. It provides a good solution to pre-tune desired signals while reject interfering signals.

A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (>20 dB) and low noise figure (

Today's very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga-sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125 - 1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%.

A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.

A complete behavioral fault simulation and automatic test pattern generation (ATPG) system for circuits modeled in VHDL has been presented in this research. Ten different behavioral fault models were selected and used to generate test patterns through fault simulation. One major advantage of the current system is that full VHDL (IEEE-STD 1076) constructs can be handled because fault simulation are performed by comparing the simulation results of good and faulty models utilizing a VHDL simulator. Areas of future research include the refinement of existing fault models, defining new behavioral fault models to reduce the gap between the behavioral fault models and gate-level failures, and the development of a better test pattern generator for target faults. Another valuable enhancement would be to run fault simulation in parallel, by embedding multiple faulty models into one test bench to simulate many faults concurrently. This would speed up the behavioral fault simulation in an efficient way. Gate-level fault simulation is not an effective solution for complex microcircuits. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC).

Carry lookahead adders have been, over the years, implemented in complex arithmetic units due to their regular structure which leads to efficient VLSI implementation for fast adders. In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder, the optimization produces a 6.37%increase in speed of the critical path while only contributing a 2.16% area overhead. The full testability of the circuit is achieved in the optimized adder design.

As a modern radar receiver must rapidly search a large frequency range with maximum sensitivity, capabilities such as high instantaneous dynamic range (IDR), good multiple-signal-detection capability, wider bandwidth (BW), and high-frequency resolution are indispensable. Many techniques proposed to improve digital wideband receiver performance are computationally intensive and limit their real-time performance due to hardware constraint. In this paper, an innovative three gigasample-per-second hybrid computing platform digital wideband receiver system is presented, which employs two Nvidia Tesla C2050 graphics processor units and a Xilinx Virtex-5 field-programmable gate array for hardware acceleration to drastically improve receiver performance over its predecessor designs. The receiver detects five simultaneous signals in 1.25-GHz BW (125-1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture achieves high-resolution spectral estimation and employs a hardware mechanism for multiple-signal detection before the next set of data arrives for processing.

The wideband coverage of the traditional FFT-based electronic warfare (EW) receiver is limited by the sampling frequency of the analog-to-digital converter (ADC). Compressed sensing (CS) based wideband EW digital receiver has been proposed and under development to process wideband sparse signals with reduced sampling rate. In this study, we calculate the sensitivity of a CS based EW receiver. Two modulation schemes of CS are used. One is pseudorandom chip (PRC) and the other is non-uniform sampling (NUS) modulation. The orthogonal matching pursuit (OMP) algorithm is used to process CS data. The insufficient nature of the sparcity of the signal adversely affects the signal detection probability for both PRC and NUS modulation schemes. Methods to remedy this problem in both modulation schemes are proposed. The improvement in the signal detection and thus the sensitivity performance of the CS based receiver are presented.