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260 results on '"Chip multiprocessor"'

2. A Study on Requests Serialization in Directory-Based Protocol for MESI Cache Coherence Protocol

Author

Yadav, Sonal, Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Kumar, Rajesh, editor, Ahn, Chang Wook, editor, Sharma, Tarun K., editor, Verma, Om Prakash, editor, and Agarwal, Anand, editor

Published
2022
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3. Congestion aware low power on chip protocols with network on chip with cloud security

Author

Suresh Ponnan, Tikkireddi Aditya Kumar, Hemakumar VS, Sakthieswaran Natarajan, and Mohd Asif Shah

Subjects
Network-on-Chip, System on Chip, Chip multiprocessor, Congestion, Long term evolution, Embedded transition inversion, Computer engineering. Computer hardware, TK7885-7895, Electronic computers. Computer science, QA75.5-76.95
Abstract

Abstract This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors. This paper aims to research the advantages and disadvantages of low congestion protocols on highway environments like multiple master multiple slave interconnections. A long-term evolution and effective on-chip connectivity solution for secured, congestion aware and low power architecture is emerged for Network-on-Chip (NoC) for MCSoC. Applications running simultaneously on a different chip are often exchanged dynamically on the chip network. Of-course, in general on chip communication, resources mean that applications may interact with shared resources to influence each other's time characteristics.

Published
2022
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5. Congestion aware low power on chip protocols with network on chip with cloud security.

Author

Ponnan, Suresh, Kumar, Tikkireddi Aditya, VS, Hemakumar, Natarajan, Sakthieswaran, and Shah, Mohd Asif

Subjects
NETWORKS on a chip, COMPUTER network protocols, COMPUTER architecture, VERY large scale circuit integration, LONG-Term Evolution (Telecommunications), SYSTEMS on a chip
Abstract

This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors. This paper aims to research the advantages and disadvantages of low congestion protocols on highway environments like multiple master multiple slave interconnections. A long-term evolution and effective on-chip connectivity solution for secured, congestion aware and low power architecture is emerged for Network-on-Chip (NoC) for MCSoC. Applications running simultaneously on a different chip are often exchanged dynamically on the chip network. Of-course, in general on chip communication, resources mean that applications may interact with shared resources to influence each other's time characteristics. [ABSTRACT FROM AUTHOR]

Published
2022
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6. Efficient classification of private memory blocks.

Author

Upadhyay, Bhargavi R., Ros, Alberto, and Shah, Jalpa

Subjects
*MULTICORE processors, *CLASSIFICATION, *MEMORY, *MATHEMATICAL optimization, *MULTIPROCESSORS
Abstract

• Private/shared data classification is proposed to enhance system optimizations. • The block classification removes miss-classification of page granularity schemes. • Optimizations are proposed to reduce the overheads of block-grain classification. • We simulate 15 parallel benchmarks for a 16-core CMP multiprocessor. • The proposed work improves system performance by 8.0% to a page-grain scheme. Shared memory architectures are pervasive in the multicore technology era. Still, sequential and parallel applications use most of the data as private in a multicore system. Recent proposals using this observation and driven by a classification of private/shared memory data can reduce the coherence directory area or the memory access latency. The effectiveness of these proposals depends on the accuracy of the classification. The existing proposals perform the private/shared classification at page granularity, leading to a miss-classification and reducing the number of detected private memory blocks. We propose a mechanism able to accurately classify memory blocks using the existing translation lookaside buffers (TLB), which increases the effectiveness of proposals relying on a private/shared classification. Our experimental results show that the proposed scheme reduces L1 cache misses by 25% compared to a page-grain classification approach, which translates into an improvement in system performance by 8.0% with respect to a page-grain approach. [ABSTRACT FROM AUTHOR]

Published
2021
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7. Near-optimal replacement policies for shared caches in multicore processors.

Author

Díaz, Javier, Ibáñez, Pablo, Monreal, Teresa, Viñals, Víctor, and Llabería, José M.

Subjects
*CACHE memory, *MULTICORE processors, *FAIRNESS
Abstract

An optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches because replacement decisions alter this future sequence. We present a novel near-optimal policy for minimizing the miss rate in a shared cache that approaches the optimal execution iteratively. During each iteration, the future access sequence is reconstructed on every miss interleaving the future per-core sequences, taken from the previous iteration. This single sequence feeds a classical private-cache optimum replacement policy. Our evaluation on a shared last-level cache shows that our proposal iteratively converges to a near-optimal miss rate that is independent of the initial conditions, within a margin of 0.1%. The best state-of-the-art online policies achieve around 65% of the miss rate reduction obtained by our near-optimal proposal. In a shared cache, miss rate optimization does not imply the optimization of other metrics. Therefore, we also propose a new near-optimal policy to maximize fairness between cores. The best state-of-the-art online policy achieves 60% of the improvement in fairness seen with our near-optimal policy. Our proposals are useful both for setting upper performance bounds and inspiring implementable mechanisms for shared caches. [ABSTRACT FROM AUTHOR]

Published
2021
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8. Dynamic scheduling in multicore processors

Author

Rosas Ham, Demian and Watson, Ian

Subjects
004.1, Dynamic Load Balancing, Chip Multiprocessor
Abstract

The advent of multi-core processors, particularly with projections that numbers of cores will continue to increase, has focused attention on parallel programming. It is widely recognized that current programming techniques, including those that are used for scientific parallel programming, will not allow the easy formulation of general purpose applications. An area which is receiving interest is the use of programming styles which do not have side-effects. Previous work on parallel functional programming demonstrated the potential of this to permit the easy exploitation of parallelism. This thesis investigates a dynamic load balancing system for shared memory Chip Multiprocessors. This system is based on a parallel computing model called SLAM (Spreading Load with Active Messages), which makes use of functional language evaluation techniques. A novel hardware/software mechanism for exploiting fine grain parallelism is presented. This mechanism comprises a runtime system which performs dynamic scheduling and synchronization automatically when executing parallel applications. Additionally the interface for using this mechanism is provided in the form of an API. The proposed system is evaluated using cycle-level models and multithreaded applications running in a full system simulation environment.

Published
2012

9. Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors

Author

Choudhury, Avishek, Sikdar, Biplab K., Barbosa, Simone Diniz Junqueira, Series editor, Chen, Phoebe, Series editor, Filipe, Joaquim, Series editor, Kotenko, Igor, Series editor, Sivalingam, Krishna M., Series editor, Washio, Takashi, Series editor, Yuan, Junsong, Series editor, Zhou, Lizhu, Series editor, Kaushik, Brajesh Kumar, editor, Dasgupta, Sudeb, editor, and Singh, Virendra, editor

Published
2017
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11. Novel fairness-aware co-scheduling for shared cache contention game on chip multiprocessors.

Author

Xiao, Zheng, Chen, Liwen, Wang, Bangyong, Du, Jiayi, and Li, Keqin

Subjects
*MULTIPROCESSORS, *NASH equilibrium, *GAMES, *SHARED workspaces
Abstract

• Propose a novel fairness-aware thread co-scheduling model using non-cooperative game. • Algorithm IA is proposed to solve the Nash equilibrium of non-cooperative game model. • It is theoretically proved that IA has a potential game process and it can converge to Nash equilibrium. • IA is further enhanced by cache partition, reducing the number of misses under the shared cache. Threads running on different cores of chip multiprocessors (CMP) can cause thread performance degradation due to contention for shared resources such as shared L2 cache. Some studies have shown that thread co-scheduling can effectively reduce contention for shared resources. However, in a multi-core system with shared caches, mutual interference between threads is unpredictable. As the number of cores increases, we are unlikely to exhaust all possible co-scheduling schemes. In this paper, a novel fairness-aware thread co-scheduling algorithm base on non-cooperative game is proposed to reduce L2 cache misses. We tried to improve the overall performance of the system by scheduling threads fairly. The originality of this work is to model thread scheduling using a non-cooperative game. The execution time of a thread varies depending on which threads are running on other cores of the same chip, because different thread combinations result in different levels of cache contention. Given the interdependence and competition between threads on the CMP architecture, non-cooperative game is used to solve the problem of thread co-scheduling where each thread is considered as a participant in the game. An iterative algorithm (IA) is proposed to solve the Nash equilibrium of the non-cooperative game in this paper. Subsequently, it is theoretically proved that IA has a potential game process and finally proves that IA can converge to Nash equilibrium in N iterations, where N is the number of threads. The co-scheduling scheme of all threads is obtained by solving the Nash equilibrium of the IA. Finally, the convergence and effectiveness of IA proposed in this paper is verified by experiments. In addition, we use the cache partition to improve the performance of IA. Experimental results show that the number of total cache misses of IA is less than that of the default scheduling algorithm, IA combined with cache partitioning can further reduce the total cache misses. [ABSTRACT FROM AUTHOR]

Published
2020
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12. Co-scheduling HPC workloads on cache-partitioned CMP platforms.

Author

Aupy, Guillaume, Benoit, Anne, Goglin, Brice, Pottier, Loïc, Robert, Yves, Dongarra, Jack, and Tourancheau, Bernard

Subjects
*HIGH performance computing, *HUMAN behavior models, *MULTIPROCESSORS, *ADVENT
Abstract

With the recent advent of many-core architectures such as chip multiprocessors (CMPs), the number of processing units accessing a global shared memory is constantly increasing. Co-scheduling techniques are used to improve application throughput on such architectures, but sharing resources often generates critical interferences. In this article, we focus on the interferences in the last level of cache (LLC) and use the Cache Allocation Technology (CAT) recently provided by Intel to partition the LLC and give each co-scheduled application their own cache area. We consider m iterative HPC applications running concurrently and answer to the following questions: (i) How to precisely model the behavior of these applications on the cache-partitioned platform? and (ii) how many cores and cache fractions should be assigned to each application to maximize the platform efficiency? Here, platform efficiency is defined as maximizing the performance either globally, or as guaranteeing a fixed ratio of iterations per second for each application. Through extensive experiments using CAT, we demonstrate the impact of cache partitioning when multiple HPC applications are co-scheduled onto CMP platforms. [ABSTRACT FROM AUTHOR]

Published
2019
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13. A thermal-sensitive design of a 3D torus-based optical NoC architecture.

Author

Ye, Yaoyao and Zhang, Zhe

Subjects
*ARCHITECTURE, *OPTICAL switching, *TRAFFIC patterns, *ROUTING algorithms, *OPTICAL losses, *SYSTEMS on a chip, *NETWORK routers
Abstract

In order to overcome limitations of traditional electronic interconnects in terms of power efficiency and bandwidth density, optical networks-on-chip (NoC) based on silicon photonics have been proposed as an emerging on-chip communication architecture for chip multiprocessors (CMPs) with large core counts. However, due to thermo-optic effects, wavelength-selective silicon photonic devices such as microresonators suffer from temperature-dependent wavelength shift. In this work, we propose a thermal-sensitive design of a 3D torus-based optical NoC architecture. For the 3D torus-based optical NoC architecture, we propose a hybrid optical-electronic router architecture with a fully-connected 7 × 7 optical switching fabric. Besides, a thermal-sensitive routing algorithm is proposed to optimize the optical power loss in the presence of on-chip temperature variations. Simulation results show that for a set of synthetic traffic patterns, the proposed 3D torus-based optical NoC with the thermal-sensitive routing reduces the average thermal-induced optical power loss by 14.3% and 17% respectively as compared to the matched 3D torus-based optical NoC and the 3D mesh-based optical NoC with the traditional XYZ routing. For a set of real applications, the proposed 3D torus-based optical NoC with the thermal-sensitive routing reduces the worst-case optical power loss by 7.9% and 14.6% respectively as compared to the matched 3D torus-based optical NoC and the 3D mesh-based optical NoC with the traditional XYZ routing. • A thermal-sensitive design approach of a 3D torus-based optical NoC architecture is proposed. • A hybrid optical-electronic router architecture with a fully-connected 7 × 7 optical switching fabric is proposed. • A SystemC-based cycle-accurate network simulator is developed for the 3D torus-based optical NoC. [ABSTRACT FROM AUTHOR]

Published
2019
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14. ReD: A reuse detector for content selection in exclusive shared last-level caches.

Author

Díaz, Javier, Monreal, Teresa, Ibáñez, Pablo, Llabería, José M., and Viñals, Víctor

Subjects
*CACHE memory, *STREAMING technology, *MULTIPROCESSORS, *INFORMATION technology, *COMPUTER storage devices
Abstract

Abstract The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive caches. In this paper, we propose the Reuse Detector (ReD), a new content selection mechanism for exclusive hierarchies that leverages reuse locality at the SLLC, a property that states that blocks referenced more than once are more likely to be accessed in the near future. Being placed between each L2 private cache and the SLLC, ReD prevents the insertion of blocks without reuse into the SLLC. It is designed to overcome problems affecting similar recent mechanisms (low accuracy, reduced visibility window and detector thrashing). ReD improves performance over other state-of-the-art proposals (CHAR, Reuse Cache and EAF cache). Compared with the baseline system with no content selection, it reduces the SLLC miss rate (MPI) by 10.1% and increases harmonic IPC by 9.5%. Highlights • ReD is a Reuse Detector that exploits the reuse locality in the SLLC request stream. • Placed between each L2 and the SLLC, it forces useless blocks to bypass the latter. • ReD has a large detection window, bypasses with accuracy, and resists trashing. • It reduces the SLLC miss rate by 10.1% and increases harmonic IPC by 9.5%. [ABSTRACT FROM AUTHOR]

Published
2019
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15. Introduction

Author

Bergman, Keren, Carloni, Luca P., Biberman, Aleksandr, Chan, Johnnie, Hendry, Gilbert, Chandrakasan, Anantha P., Series editor, Bergman, Keren, Carloni, Luca P., Biberman, Aleksandr, Chan, Johnnie, and Hendry, Gilbert

Published
2014
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16. Data Access Type Aware Replacement Policy for Cache Clustering Organization of Chip Multiprocessors

Author

Li, Chongmin, Wang, Dongsheng, Wang, Haixia, Li, Guohong, Xue, Yibo, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Wu, Chenggang, editor, and Cohen, Albert, editor

Published
2013
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17. OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access

Author

Xu, Thomas Canhao, Liljeberg, Pasi, Plosila, Juha, Tenhunen, Hannu, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Malyshkin, Victor, editor

Published
2013
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18. Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor

Author

Talpur, Shahnawaz, Shi, Feng, Wang, Yizhuo, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Park, James J., editor, Zomaya, Albert, editor, Yeo, Sang-Soo, editor, and Sahni, Sartaj, editor

Published
2012
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19. Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors

Author

Shafiee, Ali, Shahidi, Narges, Baniasadi, Amirali, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Varbanescu, Ana Lucia, editor, Molnos, Anca, editor, and van Nieuwpoort, Rob, editor

Published
2012
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20. Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors

Author

Khan, Omer, Kundu, Sandip, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, and Stenström, Per, editor

Published
2011
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21. A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors

Author

Aliee, Hananeh, Zarandi, Hamid Reza, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Flammini, Francesco, editor, Bologna, Sandro, editor, and Vittorini, Valeria, editor

Published
2011
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22. Exploring the Architecture of a Stream Register-Based Snoop Filter

Author

Blumrich, Matthias, Salapura, Valentina, Gara, Alan, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, and Stenström, Per, editor

Published
2011
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23. Comparing Scalability Prediction Strategies on an SMP of CMPs

Author

Singh, Karan, Curtis-Maury, Matthew, McKee, Sally A., Blagojević, Filip, Nikolopoulos, Dimitrios S., de Supinski, Bronis R., Schulz, Martin, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, D’Ambra, Pasqua, editor, Guarracino, Mario, editor, and Talia, Domenico, editor

Published
2010
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24. Scalable Shared-Cache Management by Containing Thrashing Workloads

Author

Xie, Yuejian, Loh, Gabriel H., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Patt, Yale N., editor, Foglia, Pierfrancesco, editor, Duesterwald, Evelyn, editor, Faraboschi, Paolo, editor, and Martorell, Xavier, editor

Published
2010
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25. Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors

Author

Jiang, Yunlian, Tian, Kai, Shen, Xipeng, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Patt, Yale N., editor, Foglia, Pierfrancesco, editor, Duesterwald, Evelyn, editor, Faraboschi, Paolo, editor, and Martorell, Xavier, editor

Published
2010
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26. Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors

Author

Feng, Shuguang, Gupta, Shantanu, Ansari, Amin, Mahlke, Scott, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Patt, Yale N., editor, Foglia, Pierfrancesco, editor, Duesterwald, Evelyn, editor, Faraboschi, Paolo, editor, and Martorell, Xavier, editor

Published
2010
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27. Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines.

Author

Deb, Dipika, Jose, John, Das, Shirshendu, and Kapoor, Hemangee K.

Subjects
*COMPLEMENTARY metal oxide semiconductors, *ELECTRIC lines, *NETWORKS on a chip, *ADAPTIVE routing (Computer network management), *ROUTING (Computer network management), *DATA packeting
Abstract

Abstract Advancements in CMOS technology led to the increase in number of processing cores on a single chip. Communication between different cores in such multicore systems is facilitated by an underlying interconnect. Due to the limitations of traditional bus-based system Network on Chip (NoC) based interconnect is the most acceptable cost effective framework for inter-core communication. A packet in an NoC travels through a sequence of intermediate routers before arriving at its destination. As the size of NoC scales high, the average number of intermediate routers that a packet traverse also increases. This results in higher packet latency which degrades application performance. In this work, we introduce cost effective adaptive routing techniques that can forward long distance packets through specialized channels made of Transmission Line (TL). These extra TLs introduced in the chip reduce the diameter of the network thereby reducing average packet latency. We propose two novel router architectures; SBTR and e-SBTR that reduce packet latency by reducing the number of intermediate hops. We use PARSEC benchmark and SPEC CPU 2006 benchmark mixes to evaluate the performance of our proposed techniques. SBTR and e-SBTR reduce average packet latency by 7.9% and 25% respectively. Both the techniques also reduce average hop count by 8.13% and 27.6% respectively. We also observe that our proposed technique e-SBTR performs better than the state-of-the-art Express Virtual Channel technique in terms of packet latency and hop count respectively. Highlights • Long distance on-chip communication degrades the performance of NoC in CMP. • We propose a hybrid NoC architecture with high speed Transmission Line (TL). • An adaptive routing technique (SBTR) is proposed to send long distance packets with TL. • An improved hybrid mechanism called e-SBTR is also proposed in this paper. • The proposed techniques are compared and combined with an existing technique. [ABSTRACT FROM AUTHOR]

Published
2019
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28. Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems.

Author

Arslan, Huseyin G., Yu-Chu Tian, Fenglian Li, Chen Peng, and Min-Rui Fei

Subjects
*MULTIPROCESSORS, *INTEGRATED circuits, *DATA, *ADAPTIVE computing systems, *CACHE memory
Abstract

In chip multiprocessor scheduling, cache memory awareness is critical. However, most existing cache-aware multiprocessor scheduling methods are static and open-loop and thus do not work well in dynamic environments. To address this challenging problem, a control-theoretic approach is presented in this paper for adaptive cache-fair multiprocessor scheduling. The adaptive cache-fair multiprocessor scheduling uses process models to estimate the shared cache size requirements and the instruction count variations of the threads running on multiprocessor cores. Then, it feeds the estimated information back to an adaptive controller. Designed from the process models, the controller decides processor cycle re-allocation through model computation to maintain the instruction counts of the multiple threads at their desired values. The effectiveness of the adaptive cache-fair multiprocessor scheduling is demonstrated through examples. [ABSTRACT FROM AUTHOR]

Published
2018
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30. Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs

Author

Lira, Javier, Molina, Carlos, González, Antonio, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sips, Henk, editor, Epema, Dick, editor, and Lin, Hai-Xiang, editor

Published
2009
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31. SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework

Author

Feng, Degui, Jiang, Guanjun, Zhang, Tiefei, Hu, Wei, Chen, Tianzhou, Cao, Mingteng, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Dou, Yong, editor, Gruber, Ralf, editor, and Joller, Josef M., editor

Published
2009
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32. The Deferred Event Model for Hardware-Oriented Spiking Neural Networks

Author

Rast, Alexander, Jin, Xin, Khan, Mukaram, Furber, Steve, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Köppen, Mario, editor, Kasabov, Nikola, editor, and Coghill, George, editor

Published
2009
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33. ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors

Author

Hammoud, Mohammad, Cho, Sangyeun, Melhem, Rami, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Seznec, André, editor, Emer, Joel, editor, O’Boyle, Michael, editor, Martonosi, Margaret, editor, and Ungerer, Theo, editor

Published
2009
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34. Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

Author

Ding, Yang, Kandemir, Mahmut, Irwin, Mary Jane, Raghavan, Padma, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Seznec, André, editor, Emer, Joel, editor, O’Boyle, Michael, editor, Martonosi, Margaret, editor, and Ungerer, Theo, editor

Published
2009
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36. Evaluating OpenMP on Chip MultiThreading Platforms

Author

Liao, Chunhua, Liu, Zhenying, Huang, Lei, Chapman, Barbara, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Mueller, Matthias S., editor, Chapman, Barbara M., editor, de Supinski, Bronis R., editor, Malony, Allen D., editor, and Voss, Michael, editor

Published
2008
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37. Evaluation of Sparse LU Factorization and Triangular Solution on Multicore Platforms

Author

Li, Xiaoye Sherry, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Palma, José M. Laginha M., editor, Amestoy, Patrick R., editor, Daydé, Michel, editor, Mattoso, Marta, editor, and Lopes, João Correia, editor

Published
2008
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38. Adaptive L2 Cache for Chip Multiprocessors

Author

Benítez, Domingo, Moure, Juan C., Rexachs, Dolores I., Luque, Emilio, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bougé, Luc, editor, Forsell, Martti, editor, Träff, Jesper Larsson, editor, Streit, Achim, editor, Ziegler, Wolfgang, editor, Alexander, Michael, editor, and Childs, Stephen, editor

Published
2008
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39. FROCM: A Fair and Low-Overhead Method in SMT Processor

Author

Chen, Shuming, Ma, Pengyong, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Perrott, Ronald, editor, Chapman, Barbara M., editor, Subhlok, Jaspal, editor, de Mello, Rodrigo Fernandes, editor, and Yang, Laurence T., editor

Published
2007
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40. Supporting Speculative Multithreading on Simultaneous Multithreaded Processors

Author

Packirisamy, Venkatesan, Wang, Shengyue, Zhai, Antonia, Hsu, Wei-Chung, Yew, Pen-Chung, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Robert, Yves, editor, Parashar, Manish, editor, Badrinath, Ramamurthy, editor, and Prasanna, Viktor K., editor

Published
2006
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41. Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor

Author

Stavrou, Kyriakos, Trancoso, Pedro, Evripidou, Paraskevas, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Jesshope, Chris, editor, and Egan, Colin, editor

Published
2006
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42. Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors

Author

Hasasneh, Nabil, Bell, Ian, Jesshope, Chris, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Dough, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Grass, Werner, editor, Sick, Bernhard, editor, and Waldschmidt, Klaus, editor

Published
2006
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43. Conclusions

Author

Bergman, Keren, Carloni, Luca P., Biberman, Aleksandr, Chan, Johnnie, Hendry, Gilbert, Chandrakasan, Anantha P., Series editor, Bergman, Keren, Carloni, Luca P., Biberman, Aleksandr, Chan, Johnnie, and Hendry, Gilbert

Published
2014
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50. Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches.

Author

Li, Jianhua, Li, Minming, Xue, Chun Jason, Ouyang, Yiming, and Shen, Fanfan

Subjects
*NON-uniform memory access, *CACHE memory, *MULTIPROCESSORS, *PARALLEL processing, *RUN time systems (Computer science)
Abstract

Non-Uniform Cache Architecture (NUCA) is a viable solution to mitigate the problem of large on-chip wire delay due to the rapid increase in the cache capacity of chip multiprocessors (CMPs). Through partitioning the last-level cache (LLC) into smaller banks connected by on-chip network, the access latency will exhibit non-uniform distribution. Various works have well explored the NUCA design, including block migration, block replication and block searching. However, all of the previous mechanisms designed for NUCA are thread-oblivious when multi-threaded applications are deployed on CMP systems. Due to the interference on shared resources, threads often demonstrate unbalanced progress wherein the lagging threads with slow progress are more critical to overall performance. In this paper, we propose a novel NUCA design called thread Criticality Assisted R eplication and Migration (CARM). CARM exploits the runtime thread criticality information as hints to adjust the block replication and migration in NUCA. Specifically, CARM aims at boosting parallel application execution through prioritizing block replication and migration for critical threads. Full-system experimental results show that CARM reduces the execution time of a set of PARSEC workloads by 13.7 and 6.8 percent on average compared with the tradition D-NUCA and Re-NUCA respectively. Moreover, CARM also consumes much less energy compared with the evaluated schemes. [ABSTRACT FROM AUTHOR]

Published
2017
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