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Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35 μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18 μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures. [ABSTRACT FROM AUTHOR]

Different aspects of the integration of strontium bismuth tantalate (SBT)-based high-density ferroelectric random access memory (FeRAM) is discussed in relation to the fabrication of pseudo-three-dimensional (3D) cell structure. The excellent electrical and reliability properties of the small integrated FeCAP prove the feasibility of the technology, while the verification of the potential electrical 3D effect confirms the basic scaling potential of the concept beyond that of the single-mask capacitor.

Objective To analyse the anatomical, functional and quality-of-life results when using bioactive glass in mastoid and epitympanic obliteration. Design Prospective clinical study. Setting Tertiary referral centre. Participants Forty-one cases (39 patients) operated between May 2013 and January 2015. Main outcome measures Anatomical results were evaluated by otomicroscopy 1 year after surgery and using imaging to detect residual disease. Functional results were studied by postoperative hearing gain. Quality of life was assessed with the Glasgow Benefit Inventory questionnaire and the success of surgery by a surgery-specific questionnaire. Results At 1 year, all patients presented a well-healed external auditory canal, with an intact tympanic membrane. In cases with cholesteatoma ( n = 23), no recurrent retraction pockets or residual disease were observed on imaging studies. The overall air-bone gap closure was 7.7 ± 1.84 dB (mean ± se of the mean, P < 0.001, paired t-test). No significant differences were found on hearing results when comparing primary versus revision surgery, canal-wall-up versus canal-wall-down obliterations, type of tympanoplasty and presence of cholesteatoma (multifactor anova). The Glasgow Benefit Inventory improved with an average score of 28 and the success of surgery questionnaire showed a significant improvement in ear discharge and a moderate improvement in hearing and equilibrium. Conclusions The use of bioactive glass for mastoid and epitympanic obliteration in canal-wall-down or canal-wall-up tympanoplasties is an effective procedure in both primary and revision surgery. The anatomical and functional results appear to be well correlated with patient experience and to the improvement in quality of life. [ABSTRACT FROM AUTHOR]

This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μm CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excellent results are presented for the etch process to form the contacts to the electrodes. [ABSTRACT FROM AUTHOR]

The effect of a thin Ta layer at the Si/Ti interface on the intermediate phase formation has been studied in detail by in situ sheet resistance, x-ray diffraction, transmission electron microscopy and Rutherford backscattering spectroscopy of partially reacted samples. When a Ta layer is deposited at the Si/Ti interface, a new intermediate phase has been detected, i.e. the hexagonal TiSi[sub 2] C40. This phase grows on the C40-TaSi[sub 2] that is formed at the interface with silicon. The lattice parameters of the C40-TiSi[sub 2] obtained by ab initio calculations agree quite well with the experimental ones. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]