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Atomic layer etching (ALE) can result from sequential, self-limiting thermal reactions. The reactions during thermal ALE are defined by fluorination followed by ligand exchange using metal precursors. The metal precursors introduce various ligands that may transfer during ligand exchange. If the transferred ligands produce stable and volatile metal products, then the metal products may leave the surface and produce etching. In this work, selectivity in thermal ALE was examined by exploring tin(II) acetylacetonate (Sn(acac)2), trimethylaluminum (TMA), dimethylaluminum chloride (DMAC), and SiCl4 as the metal precursors. These metal precursors provide acac, methyl, and chloride ligands for ligand exchange. HF-pyridine was employed as the fluorination reagent. Spectroscopic ellipsometry was used to measure the etch rates of Al2O3, HfO2, ZrO2, SiO2, Si3N4, and TiN thin films on silicon wafers. The spectroscopic ellipsometry measurements revealed that HfO2 was etched by all of the metal precursors. Al2O3 was et...

Two-dimensional (2D) metal dichalcogenides like molybdenum disulfide (MoS2) may provide a pathway to high-mobility channel materials that are needed for beyond-complementary metal-oxide-semiconductor (CMOS) devices. Controlling the thickness of these materials at the atomic level will be a key factor in the future development of MoS2 devices. In this study, we propose a layer-by-layer removal of MoS2 using the atomic layer etching (ALET) that is composed of the cyclic processing of chlorine (Cl)-radical adsorption and argon (Ar)(+) ion-beam desorption. MoS2 etching was not observed with only the Cl-radical adsorption or low-energy (

This article describes less explored solutions to improve interconnect performance without changing established steps (etch, strip, clean, CMP) in a sub-100nm integration route. Process conditions of the porogen-based low-k are adjusted by (1) varying the curing time (2) adding a thermal anneal step prior to CuO reduction or (3) depositing a capping layer on top of the low-k after curing. The low-k material examined in this study is Aurora^(R) ELK HM (k~2.5). The integration process was robust against these variations, showing good electrical yield for all process splits. RC-product was improved when using a shorter curing time and when an anneal step prior to CuO reduction was performed. The use of a thicker capping layer decreased capacitance, showing an improved protection against damage.

Two-dimensional (2D) metal dichalcogenides like molybdenum disulfide (MoS2) may provide a pathway to high-mobility channel materials that are needed for beyond-complementary metal-oxide-semiconductor (CMOS) devices. Controlling the thickness of these materials at the atomic level will be a key factor in the future development of MoS2 devices. In this study, we propose a layer-by-layer removal of MoS2 using the atomic layer etching (ALET) that is composed of the cyclic processing of chlorine (Cl)-radical adsorption and argon (Ar)(+) ion-beam desorption. MoS2 etching was not observed with only the Cl-radical adsorption or low-energy (20 eV) Ar(+) ion-beam desorption steps; however, the use of sequential etching that is composed of the Cl-radical adsorption step and a subsequent Ar(+) ion-beam desorption step resulted in the complete etching of one monolayer of MoS2. Raman spectroscopy, X-ray photoelectron spectroscopy (XPS), and atomic force microscopy (AFM) indicated the removal of one monolayer of MoS2 with each ALET cycle; therefore, the number of MoS2 layers could be precisely controlled by using this cyclical etch method. In addition, no noticeable damage or etch residue was observed on the exposed MoS2.

Controlled layer by layer material removal will be required for device fabrication in the future. Atomic level etch is a promising path to answer the processing demands of thin high mobility channel devices on the angstrom scale. Self-limiting reactions, discrete reaction & activation steps, or extremely low ion energy etch plasmas are some of the pathways being pursued for precise sub-nanometer material removal. Critical etch applications that require atomic layer control will be discussed, and promising approaches towards atomic layer etch will be reviewed in this talk.

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility.

We report a record low contact resistivity of sub-1.0×10−8 Ω.cm2 realized on n+ In 0.53 Ga 0.47 As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III–V on Si substrates. A novel low-damage III–V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III–V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (−60%).

We have investigated the growth mechanism of ALD-TiN film on different dielectrics and the resulting effective work function value. TiN nucleation rate and growth rate are found to be dependent on the dielectric films. TiN growth mechanism changed from 3-D type on SiO 2 to layer-by-layer type on HfO 2 . The minimum TiN thickness required for a complete surface coverage varies according to the growth mechanism. Capacitor (MOSCAP) characterization revealed that the effective work function of TiN is dependent not only on dielectric films but also on the TiN thickness. The behavior of work function and fixed charge correlated with the growth mechanism of TiN on dielectric films.

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρc) extraction of 2×10-8Ω cm2 and 5×10-9Ω cm2 for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρc values. The results show the importance of such test structures to accurately extract ultralow ρc values relevant to sub-14-nm technology nodes.

This paper reports tri-gate sub-100 nm In0.53Ga0.47As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of gm, max > 1.5 mS/μm, at VDS = 0.5 V. This result is the best balance of gm, max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ0 = 760 cm2/V-s and peak vx0 = 1.6×107 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.

Parasitic resistance (Rpara) is a grand challenge to successfully hetero-integrate III-V channels onto Si for CMOS application. Here, we report the first statistical IDsat comparison for non-self-aligned and self-aligned contacts of In0.53Ga0.47As MOSFETs fabricated on large scale Si substrates with VLSI toolsets. We compare non-self-aligned Mo and self-aligned Ni-InGaAs contacts. Devices with self-aligned contacts exhibit a 25% enhancement in IDsat over devices with non-self-aligned contacts largely due to the 27% reduction in Rpara. We have also extended the thermal stability of Ni-InGaAs to 500 °C (highest reported) enabling it to be compatible with BEOL processes. The impact of the Ni-InGaAs process module on tool contamination is discussed. These results represent significant progress towards establishing a path to a unified Ni-based S/D contact module for Si/SiGe/Ge/III-V co-integration on VLSI platforms.

In this letter, it is shown that for fin widths down to and (100)/ fin surface/direction, respectively. Although PMOS FinFET mobility is degraded by 35% for [110]/ fins, it is enhanced by up to 30% for (100)/ fins. These results can be qualitatively explained using the bulk-Si piezoresistance coefficients.

The superior transport properties of III–V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III–V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj

The material properties of two ultra low-k organic polymers are characterized for copper interconnect integration. The k-values are 2.2-2.3 for both. Compared to OSG materials of similar k-values, these polymers have lower porosity and smaller pore size, achieved using selfassembled chemistry. Both materials demonstrate excellent resistance to plasma damage: no water uptake was detected after exposure to selected etching plasmas. This characteristic, combined with the small pore size and low porosity, results in the successful integration of the organic low-ks in 80 nm spacing with no significant increase in the integrated k-values.It is found that higher open porosity in polymer A is accompanied by higher leakage current, which is not however linked to lower dielectric breakdown lifetimes.

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (Rext) be minimized. Among the different components of Rext, contact resistance (RC ), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower RC . However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low RC . In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-V). In this paper, we will review these RC reduction options and present some of our recent results on contact/junction engineering to lower RC in III-V MOSFETs.

Atomic Layer Etch (ALEt) and Atomic Layer Clean (ALC) are emerging as enabling technologies for sub-10 nm technology nodes. At these scales, performance will depend critically on process variations, and novel technologies will thus be required to meet process and device specifications without increasing complexity. At even more aggressive nodes, where novel 2D materials are being considered, the need for zero damage and quasi-infinite selectivity during etch and clean processes becomes increasingly important. Generation of an improved fundamental understanding and control of surface reactions and interactions at the atomic scale is needed to make possible the controllable fabrication of nm and sub-nm devices, and, in addition, could offer a pathway to new materials, devices, and applications. Atomic layer etch and clean are the most promising routes for delivering the precision needed at nm and sub-nm length scales. However, if implementation of these technologies is to be realized in integrated circuit manufacturing, many aspects of ALEt and ALC must be better understood and further process development undertaken. The articles in this focus issue address many of the current and anticipated process challenges, including surface reaction control, plasma source design, and selective chemistry strategies. Specifically, a wide range of materials and applications are discussed, from traditional silicon and silicon dioxide layers to the more specialized metal dichalcogenides. Approaches described include plasma systems that can deliver ex

This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ~plusmn0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack

We report a thermally stable N-metal process in which surface passivation of HfSiO dielectric using thin layers of La2O3, deposited by either MBE or PVD, significantly shifts the metal gate effective work function toward the Si conduction band edge. Well-behaved transistors with Lg down to 70 nm have been fabricated with threshold voltage of 0.25V, mobility up to 92% of the universal SiO2 mobility, and Tinv ~1.6 nm

Systematic analysis of the influence of nitrogen on the work function of TaN, HfN, and HfTiN was performed. It was observed that the effective work function of these materials could be modulated by /spl sim/300 meV by varying the nitrogen content in the film even after 1000 /spl deg/C anneal. Additionally, there is minimal observable influence of high nitrogen flow rates during the plasma deposition of metal nitrides on the integrity of the hafnium based high-k dielectrics.

A material system Ru-Hf alloys was evaluated for its potential as future generation dual-metal CMOS electrode. It was observed that the effective work function of the alloy could be modulated from 4.3 to 4.8 eV by varying the Hf content in the Ru-Hf alloy from 65% to 0%. Additionally, comparison between the Ru-Hf (1:1) with Ru-Ta (1:1) suggests that the two alloy systems exhibit similar behavior in work function modulation.

Select amorphous metals (transition-metal-silicon-nitride: TaSiN, MoSiN, HfSiN, TiSiN), were systematically evaluated for their electrical (effective work function) and physical (XRD, HRTEM, HAADF-STEM, EELS) properties. Effective work function values spanning 4.16 to 4.8 eV were observed for these materials after a 1000/spl deg/C anneal and on both SiO/sub 2/ and Hf based high-k dielectrics, making them attractive candidates for future generation CMOS metal gates.

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

We show an ALD based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability. Furthermore, the HfSiON dielectric films are integrated in a gate first approach that includes a 1000degC-5s anneal. It is also demonstrated that this 1 nm EOT HfSiON can achieve electron and hole mobilities comparable to that of SiON. This progress is enabled due to better understanding of the relationship between charge trapping, HfSiON thickness and crystallinity. Performance and reliability improvement is attributed to reduced charge trapping due to suppressed crystallization of the optimized HfSiON films

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

An advanced organic polymer material of k = 2.2 has been successfully integrated in Cu lines with dielectric spacing from 80 to 20 nm. Cu lines with both TaN/Ta barrier and no barrier were fabricated. Current–voltage (I–V) and time dependent dielectric breakdown (TDDB) measurements were performed to study the scalability of this material. In the case of TaN/Ta barrier, no TDDB degradation was observed at 100 °C as the dielectric spacing changed from 80 to 30 nm. In the case of no barrier, TDDB performance at 100 °C was better than that of SiO2 without a barrier. However, TDDB at 200 °C showed a clear degradation. In contrast, no such degradation was present when TaN/Ta barrier was used.

This paper discusses integration aspects of a porous low-k film (k ∼2.45) cured with a broadband UV lamp. Different process splits are discussed which could contribute to avoid integration induced damage and improve reliability. The main factor contributing to a successful integration is the presence of a thick (protecting) cap layer partially remaining after chemical mechanical polishing (CMP), which leads to yielding structures with a k eff of ∼2.6, a breakdown voltage of ∼6.9 MV/cm and time dependent dielectric breakdown (TDDB) lifetimes in the excess of 100 years. Long thermal anneals restore the k-value but degrade lifetime.

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

Plasma carbonization was used to study the effect of carbon incorporation on the work function of metal nitride gates. The work functions were shifted by as much as 200 mV upon the incorporation of 8% carbon. X-ray photoelectron spectroscopy shows that these shifts in the work function values are mainly driven by the formation of metal-carbon and carbon-carbon bonds in the metal gate. In particular, the work function decreased with increasing the metal-carbon bond concentration, reaching as low as 4.28 eV for TaC with 50% carbon. This correlation of bonding with the work function can be used to tune the work function of metal gates.

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The formation of a carbonized layer in positive photoresist after high dose ion implants has been studied as a function of the implant parameters. In this study SEM observations of the carbonized layer were used to confirm that the physical scattering characteristics of the ions within the photoresist determine the extent to which the carbonization, or increase of the relative carbon concentration, can occur. The thickness of the carbonized layer was found to be directly dependent on the energy and atomic species of the ions, and to be relatively independent of the ion beam current and the total ion dose. The role of the ion dosage in the formation of the carbonized layer is discussed, and the wet and dry etch characteristics of the carbonized layer are presented.

Photoresist removal from silicon substrates has been achieved by a dry processing method using a plasma remote from the substrate to produce active species. Although the principal gas used is oxygen, the addition of small amounts of other gases (N2O, HCI, HBr, H2, Cl2, CF4, and CHF3) has been shown to significantly enhance resist removal. The measured temperature dependences indicate that the effect of these additives may be a combination of oxygen atom production enhancement by neutral and ionic mechanisms as well as independent reaction with the resist.

A novel process technology for producing a true cross-point EPROM cell is described in this paper. Buried N+ diffusions self-aligned to the Floating gate Avalanche injection MOS (FAMOS) transistor are used for the bit lines. These diffusions are covered with a planarized low temperature CVD oxide which isolates them from a perpendicular set of poly word lines. The bit line contacts and LOCOS isolation that are necessary for the industry standard cell have been eliminated. With this technology a 4 µm2cell using 1 µm design rules and zero alignment tolerance is feasible. The concept has been tested and verified using a 13.5 µm2test cell.

The authors report the fabrication, for the first time, of a shallow-trench isolated (less than 1 mu m deep) planarized, floating-gate avalanche injection MOS (FAMOS) transistor with n/sup +/ bitlines self-aligned to gate (n/sup +/ SAG). Key to the planar process is the self-alignment of the buried n/sup +/ diffusions (bitlines) to the floating gate of the FAMOS transistor and the deposition over these diffusions of a low-temperature, conformal CVD (chemical vapor deposition) oxide. An oxide-resist etchback process was used to planarize the buried n/sup +/ CVD oxide. Trench etching was done immediately after definition of the stacked polysilicon gates. Using an anisotropic etch for single-crystal silicon, trenches with a 0.75 mu m depth were made in the bitline isolation areas of the planar devices. The trenches were then refilled with thermal and LPCVD (liquid-phase CVD) SiO/sub 2/. Characterization of the planar EPROM (erasable programmable read-only memory) cell shows that the shallow trench between bitlines has improved their isolation characteristics. An increase in programming efficiency of as much as 30% at a pulse width of 1 ms was observed in the case of the shallow-trench-isolated FAMOS. Additional data indicate the possibility of programming the trench isolated cell at drain voltages lower than the present 12.5 V, thus reducing high voltage requirements. >