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While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

International audience; Extended Drain MOS (EDMOS) transistors were studied about hot-carrier (HC) degradation and its involvement in hard breakdown (BD) events as these smart power devices represent a big challenge to optimize under Off/On mode switching in RF circuits. N-channel devices with gate-length LG=0.5µm and two gate-oxide thicknesses were tested Tox= 2.3nm (GO1) and 8.5nm (GO2). The sensitivity to BD between Off-mode and HC is pointed out in GO1 through the hot-hole injections (HHI) that are involved as a function of gate-voltage VGS = VTH and VGmax where the VTH case induces HC damage that can be used with series resistance increase (RSD ) to detect BD events in the drift region. Hole trapping and interface traps are generated leading to the dominant effect of HHI, with very close generation rates between Off- and On- mode stressing. This can be used to prevent circuit aging giving warning level for confidence in AC lifetime for power amplifiers class E and class A.

We report here reliability analysis of the CMOS technology middle of the line dielectrics from 65nm, 40nm and 28nm nodes. Time to breakdown characteristics of spacers including voltage acceleration factor, Weibull slope and activation energy is extracted and compared numerical percolation model.

The impact of moisture diffusion on two types of fully integrated stacks was investigated. One of them with dense SiO 2 layers and the other with ultra low k (ULK), both of which are predominantly used in BEOL (Back End of Line) as inter layer dielectric films. For half of the samples of each dielectric, their surrounding seal ring was intentionally damaged. Storage of these samples was then performed either at ambient or at 85°C/85% relative humidity (RH) for five months to study the impact of moisture. Capacitance measurements and current voltages curves were used to assess moisture effect. For intact seal ring samples, no variations are observed for both dielectrics, which confirms the moisture protection offered by surrounding seal ring. For damaged seal ring structures, there is no variation neither after five months at ambient nor at 85°C/85% RH for dense SiO 2 structures. However, very significant variations are observed on capacitance and breakdown values of ULK structures. The effect of baking on these samples was then investigated. Baking at 125°C or 250°C does not give full recovery of capacitance in the integrated stacks. Moreover, its effect is not permanent. Finally, to assess moisture diffusion path, time of flight — secondary ion mass spectrometry (Tof-SIMS) analysis was performed. Moisture seems to diffuse at ULK/SiCN interfaces.

P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. N- and P- channel EDMOS are optimized for a gate-length LG = 0.5 μm, with gate-oxide thickness at 2.3 nm. We have evaluated more precisely the HC damage caused from channel to the extended drain by an improved extraction of series resistance (ΔRSD) till a 2nd order mobility modeling as a function of stressing VGS from VGS = 0 to VGmax. This allows to determine the worst-case of lifetime dependence in relation to the damage in the drift zone where breakdown sensitivity is found to be intimately bound up with the hot-hole (HH) injection efficiency in N-EDMOS while P-EDMOS exhibits a larger security margin.

This work presents an in-depth study of the thermal stability of low-k material in view of intermediate Back-End-Of-Line (iBEOL) for 3D sequential Integration. SiOCH ULK were analyzed after thermal annealing up to 600°C. Moreover, the stability and reliability of this ULK material coupled with W metal in line 1 integration is characterized up to 550°C, 5 $h$ . We have demonstrated that low-k material can support a thermal budget of 500°C, 2h with limited outgassing. This result is fully compatible with 3D sequential integration.

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

This paper deals with the extreme values statistics use for metal interconnect and dielectric reliability in microelectronics. For electromigration reliability on Cu lines, experimental failure times are obtained by using an especially designed test structure (multilink) allowing determination of successive lower failure times on a large set of samples. It is shown that the experimental statistical distributions of minima failure times using our multilink structures are deductible from the usual single Cu lines lognormal distribution with the help of extreme values and order statistics. The analytical transformations from single interconnect lognormal distribution to the successive first, second, and third minima failure time distributions are derived with the help of scaling parameters. In particular, the first failure time's distribution is a Weibull distribution whose parameters are a simple expression of the total number of links and the parent lognormal distribution parameters. Since time-dependent dielectric breakdown follows also Weibull statistics, the origin of parent distribution and its analytical possible form are similarly discussed in the framework of extreme values statistics. The statistics of successive breakdown are also derived from order statistics.

International audience; Electromigration (EM) copper lines reliability is assessed through standard wafer level (WL) and PL (PL) test in the present work. Since these tests are highly accelerated, one of the main questions as in all reliability studies is the effectiveness of reporting failure phenomena as they occur under use conditions. WL is known to have been intensively used for fast EM process monitoring on high volumes with elevated stress conditions. On the other hand, the PL test having less aggressive stress conditions is used in a process qualification scheme. We use the later in this study as a reference to evaluate WL test results through various processes. Thus, the present paper deals with the ability of WL in comparison to PL to effectively report reliability performances variations for different Cu lines process modifications. Results from WL reliability and PL reliability are compared in terms of lifetime variations and standard deviation evolution. Only limited correlation is found, suggesting that the failure mechanisms acting for both methods are not the same. Moreover, the results of this study highlight the need of defining new reliable EM testing structures and methods compatible with high volumes monitoring. (C) 2013 Elsevier B.V. All rights reserved.

In this paper two different structures that reproduce crucial aspects of interconnect design are studied extensively. The purpose is to evaluate the effect of these configurations on the electromigration degradation in order to provide lifetime quantitative design rules. Taking into account these configurations will increase the accuracy of reliability prediction at design level and help designers with high current density needs.

The electromigration threshold in copper interconnect is reported in this paper. The critical product (jL)c is first determined for copper oxide interconnects with temperature ranging from 250degC to 350degC from package-level experiments. It is shown that the product does not significantly change in this temperature range. Then, (jL)c was extracted for copper low-k dielectric (k=2.8) interconnects at 350degC. A larger value than that for oxide dielectric was found. Finally, a correlation between the n values from Black's model and with jL conditions was established for both dielectrics

Self-aligned barriers have been widely investigated in the replacement of standard PECVD dielectric liners to decrease coupling capacitance. As an alternative to CVD or electroless approaches, a two step process based on the modification of the Cu surface is proposed. This technique consists first in enriching Cu surface with Si atoms followed by a nitridation step to complete the so called CuSiN self-aligned barrier. In this paper, the silicidation mechanism is described and the crucial role of the nitridation step is demonstrated in terms of barrier stability under electrical stress. CuSiN efficiency against Cu diffusion and oxidation is also evidenced. Compared to a standard SiCN barrier, CuSiN self-aligned barriers revealed a gain of at least 3 decades in time-dependent dielectric breakdown lifetime and up to 7% decrease in intra-level coupling capacitance.

Graphical abstractThe work described in the present paper is about electromigration induced void formation mechanisms in Cu lines. An unusual behavior observed on the electrical resistance of some samples suggests the presence of more than one void in the stressed lines. The scope of this paper is about the origin of these voids; mainly how they appear in the lines and how they affect the Cu lines reliability.Display Omitted Highlights? Two voids in the lines are evidenced for samples showing two resistance step increases. ? Multi-voids behavior visible only for lower stress condition. ? No particular characteristics of two-voids samples. ? The two voids seem to occur independently. ? Local tensile stress and grains disorientation mainly explain the two voids formation. The work described in the present paper is about electromigration induced void formation mechanisms in Cu lines. An unusual behavior observed on the electrical resistance of some samples suggests the presence of more than one void in the stressed lines. The scope of this paper is about the origin of these voids; mainly how they appear in the lines and how they affect the Cu lines reliability.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz f T and 370 GHz f MAX associated with a CML ring oscillator gate delay τ D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

Se ha empleado carne de pollo separada mecanicamente (CPSM) como una fuente basica de proteina para el estudio de la eficiencia de siete enzimas proteoliticas y algunas mezclas enzimaticas en la hidrolisis de esta proteina. Como parametro principal se evaluo el incremento de la solubilizacion proteica durante las cuatro horas de proteolisis. Las enzimas alcalase, esperase, flavourzyme, protease fungica, HT-proteolitico, papaina, proteopex y las mezclas de alcalase +flovourzyme, esperase + flovourzyme, HT-proteolitico + flavourzyme, y proteopex + flavourzyme se aplicaron en concentraciones de 0,60% y 1,20% del producto comercial en funcion de la proteina total. El pH inicial se ajusto a 7,0 o 8,0 y la temperatura se mantuvo a 50oC o 60oC de acuerdo con las condiciones optimas de cada enzima. La actividad proteolitica de estas enzimas tambien se comparo frente a la azocaseina. Para posibilitar la comparacion entre los tratamientos se formulo un indice de hidrolisis (IH), que representa la razon entre el valor maximo y la cantidad inicial de proteina soluble. Los resultados demostraron que la temperatura no influyo en la proteolisis en el modelo considerado. La mezcla de alcalase + flavourzyme fue la mas eficaz de todos los tratamientos con la que se obtuvo mas del 70% de proteina soluble recobrada mientras que la proteasa fungica dio los resultados mas bajos.

International audience; The miniaturisation of integrated circuits leads to reliability issues such as electromigration (EMG). This well-known phenomenon is checked at design level by CAD tools. The conventional EMG check methods are based on electrical parameters. However, the wire physical degradation depends also on the interconnection network structure. In order to improve the EMG check methodologies, we propose an accurate method based on failure mechanism and chip power grid configuration. Indeed, the power grid offers redundant paths in case of void in main power supply path. The principle of our method is to take into account the contribution of these redundant paths in power grid lifetime assessment. These effects are validated by silicon ageing tests on structures designed in 28 nm Full Depleted Silicon on Insulator (FDSOI). These accelerated tests results have confirmed the lifetime gain due to the redundancy. These results provide perspectives for the relaxation of wire current limits and improve the chip design toward EMG.

3; International audience; The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.

Implication of microstructure during electromigration void formation process is studied in this paper. Dual damascene Cu lines with cathode end width variations are characterized. The idea of these variations being to force different microstructure profiles within the same test structure. The narrow-to-wide (NTW) width transition structure shows better electromigration performances than usual structure with a constant width (CW) along the line length. Bamboo Cu grains in the NTW structure wider segment are evidenced to slow down Cu atoms migration, inducing a local Blech's-like effect. This results in delayed void nucleation time and reduced void growth rate leading to increased lifetime. By this study, we show how great advantage can be taken on lifetime with this new design.

This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High Temperature Operating Life experimental ranges. Following the electrical analysis, a large panel of failure analysis methodologies was suitably used to categorize defects such as size, location, resistance impact, etc. This thorough analysis allows us to confirm that silicon failures are accurately predicted by our electromigration checker, based on reliability design rules.

An innovative electromigration test structure is described in this paper. This new structure consisting of serial connected links is designed to address very early percentiles of lognormal electromigration failure time distribution and highlight extrinsic failures. The simplicity of implementation, data treatment and the correlation with elemental dual damascene test lines make this structure a pretty good candidate for the future of interconnects reliability.

We propose in this work an analysis method to study electromigration degradation through void size evolution at the failure time. Electrical aging tests are performed to characterize electromigration (EM) failure phenomenon on Cu lines. We followed the impact of various applied stressing currents on void sizes at the time of failure through the resistance step increase (Rstep). Two major findings emerge from this study. First, the voids size distributions at the failure time show a bimodal behavior symptomatic of different voids sizes and locations. Secondly, the proportion of higher void size values increases with the stress current. In addition to the comprehension of electromigration void growth mechanisms; this simple method is particularly useful during process development to track voids occurring under via.

The work presented in this paper compares electromigration results from standard wafer level and package level tests. Dual damascene low-k Cu lines with different processes have been tested and correlation between both testing methods is evaluated. Results from wafer level reliability and package level reliability are compared around lifetime variations and standard deviation. Only limited correlation is found, strengthening the need of defining new reliable electromigration testing methods compatible with an industrial environment. Comparison between failures mechanisms involved in each testing method is also addressed.

Time evolution of resistance during EM tests is extensively analyzed for various Cu interconnect structures and processes from the 40 nm node technology. Resistance evolution is used to model void nucleation and growth kinetics. We show that adding Al or other impurities in the line is effective to increase electromigration lifetime. This lifetime increase is due, as expected, to Cu drift velocity decrease but also to an increase of the time to void formation. TEM picture shows that Al precipitates are formed at grain boundaries and are most likely responsible for the occurrence of an incubation time Resistance saturation is observed for short lines thanks to Blech effect. A resistance model is developed to characterize short length effect in 40 nm node. The model is also used to explain EM lifetime improvement thanks to a pre-stress condition where compressive stress is added at cathode end of long line structures.

As the interconnect cross-sections are ever scaled down, a particular care must be taken on the tradeoff between increase of current density in the back end of line and reliability to prevent electromigration (EM). Some lever exists as the well-known Blech effect [1]. One can take advantage of the EM induced backflow flux that counters the EM flux. As a consequence, the total net flux in the line is reduced and additional current density in designs can be allowed in short lines. However, the immortality condition is most of the time addressed with a standard test structures ended by two vias [2]–[3]. Designs present complex configurations far from this typical case and the Blech product (jL)c can be deteriorated or enhanced [4]. In the present paper, we present our study of EM performances of short lines ended by an inactive end of line (EOL) at one end of the test structure. Significant differences on the median time to failure (MTF) are observed with respect to the current direction, from a quasi deletion of failure to a significant reduction of the Blech effect. Based on the resistance saturation, a method is proposed to determine effective lengths of inactive EOL configurations corresponding to the standard case.

In this paper, we present our investigations on time evolution of the resistance during EM tests for various j and L conditions at three different temperatures. These resistance traces have been modeled calculating the void volume kinetic. A good agreement with experimental data was found; in particular the resistance saturation regime at low jL was simulated. From this modeling, we propose an immortality criterion depicted by the product jL2, based on the limitation of the void growth prior to an electrical detection. In the temperature range investigated, no significant variation was found for this criterion.

The ever increasing scaling down of IC leads to ever more current density in interconnects. As a consequence, electromigration (EM) becomes a concern in interconnect reliability. In order to face this problem and allow more current density in design, one can take advantage of the Blech effect [1]. Many investigations have proposed extraction methods, behaviors or values for the threshold jL c product but some controversies subsist in particular on failures under jL c [2]. We studied the resistance saturation with time to characterize Blech effect of Cu/low-k dual damascene interconnects from the 65 nm node. We propose an immortality criterion proportional to the jL2 product based on the limitation of EM induced void volume at steady state. In our case, this criterion leads to more relaxed current rules for short lines compared to jL c criterion.

In this paper, we report on the temperature dependence of electromigration threshold product in copper interconnects. The electromigration threshold product (jL) c is first determined from lifetime distributions for temperatures ranging from 260°C to 330°C. We then propose an alternative method to determine (jL) c at much lower temperatures. We show that the threshold product does not vary significantly in the investigated temperature range. We demonstrate this alternative method is suitable to determine (jL) c close to the final product operating temperature, which would require unrealistic test duration if performed with a conventional method based on lifetime data.

Cholestatic liver diseases, such as cystic fibrosis (CF) liver disease and biliary atresia, predominate as causes of childhood cirrhosis. Despite diverse etiologies, the stereotypic final pathway involves fibrogenesis where hepatic stellate cells (HSCs) are recruited, producing excess collagen which initiates biliary fibrosis. A possible molecular determinant of this recruitment, monocyte chemotaxis protein-1 (MCP-1), an HSC-responsive chemokine, was investigated in CF liver disease and biliary atresia. The bile-duct-ligated rat and in vitro coculture models of cholestatic liver injury were used to further explore the role of MCP-1 in HSC recruitment and proposed mechanism of induction via bile acids. In both CF liver disease and biliary atresia, elevated hepatic MCP-1 expression predominated in scar margin hepatocytes, closely associated with activated HSCs, and was also expressed in cholangiocytes. Serum MCP-1 was elevated during early fibrogenesis. Similar observations were made in bile-duct-ligated rat liver and serum. Hepatocytes isolated from cholestatic rats secreted increased MCP-1 which avidly recruited HSCs in coculture. This HSC chemotaxis was markedly inhibited in interventional studies using anti-MCP-1 neutralizing antibody. In CF liver disease, biliary MCP-1 was increased, positively correlating with levels of the hydrophobic bile acid, taurocholate. In cholestatic rats, increased MCP-1 positively correlated with taurocholate in serum and liver, and negatively correlated in bile. In normal human and rat hepatocytes, taurocholate induced MCP-1 expression. Conclusion: These observations support the hypothesis that up-regulation of hepatocyte-derived MCP-1, induced by bile acids, results in HSC recruitment in diverse causes of cholestatic liver injury, and is a key early event in liver fibrogenesis in these conditions. Therapies aimed at neutralizing MCP-1 or bile acids may help reduce fibro-obliterative liver injury in childhood cholestatic diseases. (HEPATOLOGY 2009;49:533-544.)

In this study, conduction asymmetry is analyzed using asymmetric stacks in order to appreciate the cathode role. Then original test structures are used to highlight fringe leakage and to model asymmetry in a pure Ta2O5 capacitor for both surface and peripheral currents. Finally, the impact of peripheral on self-heating and consequently on reliability parameters is deeply investigated. Important information are then provided regarding intrinsic MIM characteristics, process optimization, reliability methodology and design rules.

Electromigration failure mode has been recognized as a strong limitation to scaling of copper interconnects for years. The development, as well as manufacturing monitoring, of advanced CMOS processes requires a large number of electromigration tests. Such industrial need is in favour of fast wafer level test rather than long-term tests on packaged samples. However, lifetimes issued from wafer level tests are still difficult to project to operating conditions since large uncertainties affect activation energy Ea and current density exponent n calculated using this methodology. Despite several improvements on the test procedure itself, longitudinal temperature gradients in metal line under test still represent a source of errors. Here, we present a characterization of thermal gradients developing in electromigration tests lines and a new design of test structure to minimize these gradients. By performing electromigration wafer level tests on this new structure, we observe a great improvement in Ea determination.

The careful analysis of resistance evolution with time during electromigration tests provided valuable information about damascene architecture and intrinsic electromigration behavior. On one hand, void length and barrier resistivity can be extracted from the step height, but we have shown that it is sensitive to high accelerated tests. On the other hand, both the activation energy and the current density exponent can be calculated directly from the slope of the progressive increase, on a single device. Such methodology is likely to increase accuracy on Black's parameters.

Taking into account Matthiessen's rules, we have developed a model of residual resistivity with line dimensions. The method developed allows distinguishing the effect of impurities and the sizing effect. Thus we are able to determine line dimensions consistent with process variation. Finally this model allows an appreciable evaluation of the TCR

The careful analysis of resistance evolution with time during electromigration tests provided valuable information about damascene architecture and intrinsic electromigration behaviour. We found first, that resistance evolution includes an abrupt event, the amplitude of which is usually corresponding to the failure criteria and second, that the height of this step (and sample resistance) is correlated with time to fail. We showed that the evolution of time to step was more likely to be due to the vertical growth of a void which length is making resistance step amplitude varying from sample to sample. Second we found a correlation between sample initial resistance and time to failure that is believed to be due to trench depth. However this effect is widely spread and correlation coefficient is as low as 0.3. These 2 phenomena combined together, increase the standard deviation affecting lifetime. As a matter of fact, resistance increase rate is expected to be directly proportional to void growth rate and copper diffusion coefficient whereas step height is function of the void shape and barrier thickness

The electromigration threshold in copper interconnect is reported in this study. The critical product jLc was first determined for copper-oxide interconnects in the temperature range 250/spl deg/C-350/spl deg/C from package level experiments. It is shown that the product does not significantly change in this temperature range. Then jLc was extracted for copper-low k dielectric (k=2.8) interconnects at 350/spl deg/C. A larger value than for oxide dielectric was found. Finally, a correlation between n values from Black's model and jL conditions was established for both dielectrics.

Several experimental studies reported an increase of the copper resistivity with decreasing interconnects dimensions (Schafft and Suchle, 1992). However, the accuracy of measurement is limited by the knowledge of sample geometry. As a matter of fact, the geometry of resistors issued from advanced damascene process is varying with process parameters (trench height, diffusion barrier thickness, CMP (chemical mechanical polishing) effect). Taking into consideration Mathiessen empirical relation we established a relation between, resistivity, TCR (temperature coefficient of resistance) and metal cross section to develop an accurate methodology to determine thickness and resistivity of damascene copper samples.