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The electronically tunable differentiator using a voltage difference transconductance amplifier (VDTA) is proposed, designed, and analyzed. The simulation was done using the Cadence Virtuoso tool of 45 nm CMOS technology with a supply voltage of ±0.9 V. The maximum power consumption of the proposed circuit is 246 μ W with a total harmonic distortion of 5.4%. The output can be tuned using four parameters: g m 1 , g m 2 , R 1 , and R 2 . The transconductance can be varied using bias current and aspect ratio of CMOS transistors. The utilized area of VDTA layout is 1075.81 μ m2. The parasitic impedance affects the output of post-layout simulation and causes little delay compared to schematic. The design has been experimentally verified using LM13700 integrated circuit. The results of the proposed circuit show good agreement with the experimental results and mathematical expressions. The proposed circuit can be used as a tunable PD controller, in which the voltage gain of the proposed circuit is G PD = K p + S K d . The design is versatile and can be used in different applications such as temperature control systems, photo voltaic cells, waveform generators, microwave communications systems, and instrumentation systems. [ABSTRACT FROM AUTHOR]

In this paper, we present a CMOS rail-to-rail second-generation voltage conveyor (VCII) suitable for low power applications, implemented in 180 nm CMOS technology with a supply voltage of ± 0.9 V. The proposed VCII consists of a current and voltage buffer operating in class AB. At the input of the voltage buffer, there is a bulk-driven differential amplifier, which provides a rail-to-rail input common-mode voltage. A common source output stage in class AB provides rail-to-rail at the output of the voltage buffer. The transistors are designed to operate in moderate inversion, achieving a relatively large current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively, with a power consumption of 157 μW. A sine wave with an amplitude of 1.5 Vpp and a frequency of 1 MHz on the output buffer has a total harmonic distortion of only 0.29%. The application of VCII in a relaxation oscillator with a frequency of up to 10 MHz is demonstrated, as well as its comparative characteristics with reference to other relevant square-wave generators published in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a novel power-efficient topology for receivers in short-range LiDAR sensors. Conventionally, LiDAR sensors exploit complex time-to-digital converters (TDCs) for time-of-flight (ToF) distance measurements, thereby frequently leading to intricate circuit designs and persistent walk error issues. However, this work features a fully differential trans-impedance amplifier with on-chip avalanche photodiodes as optical detectors so that the need of the following post-amplifiers and output buffers can be eliminated, thus considerably reducing power consumption. Also, the combination of amplitude-to-voltage (A2V) and time-to-voltage (T2V) converters are exploited to replace the complicated TDC circuit. The A2V converter efficiently processes weak input photocurrents ranging from 1 to 50 μApp which corresponds to a maximum distance of 22.8 m, while the T2V converter handles relatively larger photocurrents from 40 μApp to 5.8 mApp for distances as short as 30 cm. The post-layout simulations confirm that the proposed LiDAR receiver can detect optical pulses over the range of 0.3 to 22.8 m with a low power dissipation of 10 mW from a single 1.8 V supply. This topology offers significant improvements in simplifying the receiver design and reducing the power consumption, providing a more efficient and accurate solution that is highly suitable for short-range LiDAR sensor applications. [ABSTRACT FROM AUTHOR]

The demand for gas sensing systems that enable fast and precise gas recognition is growing rapidly. However, substantial challenges arise from the complex fabrication process of sensor arrays, time‐consuming data transmission to an external processor, and high energy consumption in multi‐stage data processing. In this study, a gas sensing system using on‐chip annealing for fast and power‐efficient gas detection is proposed. By utilizing a micro‐heater embedded in the gas sensor, the sensing material of adjacent sensors in the same substrate can be easily varied without further fabrication steps. The response to oxidizing gas is constrained in metal oxide (MOX) sensing material with small grain sizes, as the depletion width of grain cannot extend beyond the grain size during the gas reaction. On the other hand, the response to reducing gases and humidity, which decrease the depletion width, is less affected by grain sizes. A readout circuit integrating a differential amplifier and dual FET‐type gas sensors effectively emphasizes the response to oxidizing gases by canceling the response to reducing gases and humidity. The selective on‐chip annealing method is applicable to various MOX sensing materials, demonstrating its potential for application in commercial fields due to its simplicity and expandability. [ABSTRACT FROM AUTHOR]

Memristor technology has grown at a breakneck pace over the last decade, with the promise to transform data processing and storage. A memristor is a non-linear electrical component with two terminals that connect electric charge and magnetic flux. The ability to store and process data in the same physical location is a fundamental benefit of memristors over traditional electrical components. It has a unique feature in that its resistance may be preset (resistor function) and then saved (memory function). Memristors, unlike other types of memory used in modern electronics, are stable and retain their state even if the device is turned off. In this work, a new highly accurate asymmetrical memristor is proposed for highly efficient analog applications. The proposed work used 5 Complementary metal–oxide–semiconductor (CMOS) devices in a parallel and series-connected manner. A bypass transistor is used to control the current flow between two terminals to perform a stable operation. A differential amplifier circuit is used to validate the proposed memristor performance. The proposed work is implemented using TSMC 45 nm CMOS technology. This application consumes less power and has good performance when compared with conventional techniques. In this work, a 1 V power supply occupies a 67.5 µm2 layout area. The experimental results are improved when compared with the existing circuit. [ABSTRACT FROM AUTHOR]

In this study, we developed and demonstrated a millimeter-wave electric field imaging system using an electro-optic crystal and a highly sensitive polarization measurement technique using a polarization image sensor, which was fabricated using a 0.35-µm standard CMOS process. The polarization image sensor was equipped with differential amplifiers that amplified the difference between the 0° and 90° pixels. With the amplifier, the signal-to-noise ratio at low incident light levels was improved. Also, an optical modulator and a semiconductor optical amplifier were used to generate an optical local oscillator (LO) signal with a high modulation accuracy and sufficient optical intensity. By combining the amplified LO signal and a highly sensitive polarization imaging system, we successfully performed millimeter-wave electric field imaging with a spatial resolution of 30 × 60 µm at a rate of 1 FPS, corresponding to 2400 pixels/s. [ABSTRACT FROM AUTHOR]

Complementary metal oxide semiconductor (CMOS) comparators play a pivotal role in analog and mixed‐signal circuits, finding diverse applications across electronic systems. In data converter circuits, the significance of high‐speed, low‐power comparators is pronounced. They ensure swift and precise signal comparisons, minimizing energy usage for dependable analog‐to‐digital and digital‐to‐analog conversions. This paper introduces an advanced CMOS dynamic comparator, optimized for data converter circuits using a 45 nm CMOS process. The comparator integrates two novel designs tailored for operation at 0.8 and 1 V power supplies, functioning at 1 GHz. One design incorporates a cascode differential amplifier in the pre‐amplifier stage, enhancing speed and sensitivity by augmenting gain, linearity, and output swing. This approach achieves a delay of 73.53 ps and consumes 9.95 μW at a 1 V supply voltage. The second design employs a simple charge pump in the pre‐amplifier stage, further elevating speed and sensitivity through amplified voltage levels and enhanced slew rate, resulting in a 57.24 ps delay and 9.03 μW power consumption at 1 V. Simulations underscore the proposed comparator's superiority over conventional counterparts, showcasing significant enhancements in speed and power efficiency, all while preserving precision and dependability. [ABSTRACT FROM AUTHOR]

Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques. [ABSTRACT FROM AUTHOR]

The electromagnetic eddy current non-destructive testing system enables the non-destructive analysis of surface defect information on tested materials. Based on the principles of eddy current detection, this paper presents a digital eddy current detection method using high-speed sampling based on STM32. A differential eddy current coil is used as the detection probe, and the combination of a differential bridge and a differential amplifier circuit helps to reduce common-mode noise interference. The detection signal is collected via an STM32-based acquisition circuit and transmitted to the host computer through Ethernet for digital demodulation processing. The host computer performs operations such as smoothing averaging, sinusoidal fitting, and outlier removal to extract the amplitude and phase of the detection signal. The system also visually displays the condition of the tested object's surface in real time through graphical visualization. Testing showed that this system can operate at frequencies up to 8.84 MHz and clearly identify defects as narrow as 1 mm on the surface of the tested steel plate. [ABSTRACT FROM AUTHOR]

A capacitance multiplier is an active circuit designed specifically to increase the capacitance of a passive capacitor to a significantly higher capacitance level. In this paper, the use of a voltage differencing differential difference amplifier (VDDDA), an electronically controllable active device for designing grounded and floating capacitance multipliers, is proposed. The capacitance multipliers proposed in this study are extremely simple and consist of a VDDDA, a resistor, and a capacitor. The multiplication factor ( K c ) can be electronically controlled by adjusting the external bias current ( I B ). It offers an easy way of controlling it by utilizing a microcontroller for modern analog signal processing systems. The multiplication factor has the potential to be adjusted to a value that is either less than or greater than one, hence widening the variety of uses. The grounded capacitance multiplier can be easily transformed into a floating one by utilizing Zc-VDDDA. PSpice simulation and experimentation with a VDDDA realized from commercially available integrated circuits were used to test the performance of the proposed capacitance multipliers. The multiplication factor is electronically adjustable, ranging in approximation from 0.56 to 13.94. The operating frequency range is approximately three frequency decades. The realization of the lagging and leading phase shifters using the proposed capacitance multiplier is also examined and proven. The results reveal that the lagging and leading phase shifts are electronically tuned via the multiplication factor of the proposed capacitance multipliers. [ABSTRACT FROM AUTHOR]

In this paper, a fully differential amplifier is proposed in a 1.8 V-0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology, which can accommodate both voltage (V-mode) and current (C-mode) inputs. Post-layout simulation results show a fixed gain amplifier exhibiting a 26 dB (V-mode)/89 dBΩ (C-mode) gain and a programmable gain amplifier featuring a 6–26 dB gain, overall yielding a 26.8–46.4 dB dB (V-mode)/89.6–109.2 dBΩ (C-mode) programmable gain range, with a 100 MHz bandwidth and a power and area consumption of 360.5 µW and 0.0177 mm2, respectively. This amplifier has been designed considering the constraints and specifications (including low voltage, low power, reduced noise and high common mode rejection ratio) for its use in an analogue Lock-in-based Frequency Response Analyser-Impedance Spectroscopy (FRA-IS) device. The proposed design introduces a novel fully differential open-loop structure based on a transconductance–transimpedance (TC-TI) topology for high performance applications with a broad programmable bandwidth. To compare this work, different figures of merit (FoMs) are introduced as well as a comparison table with other simulated and experimental results, reporting an overall better performance in terms of gain, frequency and power-area consumption. [ABSTRACT FROM AUTHOR]

Amplification of wideband high-frequency and microwave signals is a fundamental element within every high-frequency circuit and device. Ultra-wideband (UWB) sensor applications use circuits designed for their specific application. The article presents the analysis, design, and implementation of ultra-wideband differential amplifiers for M-sequence-based UWB applications. The designed differential amplifiers are based on the Cherry–Hooper structure and are implemented in a low-cost 0.35 µm SiGe BiCMOS semiconductor process. The article presents an analysis and realization of several designs focused on different modifications of the Cherry–Hooper amplifier structure. The proposed amplifier modifications are focused on achieving the best result in one main parameter's performance. Amplifier designs modified by capacitive peaking to achieve the largest bandwidth, amplifiers with the lowest possible noise figure, and designs focused on achieving the highest common mode rejection ratio (CMRR) are described. The layout of the differential amplifiers was created and the chip was manufactured and wire-bonded to the QFN package. For evaluation purposes, a high-frequency PCB board was designed. Schematic simulations, post-layout simulations, and measurements of the individual parameters of the designed amplifiers were performed. The designed and fabricated ultra-wideband differential amplifiers have the following parameters: a supply current of 100–160 mA at −3.3 V or 3.3 V, bandwidth from 6 to 12 GHz, gain (at 1 GHz) from 12 to 16 dB, noise figure from 7 to 13 dB, and a common mode rejection ratio of up to 70 dB. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel approach to counter the influence of ambient light on photodetectors used in applications like biometric recognition and environmental sensing. The proposed solution introduces a circuit‐based technique that utilizes signal differencing to subtract ambient light signals before they reach the integrated circuit (IC). The process involves row and column differential signals, akin to analog circuit differential amplifiers. Simulations validate the circuit's functionality, showing its effectiveness in reducing ambient light impact. However, image reconstruction after differencing introduces blurriness due to the accumulation of noise. An alternative bidirectional fusion method is suggested, resulting in a clearer representation of features without noise accumulation. This innovative approach promises to enhance photodetector performance in challenging lighting conditions for various applications. [ABSTRACT FROM AUTHOR]

In this paper a new method to find the parametric faults in weakly nonlinear analog circuit is proposed. Frequency domain volterra kernels are derived to calculate the test parameters i.e., nonlinear distortions and the cross spectral density. Volterra kernels are sensitive to device parameter and the components used to build the circuit. Device parameter and each component value are varied within the tolerance limit using Monte Carlo simulation. For the fault free circuit maximum and minimum values of the 3rd order harmonic, intermodulation distortion and the cross spectral density are measured. During testing, single and multiple faults are injected and the test parameters are measured. If any one or more test parameters are outside the predetermined bounds the circuit is declared to be faulty. This proposed method offers high fault coverage capability. To validate this method CMOS differential amplifier circuit is taken under consideration. [ABSTRACT FROM AUTHOR]

This article presents measurement circuits and a test board developed for the experimental evaluation of prototype chip samples of the Fully Differential Difference Amplifier (FDDA). The Device Under Test (DUT) is an ultra low-voltage, high performance integrated FDDA designed and fabricated in 130nm CMOS technology. The power supply voltage of the FDDA is 400mV. The measurement circuits were implemented on the test board with the fabricated FDDA chip to evaluate its main parameters and properties. In this work, we focus on evaluation of the following parameters: the input offset voltage, the common-mode rejection ratio, and the power supply rejection ratio. The test board was developed and verified. The test board error was measured to be 38.73mV. The offset voltage of the FDDA was −0.66mV. The measured FDDA gain and gain bandwidth were 48dB and 550kHz, respectively. In addition to the measurement board, a graphical user interface was also developed to simplify the control of the device under test during measurements. [ABSTRACT FROM AUTHOR]

This article describes a low-voltage, low-power fractional-order low-pass filter (FO-LPF) of order 1 + α, which is implemented using a voltage differencing differential difference amplifier (VDDDA). The VDDDA structure is implemented using the bulk-driven metal oxide semiconductor transistor technique. The transistors operate in the subthreshold region to maintain low-supply voltage and low-power consumption. The FO-LPF structure implemented using this VDDDA structure is compact. It includes three VDDDAs and three grounded capacitors along with two active resistors implemented using MOS transistors. In addition, this filter structure provides electronic tuning of its order and cut-off frequency through the bias current of the active component used. The effects of tracking error and parasitics on the functionality of the proposed FO-LPF were investigated. The VDDDA and filter operate at ±300 mV and dissipate only 207 nW and 663 nW of power, respectively. Thus, the VDDDA structure and filter are suitable for low-voltage and low-power operation. Layouts of the proposed VDDDA as well as the FO-LPF were designed in the Cadence Virtuoso environment. Post-layout simulation results of the designed circuits imply that they are suitable for fabrication. Noise, total harmonic distortion, Monte-Carlo, and PVT analyses were also performed. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. [ABSTRACT FROM AUTHOR]

In this paper, we express Thévenin equivalent circuits seen looking into the terminals of the small-signal model of the vacuum tube triode in terms of the Thévenin equivalent circuits seen looking out of the other terminals and apply them to the analysis of the common-cathode, common-plate, and common-grid single-tube amplifier configurations, as well as a differential pair amplifier. This is an adaptation of equivalent circuit techniques for transistor circuits pioneered by Marshall Leach. The use of equivalent circuits can yield intuitive solutions that avoid solving sets of equations. [ABSTRACT FROM AUTHOR]

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms. [ABSTRACT FROM AUTHOR]

In recent years, the voltage differencing differential difference amplifier (VDDDA) has been used in various analog signal processing circuit designs. A second-order multifunction filter with multiple-inputs and single-output (MISO) voltage mode using VDDDA as active elements is proposed in this paper. The structure of the proposed filter comprises two VDDDAs, two grounded capacitors, and two resisters. The proposed filter has a cascadability feature in a voltage-mode system, producing voltage input and voltage output at high and low impedance ports, respectively. It can offer responses for all-pass (AP), band-reject (BR), band-pass (BP), low-pass (LP), and high-pass (HP) filters without additional inverting and double gain amplifiers, as well as the matching conditions. Choosing the appropriate input signals provides these five filter responses in the same circuit topology. With two VDDDAs, the bias currents can be utilized to electronically tune the natural frequency (!0) independently from the quality factor (Q). Experimental results using available commercial ICs have supported the theoretical expectations and confirmed the practical operation of the proposed multifunction biquad filter. [ABSTRACT FROM AUTHOR]

This article reports a two-stage differential structure power amplifier based on a 130 nm SiGe process operating at 77 GHz. By introducing a tunable capacitor for amplitude and phase balance at the center tap of the secondary coil of the traditional Marchand balun, the balun achieves amplitude imbalance less than 0.5 dB and phase imbalance less than 1 degree within the operating frequency range of 70–85 GHz, which enables the power amplifier to exhibit comparable output power over a wide operating frequency band. The power amplifier, based on a designed 3-bit digital analog convertor (DAC)-controlled base bias current source, exhibits small signal gain fluctuation of less than 5 dB and saturation output power fluctuation of less than 2 dB near the 80 GHz frequency point when the ambient temperature varies in the range of −40 °C to 125 °C. Benefiting from the aforementioned design, the tested single-path differential power amplifier exhibits a small signal gain exceeding 16 dB, a saturation output power exceeding 18 dBm, and a peak saturation output power of 19.1 dBm in the frequency band of 70–85 GHz. [ABSTRACT FROM AUTHOR]

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC's parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage V I N _ O F F of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the V I N _ O F F of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage V D D = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations. [ABSTRACT FROM AUTHOR]

An electrostatic field mill (EFM) is widely used to measure the strength of electrostatic fields, the main drawback of which is the occurrence of large measurement errors (up to 15 % in the range from 0 to 1 kV/m). This paper examines the aspects of using transimpedance amplifiers (TIAs) for the tasks of converting the current received from the EFM sensor into voltage, which will make it possible to reduce the instrumental error and ensure the linearity of the atmospheric electrostatic field strength measurement. In the general case, for the functional circuits of the electrostatic field mill, which include a differential transimpedance amplifier, there is the use of two TIA circuits, which are connected in parallel. Despite the simplicity of implementation, such a configuration contains a number of disadvantages and is not optimal. In the paper, a comparative analysis of a typical circuit of a differential TIA and a circuit of an ungrounded differential transimpedance amplifier with zero voltage drop proposed by the authors is carried out. As a result of the analysis, it was established that the designed authentic circuit of the ungrounded differential transimpedance amplifier with zero voltage drop has better parameters of linearity and interference resistance, in contrast to the generally accepted one. The value of the signal-to-noise ratio for the proposed scheme improved by 42 % on average compared to the typical one. The main difference of the proposed scheme is that the stability of the amplification factor is ensured, the influence of the bias parameters of the operational amplifier is leveled, and the overall noise level is reduced. The use of the designed scheme of an ungrounded differential transimpedance amplifier with zero voltage drop could make it possible to increase the accuracy of the measurement of the electrostatic field strength. [ABSTRACT FROM AUTHOR]

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than −10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions. [ABSTRACT FROM AUTHOR]

This paper presents the design of a driving amplifier intended for use in W-band RFICs. The amplifier adopts a differential two-stage common-source configuration to ensure robust output power. Furthermore, it has been enhanced through the incorporation of a neutralized capacitor to improve stability and maximize gain. The driving amplifier was fabricated using a 65-nm bulk CMOS process for validation. The measured performance of the amplifier demonstrated characteristics, including an input/output return loss exceeding 10 dB and a peak gain of 14.1 dB, achieved within the frequency range of 77∼88 GHz. The power consumption of the amplifier was only 34 mW at a voltage of 1 V, and it exhibited an OP1dB of 3.8 dBm. The size of the driving amplifier, excluding DC and RF pads, was 0.401×0.14 mm². [ABSTRACT FROM AUTHOR]

In this work, we propose a variation of the cellular particle swarm optimization algorithm with differential evolution hybridization (CPSO-DE) to include constrained optimization, named Ts-CPD. It is implemented as a kernel of electronic design automation (EDA) tool capable of sizing circuit components considering a single-objective design with restrictions and constraints. The aim is to improve the optimization solutions in the sizing of analog circuits. To evaluate our proposal's performance, we present the design of three analog circuits: a differential amplifier, a two-stage operational amplifier (op-amp), and a folded cascode operational transconductance amplifier. Numerical simulation results indicate that Ts-CPD can find better solutions, in terms of the design objective and the accomplishment of constraints, than those reported in previous works. The Ts-CPD implementation was performed in Matlab using Ngspice and can be found on GitHub (see Data Availability Statement). [ABSTRACT FROM AUTHOR]

This Paper presented a novel differential CMOS cascaded power amplifier (PA) operated at 76.5 GHz frequency band for automotive Radar applications. PA consumes more DC power on the front side of the RF transmitter, so a highly efficient PA is required which have high output power for long range used in automotive Radar application. PA with high output power is the biggest challenges for designing. at mm-wave range. This paper described the three most important challenges of CMOS PA: low breakdown voltages, a low-quality factor of passive elements and low output swing in CMOS technology. It presents a new method to design Class E PA using three configurations: cascaded, differential, and parallel. Some basic parameters used for PA are also discussing in this paper. Post Layout Simulation results of the proposed PA is carried out over SpectreRF Cadence software. The circuit dissipates a total DC power of 64.8 mW from a 3.6 V power supply, 340 × 1130 µm2 layout area and the input/output return losses of the circuit at 76.5GHz frequency are −36 dB and −27 dB respectively. It provides 17 dBm output power, 20.4 dB power gain, 1.15 stability factor, and 3.1 dB noise factor [ABSTRACT FROM AUTHOR]

This article presents a proficient architecture of a power-efficient gate-driven two-stage fully-differential operational transconductance amplifier (FD-OTA). The proposed fully-differential OTA operating in the subthreshold region offers a more comprehensive input and output voltage range. It exploits forward body-biasing techniques in the current mirror load that is employed on a composite input core. Further, both stages are adaptively biased using two gate-driven cascoded flipped voltage follower (CASFVF) differential amplifiers to eliminate the dedicated tail current sources and operate in super class-AB mode. The overall structure allows precise bias current control across pseudo-differential pairs, leading to low process, voltage, and temperature (PVT) variance in small and large signal performance characteristics. In open-loop operation, the proposed approach allows the 0.35-V operated OTA to obtain a voltage gain of 96.16 dB, a CMRR of 158.68 dB, a phase margin of 65.18°, and a unity gain frequency of 43.73 kHz for a 15 pF capacitive load in UMC 0.18-µm CMOS technology. Moreover, an average slew rate of 5.11 V/µs for a power dissipation of 70 nW establishes the highest large-signal figure-of-merit (FOML) among the latest state-of-the-art, proving its usefulness in high-speed applications as well. [ABSTRACT FROM AUTHOR]

Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today's high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided. [ABSTRACT FROM AUTHOR]

One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by using a monitor circuit that tracks the evolution of the circuit performance. In this paper, we propose the use of DC temperature measurements in the proximity of the circuit to perform the monitoring of circuit performance degradation and as an observable variable to adjust the bias of the main devices to restore the degraded performance to the original values. To this end, we present experimental results obtained from nine samples of a standard CMOS integrated circuit containing a high-frequency class-A power amplifier and a differential temperature sensor. After accelerated aging, the gain of the amplifier is degraded up to 50%. We propose two different procedures to perform DC temperature measurements that allow tracking of the amplifier gain degradation due to aging and, by uniquely observing temperature readings, automatically set a new bias for the amplifier devices that restores the original amplifier gain. Whereas one of the procedures is able to restore the gain up to a certain limit, the second allows full gain restoration. [ABSTRACT FROM AUTHOR]

Cascaded Single-Stage Distributed Amplifiers (CSSDAs) are instrumental in achieving ultra-wideband amplification for microwave applications due to their significant gainbandwidth products. However, their functionality is often compromised by internal noise, which detrimentally impacts the linearity of the response. An innovative solution to this prevalent issue is presented in this study through the introduction of the Quasi- Differential Distributed Amplifier (QDDA). Implementing the 0.18μm Complementary Metal Oxide Semiconductor (CMOS) technology, a QDDA with a single-stage fourcascade configuration was designed, fabricated, and tested. The empirical results revealed a high gain of 20dB and an extensive bandwidth of 30GHz. Moreover, the noise figure was observed to be 4.809 with a compact chip size of 0.74mm². This design and the resulting findings were accomplished using the Advanced Design System (ADS) RF simulator. The circuit layout and specifications were subsequently generated using the Cadence tool. This research demonstrates the potential of the QDDA to significantly enhance the performance of CSSDAs, contributing to the advancement of ultra-wideband microwave applications. [ABSTRACT FROM AUTHOR]

Artificial intelligence has made people's demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtractor, voltage follower and ReLU activation function are designed based on a differential amplifier. An Iris dataset was introduced in this experiment to conduct simulation experiments on the research circuit. The IMC circuit designed for this experiment has high performance, with an accuracy rate of 96.2% and a recall rate of 60.2%. The overall current power consumption of the hardware circuit is small, and the current power consumption of the subtractor circuit and ReLU circuit does not exceed 100 µA, while the power consumption of the negative feedback circuit is about 440 mA. The accuracy of analog circuits under the IMC architecture is above 93%, the energy consumption is only about 360 nJ, and the recognition rate is about 12 μs. Compared with the classic von Neumann architecture, it reduces the circuit recognition rate and power consumption while meeting accuracy requirements. [ABSTRACT FROM AUTHOR]

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0–29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0–29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0–29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0–29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm2, including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a versatile first-order analog filter using differential difference transconductance amplifiers (DDTAs). The DDTA employs the bulk-driven (BD) multiple-input MOS transistors technique (MI-MOST) operating in the subthreshold region. This results in low-voltage and low-power operational capability. Therefore, the DDTA, designed using 130 nm CMOS technology from UMC in the Cadence environment, operates with 0.3 V and consumes 357.4 nW. Unlike previous works, the proposed versatile first-order analog filter provides first-order transfer functions of low-pass, high-pass, and all-pass filters within a single topology. The non-inverting, inverting, and voltage gain of the transfer functions are available for all filters. Furthermore, the proposed structure provides high-input and low-output impedance, which is required for voltage-mode circuits. The pole frequency and voltage gain of the filters can be electronically controlled. The total harmonic distortion of the low-pass filter was calculated as −39.97 dB with an applied sine wave input signal of 50 mVpp@ 50 Hz. The proposed filter has been used to realize a quadrature oscillator to confirm the advantages of the new structure. [ABSTRACT FROM AUTHOR]

Advancements in integrated circuits technology, force designers to adopt methods and approaches with posed limitations. Nowadays, multistage amplifiers are widely in demand due to high‐gain performance while avoiding placing transistors vertically in contrast with cascode structures. In this work, a four‐stage amplifier is investigated and frequency is compensated via a compensation network that includes two Miller capacitors at the outputs of differential blocks. So, using two Miller capacitors and sharing these capacitors common in four Miller loops, provide an opportunity to achieve acceptable frequency response regarding gain‐bandwidth product and phase margin. The proposed amplifier is modeled symbolically and simulated with the HSPICE circuit simulator with the help of 0.18 μm CMOS technology. According to the simulation results, the proposed approaches show superior performance compared with previously existing methods. Additionally, the sensitivity of the proposed amplifier against load and compensation capacitors expresses a stable and relatively fixed frequency response. Such a high gain amplifier with more than 180 dB as DC gain and 88° phase margin, is in great demand for realizing modulators and data converters. [ABSTRACT FROM AUTHOR]

This paper proposes a FINFET (Fin Field Effect Transistor)-based Voltage Difference Transconductance Amplifier (VDTA). This paper aims to provide an amplifier that will enable VDTA to achieve its desired characteristics. The circuit proposed for FINFET-based VDTA operates with a bias current order of 150μA and a source voltage of 0.9V. The active element makes the amplitude electronically tuneable with bias current. The designed circuit was implemented in both GPDK 180nm technology and FINFET technology using the Cadence Virtuoso tool. Various factors, including technology node components and the operating voltage provided by FINFET VDTA structures, are compared. A Monte Carlo simulation is conducted for the suggested circuit, which dissipates 187.53μW of power. In comparison to the standard VDTA, it exhibits notably low power dissipation. [ABSTRACT FROM AUTHOR]

We present a novel switched-capacitor, integrator-multiplexing, second-order delta-sigma modulator (DSM) featuring a single differential difference amplifier (DDA). Power consumption is low and resolution is high when this DSM is used for portable electroencephalographic applications. A single DDA (rather than a conventional operational transconductance amplifier) with appropriate switch and capacitor architectures is used to create the second-order switched-capacitor DSM. The configuration ensures that the resolution is high. The modulator was implemented using a standard 180 nm complementary metal–oxide–silicon process. At a supply voltage of 1.8 V, a signal bandwidth of 250 Hz and a sampling frequency of 200 kHz, simulations demonstrated that the modulator achieved an 82 dB peak signal-to-noise–distortion ratio and an effective number of bits of 14. [ABSTRACT FROM AUTHOR]

This letter presents a compact lumped‐element two‐way differential to single‐ended Wilkinson power combiner with embedded impedance transformation. It consists of two transformer baluns and two parallel resistance and capacitor (RC) branches. The two transformers generate high‐order impedance transformation networks at even‐mode operation and form resonators together with the two parallel RC branches at odd‐mode operation, thus achieving broadband impedance matching and power combining with a compact area. A proof‐of‐concept prototype working at 1.7 GHz is designed and fabricated. Measurement results show that the peak isolation is 24.5 dB, insertion loss is from 0.34 to 1.15 dB and magnitude and phase imbalance are within 0.1 dB and 1∘ ${1}^{\circ }$, respectively, over the frequency range from 1.37 to 1.97 GHz. The area is only 6.54 mm × $\times $ 6 mm. [ABSTRACT FROM AUTHOR]

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (DTMOS) and unique adaptive biasing technique are used to obtain the enhanced slew-rate with minimized power supply overhead. This dynamic threshold MOS based fully differential OTA operates at ±0.5 V dual supply voltage. It provides average slew-rate as168 V/μS with 0.104 mW static power consumption. The dc gain of the circuit is calculated as 73.86 dB with a 72° phase margin. The figure of merit of proposed OTA is 16.15 [(V/µs).pF/µW] for the load capacitor of 10 pF, which shows significant improvement compared to prior work. To validate the robustness of the proposed design universal voltage mode filter is designed and simulated as its application. Mentor Graphics Eldospice with 0.18 μm TSMC level 53 CMOS technology has been used to verify the performance of the proposed circuit and its application. [ABSTRACT FROM AUTHOR]

With the principle of the traditional band pass filter (BPF) and the 0.6-µm BiCMOS process, an operational transconductance amplifier (OTA-C) type BPF which central frequency could be tuned linearly in the infrared receiver (IR) chip was proposed. The BPF uses the improved bipolar OTA circuit. The pre-stage of the negative feedback increases the input voltage range. The second stage is the differential transconductance amplifier which tunes the central frequency linearly. The whole circuit is simulated by the Cadence software. When the working temperature is 25? and the working voltage is 5V, the result shows that central frequency could quadrature tunable and the central frequency could be linear adjusted between 24 KHz and 49 KHz. The central frequency is 35.04 KHz and the gain is 21.45dB while the frequency modulation (FM) code is 10010. The test results can satisfy the actual needs in the IR chip. [ABSTRACT FROM AUTHOR]

To suppress errors in a touch readout circuit due to display noise, differential sensing using fully differential amplifiers is widely used. However, conventional differential sensing methods require additional circuits or increase circuit complexity, thus increasing power consumption and circuit area or requiring additional dummy RX line on the touch panel. In this study, we propose a compact touch readout circuit composed of a single-ended amplifier while keeping the display noise suppression of differential sensing so as to minimize power consumption and circuit area increase and avoid the need for additional dummy RX line. The proposed touch readout circuit for is fabricated in circuit area of 0.4 mm2 with 0.35 µm 3.3 V CMOS process and measured for 10.1-inch touch panel on top of a TFT-LCD panel. With the proposed touch readout circuit, the signal-to-noise ratio (SNR) is improved by up to 13.1 dB compared to the conventional touch readout circuit using single-ended amplifiers. [ABSTRACT FROM AUTHOR]

The application of a versatile, low‐temperature thin‐film transistor (TFT) technology is presently described as the implementation on a flexible substrate of an analog front‐end (AFE) system for the acquisition of bio‐potential signals. The technology is based on semiconducting amorphous indium‐gallium‐zinc oxide (IGZO). The AFE system consists of three monolithically integrated constituent components: a bias‐filter circuit with a bio‐compatible low cut‐off frequency of ≈1 Hz, a 4‐stage differential amplifier offering a large gain‐bandwidth product of ≈955 kHz, and an additional notch filter exhibiting over 30 dB suppression of the power‐line noise. Respectively built using conductive IGZO electrodes with thermally induced donor agents and enhancement‐mode fluorinated IGZO TFTs with exceptionally low leakage current, both capacitors and resistors with significantly reduced footprints are realized. Defined as the ratio of the gain‐bandwidth product of an AFE system to its area, a record‐setting figure‐of‐merit of ≈86 kHz mm−2 is achieved. This is about an order of magnitude larger than the < 10 kHz mm−2 of the nearest benchmark. Requiring no supplementary off‐substrate signal‐conditioning components and occupying an area of ≈11 mm2, the stand‐alone AFE system is successfully applied to both electromyography and electrocardiography (ECG). [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwidth product of 10 MHz when driving a 150 pF load capacitance. Good robustness is achieved under PVT variations, in particular for voltage gain, offset voltage, and phase margin. State-of-the-art small signal figures of merit and limited area footprint are key characteristics of the proposed amplifier. [ABSTRACT FROM AUTHOR]

The implementation of a 0.38 V K-band low-power fully differential low-noise amplifier (LNA) in a 45 nm silicon-on-insulator (SOI) process is presented. The proposed architecture employs a two-stage approach with transformer-based interstage matching networks to minimize circuit area. The proposed LNA covers the frequency range from 20.3 to 24.1 GHz, it achieves a noise figure (NF) as low as 2.2 dB, and a gain of 12.9 dB, with a power consumption of 11.7 mW from a 0.38 V DC supply in a very compact area (0.15 mm2) excluding pads. Non-linearity simulations show the proposed circuit achieves a Po1dB of −7.3 dBm, and an OIP3 (Output Third Order Intercept) of 7 dBm. The transformers allow improved area use since they are simultaneously used as matching networks, RF chokes to bias the active devices, baluns at the input and output terminals to convert the single-ended signal into differential mode, and vice versa, and facilitates the interconnection with the upcoming stages. We used a state-of-the-art tool that generates the desired inductances to perform impedance matching for a given frequency and coupling factor value. A comparison with similar works proves the proposed LNA achieves a very low NF and the lowest power consumption reported in a differential circuit. [ABSTRACT FROM AUTHOR]

This work reports the design, modelling, and simulation of a novel polymer MEMS gas sensor platform called a ring–flexure–membrane (RFM) suspended gate field effect transistor (SGFET). The sensor consists of a suspended polymer (SU-8) MEMS based RFM structure holding the gate of the SGFET with the gas sensing layer on top of the outer ring. During gas adsorption, the polymer ring–flexure–membrane architecture ensures a constant gate capacitance change throughout the gate area of the SGFET. This leads to efficient transduction of the gas adsorption-induced nanomechanical motion input to the change in the output current of the SGFET, thus improving the sensitivity. The sensor performance has been evaluated for sensing hydrogen gas using the finite element method (FEM) and TCAD simulation tools. The MEMS design and simulation of the RFM structure is carried out using CoventorWare 10.3, and the design, modelling, and simulation of the SGFET array is carried out using the Synopsis Sentaurus TCAD. A differential amplifier circuit using RFM-SGFET is designed and simulated in Cadence Virtuoso using the lookup table (LUT) of the RFM-SGFET. The differential amplifier exhibits a sensitivity of 2.8 mV/MPa for a gate bias of 3 V and a maximum detection range of up to 1% hydrogen gas concentration. This work also presents a detailed fabrication process integration plan to realize the RFM-SGFET sensor using a tailored self-aligned CMOS process adopting the surface micromachining process. [ABSTRACT FROM AUTHOR]

This paper outlines the use of charge detection mass spectrometry to simultaneously measure the charge and mass of micron-sized particles. In a flow-through instrument, the detection of charge was achieved through charge induction onto cylindrical electrodes that connect to a differential amplifier. Mass was determined by particle acceleration under the influence of an electric field. Particles ranging from 30 to 400 fg (3 to 7 µm diameter) were tested. The detector design can measure particle mass within 10% accuracy for particles up to 620 fg with total charge ranging from 500e− to 56 ke−. This charge and mass range are expected to be relevant for dust on Mars. [ABSTRACT FROM AUTHOR]