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Numerical simulations, characterization methods and integration processes are developed to examine and optimize three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance. The impact of a high-[kappa] metal TiN/Hf[O.sub.2] gate stack introduction on the MCFET electrical properties is studied, and the methods to reduce the increase in series resistance by optimizing the source/drain (S/D) shape and the S/D silicide position are discussed.

An optimized multi-channel field-effect transistor (MCFET) structure fabricated on a silicon-on-insulator (SOI) substrate with a silicon-on-nothing (SON) process is presented and its performance is analyzed. The current gain of the MCFET structure, its transport properties and specific electrostatic properties are examined, and it is observed that the bottom channel in narrow devices increases the drain current of the MCFET structure without degrading its electrostatic characteristics.

The experimental ballistic ratio, injection velocity and carrier mean-free path evolutions with the transistor gate length, the inversion charge and the temperature are examined in n- and p-FDSOI devices. The evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature is used for examining the mobility degradation with decreasing gate lengths, signifying the importance of Coulomb scattering on the mobility behavior.

A new experimental method is described for determining the backscattering coefficient and the ballistic ratio of n- and p-FDSOI and multigate nanodevices. Universal abaci are developed in order to accurately extract backscattering coefficients for n- and p-FDSOI MOSFETs both in linear and saturated regimes.

A full-quantum three-dimensional self-consistent simulation is used to analyze the lateral size effects on surface-roughness-limited mobility in silicon-nanowire field-effect transistors (FETs). The results showed that the qualitative behavior of the effective mobility of devices is strongly dependant on the wire section.

The anomalous breakdown behavior of the impact-ionization metal-oxide-semiconductor (I-MOS) is examined. Findings reveal the occurrence of the first breakdown at the width borders of the device, which is followed, by the theoretical volume breakdown.

A quantitative evaluation of the intrinsic reliability limits of floating-gate (FG) memories in the decananometer range due to the reduction of collective phenomena and to the dominance of single-electron stochastic behaviors is presented. A model that predicts the intrinsic dispersions of the memory retention time and programming window is proposed, and the experimental results obtained on ultrasound memory devices are used to validate this model.

The impact of some geometrical parameters on the ionization MOSFET (IMOS) performance such as, the gate length, the intrinsic length and the Si film thickness is investigated. The static and dynamic behaviors of an IMOS inverter are studied and the maximum frequency of the inverter is investigated by simulating an IMOS ring oscillator.

A study to describe an extensive experimental research of TiN/HfO(sub 2)/SiGE and TiN/HfO(sub 2)/Si cap/SiGE gate stacked-transistors is conducted. The results reveal that due to the interface optimization, Si(sub 0.72)Ge(sub 0.28) pMOSFETs exhibit a 58% higher mobility at effective field than the universal SiO(sub 2)/Si reference and a 90% higher mobility than the HfO(sub 2)/Si reference.

The experimental evaluation of the gate architectures influence on the performance of double gate (DG) silicon-on-insulator (SOI) MOSFETs is reported. DG transistors show improved short channel effects control, higher saturation current and improved mobility.

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate is optimized and is shown to be compatible with ultra large-scale integration (ULSI) circuit fabrication. Uniform and reliable electrical characteristics are demonstrated for diverse metal oxide semiconductor (MOS) pattern structures.