Search

Foundry technology includes a family of processes that traditionally consume high amounts of energy. It is fundamental to apply the principles of Sustainable Manufacturing to increase the energy efficiency of these processes. This paper describes the research activity carried out to improve the efficiency of a carousel, which allows the automatisation of aluminium gravity die casting process, consisting of different phases: die preparation, filling with molten aluminium alloy, solidification time, die opening, and part extraction. It is demonstrated that the efficiency is a function of the disposition of the dies mounted on the carousel, due to the solidification time (which is the limiting process parameter), and different cycle times depending on the realised product. The authors propose an optimised layout, which reduces the cycle time while maintaining the same level of the casting final quality. This reduction in the cycle time significantly improves the sustainability of the foundry process.

Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified a few suitable process flows. Within the plasma dicing process flows, laser grooving before plasma etching was shown to be a key unit process to control the resulting die sidewall quality. Significant improvement on laser grooving quality has been demonstrated. Through these efforts, extremely narrow kerfs and near ideal dies strengths were achieved on Si dies. The Bosch-etching based plasma dicing process generates fluorinated polymer residues both on the Si die sidewalls as well as under the topography overhangs on wafer surfaces, such as under the solder balls or micro-bumps. The fluorinated polymers in certain areas cannot be cleaned by an in-chamber post-treatments. Multiple wet chemistry-based cleaning methods demonstrated excellent process capability, and are compatible with plasma singulated dies-on-tape handling. Lastly, many methods exist for backside metal and under Si die-attach-film (DAF) separations. The authors highlighted recent processing results suitable for post-plasma dicing die separations of such film materials.

The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment. One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.

High volume aligned wafer bonding processes typically separate the wafer to wafer alignment process from the wafer bonding process and this wafer to wafer alignment is normally done in an ambient atmosphere. While this process flow has worked well and enabled the proliferation of MEMS devices in the last decade, it does have limitations. The primary issue is the exposure to water vapor and ambient atmosphere which limits the preprocessing that can be done and maintained on the wafers to be bonded. Performing the wafer to wafer alignment, handling, and wafer bonding in a high vacuum environment allow specialized preprocessing of the wafers prior to alignment and bonding. The most basic preprocessing enabled by this high vacuum environment is the open face dehydration bake of wafers prior to alignment to alignment and bonding. When done in a cluster tool, a chamber can be dedicated to baking out the wafers to minimizing the effect of outgassing on the final vacuum level in the MEMS device. If one wafer needs a high temperature bakeout and getter activation and one wafer is limited to a low temperature bakeout this is possible by using two chamber in the cluster tool – one for the high temperature backout and one for the low temperature bakeout. Microbolometers that use vanadium oxide as the sensor layer are an example of a device needing high and low temperature bakeout. Another preprocessing enabled by the high vacuum cluster tool is a surface treatment which removes oxides from the surface, increases the surface energy, and enables the formation of covalent bonds at room temperature in the case of Si-Si bonding. This low temperature covalent bond has been shown to have an oxide free interface with a minimized amorphous layer as well as very low metal contamination. Also, because the bonding is done at or near room temperature it is possible to bond materials with substantially different CTES such a GaN to SiC This new technology will enable improved vacuum encapsulation as well as the manufacture of new, high performance engineered substrates. The latest process results as well as process flows and required equipment capabilities will be presented.

Miniaturization trend progresses continuously and enables an increasing integration level up to 3D system in package (3D-SiP). Thus, the structure of electronic packages is getting more and more complex and the material compositions often are heterogeneous mixtures of metals, polymers and ceramics. This causes challenging requirements for the investigation and reliability characterization of materials, interfaces, components and systems. The target positions are often buried or covered. Additionally the cover and housing materials are increasingly designed for harsh environment applications and so resistant against chemical attack. All these developments make the preparation for e.g. local access to perform electrical measurements or artefact free cross sectioning more and more complex. Focused ion beam preparation is limited in terms of ablation volume. Chemical decapping does not allow opening a small area very selectively and fails increasingly on the resistivity of the mold compounds against chemicals. Metallographic cross sectioning does not preserve the function of the system or can introduce artifacts which are limiting further investigations like element detection or thin film microstructure analyzes. Within all these difficulties the paper presents a new laser preparation tool for multi-purpose capabilities in failure diagnostics and reliability investigations. Several case studies show that the tool is usable for target and large area decapsulation of molding and protective gel coverage materials with no significant thermal impact. Also stacked die preparation for 3D package analyzes and pre-preparation for multi-position TEM lamellas are possible.

This chapter describes the activation of a gas-phase or a gas-surface reaction using heat or light. The atoms and molecules that take part in the chemical reactions are neutral. Neutrals produced by a downstream plasma source are not considered here. The pressures span atmospheric pressure to the mTorr range, with concentrations and temperatures at or close to the condensation point. After discussing the processing window for gas-phase processes and comparing them to similar liquid-phase processes, several enabling applications are listed. The chemistries and mechanisms are described first in general for any gas-surface reaction followed by details of the primary processes in use today: oxide removal with HF vapor, organic and resist removal with ozone, and metal removal with chlorine activated by ultraviolet light. The gas-phase cleaning processes are those a process engineer is likely to encounter: front-end-of-line including isolation, gate and prefurnace, and pre-epi modules; middle of line contact; and back-end-of-line and hard mask trim and nanostructure formation, polysilicon emitters, and pre-thin film measurement. Finally, the gas-phase processing equipment in use today is described. Although gas-phase cleaning has not displaced liquid-phase for integrated circuit manufacturing steps as initially anticipated, the selectivity that is possible in the gas-phase and its vacuum compatibility have enabled several niche applications.

This paper describes an optimized out-of-plane fabrication method for neural 3D high-aspect-ratio microelectrode array (MEA) based on a dicing technology platform (a standard procedure in semiconductor industry). The proposed MEA fabrication required important modifications in the dicing process. Since electrodes length reaches up to 4 mm, the main hindrance was the 2 mm cutting depth limit allowed for dicing machines with regular blades. This new procedure consisted on modifying Z-axis calibration, so cuts as deep as the exposure of blades were possible. The employment of proper blades for each fabrication step was also mandatory. Thin and high-exposure blades were used for deep cuts in silicon wafers, and V-shaped blades were employed to produce sharpened tips on the electrodes. Moreover, parameters as very low-cut speeds were essential to avoid wafer chipping and microcracks. Results showed high-precision and high-quality cuts in all steps of the 3D MEA fabrication, without unnecessary additional steps of etching post-processing. The optimized fabrication process was successfully demonstrated with a 3D neural probe array comprising 36 individually addressable electrodes.

Display Omitted Chip to wafer self-alignment phenomenon was successfully identified into 3 steps.Hybrid chip-dicing process was developed for a better yield and alignment accuracy.Surface activated bonding was introduced for wafer level chip transfer at room temperature.Practically valuable for size-free and flexible MEMS-IC integration in wafer scale. Wafer level chip scale package (WLCSP) is one of the most promising methods for the integration of micro-electromechanical systems (MEMS) with integrated circuits (IC). In our previous works, we have successfully developed a 2-step approach by using a carrier wafer for size-free MEMS-IC integration. This approach exhibits both excellent process flexibility and high efficiency. This approach has been proved practically valuable when compared to chip to wafer (C2W) bonding or wafer to wafer (W2W) bonding. For the improvement of above approach, the phenomenon of the chip to carrier wafer self-alignment was investigated in this work. The process parameters and the chip-dicing processes, which may affect yields and accuracy of the self-alignment, were analyzed. A hybrid process was then proposed for chip-dicing to reduce the process cost as well as to decrease the exhaust of greenhouse gases. Moreover, a surface activated room temperature bonding process was introduced and optimized for transferring of above chips from the carrier wafer to a target wafer with less damage to those chips. A full size-free MEMS-IC integration process was finally demonstrated, and then evaluated from both electrical and mechanical points-of-view.

This paper introduces a heterogeneous die integration process using electroplated copper to mount a bare die into a silicon handling wafer while simultaneously forming vertical, through-wafer vias. Deep reactive-ion etching is used to form openings in the handling wafer allowing the die to be flush-mounted for minimal device thickness. The backsides of the support wafer and die are coated by copper sputtering and electroplating, which physically secures the die in place. Electrical isolation is achieved through passivation of the silicon handle wafer sidewalls before copper electroplating. Wet thermal oxide growth was chosen over plasma-enhanced chemical vapor deposition as the sidewall passivation technique, as wet thermal oxide was found to yield superior coverage and uniformity. Topside interconnects were realized using a previously established thick-film copper metallization process. A $3\times 3$ die array was successfully produced and tested for die-to-die connectivity. Thermal modeling of the fabricated devices showed that power densities up to 1 W/cm $^{2}$ could be accommodated while keeping the maximum temperature below 85 °C.

In this letter, an innovative fabrication method for InGaN-based light-emitting diode (LED) was proposed, and the produced optical device was called the wafer-level InGaN-based thin-film flip-chip LEDs (wTFFC-LEDs). Packaging technologies, such as wafer-to-wafer bonding, laser lift-off, textured surface, and interconnection techniques, were applied to complete the device. Through this architecture, the absorption caused by electrodes in traditional vertical injection LEDs (V-LEDs) can be minimized, as well as the light extraction efficiency can be improved. Light-output power of wTFFC-LEDs (350 mA) was increased by 36.5% and 17.2% compared with the V-LEDs and flip-chip LEDs. Furthermore, the external quantum efficiency was also relatively enhanced by 36.3% and 15.5% higher than those of reference devices.

Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die ...

Packaging the integrated circuit (IC) chip is a necessary step in the manufacturing process of IC products. In general, wafers with the same size and process should have a fixed number of packaged dies. However, many factors decrease the number of the actually packaged dies, such as die scratching, die contamination, and die breakage, which are not considered in the existing die-counting methods. Here we propose a robust method that can automatically determine the number of actual packaged dies by using machine vision techniques. During the inspection, the image is taken from the top of the wafer, in which most dies have been removed and packaged. There are five steps in the proposed method: wafer region detection, wafer position calibration, dies region detection, detection of die sawing lines, and die number counting. The abnormal cases of fractional dies in the wafer boundary and dropped dies during the packaging are considered in the proposed method as well. The experimental results show that the precision and recall rates reach 99.83% and 99.84%, respectively, when determining the numbers of actual packaged dies in the 41 test cases.

This paper presents a novel combined through-wafer-groove fabrication approach, which is applied to the wafer level packaging (WLP) of GaAs charge coupled devices (CCD) for electrical interconnection. The combined methodology includes mechanical dicing of the groove and wet chemical etching for polishing. The parameters of the mechanical dicing are researched, including feed speed, dicing directions of the wafer, and cutting depth, to minimize the chipping. Two kinds of chemical solution are tried, and the results are discussed. Besides, the etch rate is measured, which provides a guideline for the process design. Finally, GaAs-CCD WLP sample is achieved and the electrical properties are tested to validate the feasibility of this fabrication approach. This methodology is featured by low cost, low process temperature, and good process uniformity.

Display Omitted Fully automated laser-based ellipsometry for on product wafer measurements.Complete process characterization of advanced packaging applications.Superior fleet matching on multi-layer stacks using feed forward metrology.Accurate, high throughput measurements. The growing need for smaller, faster devices that consume less power at low cost has led to advances in wafer level packaging. The increasingly complex process employed at OSATs has generated a need for more advanced and automated measurement techniques. In this paper, we present results from the adoption of Focused Beam Ellipsometry in the characterization of thickness and optical constants of various single and multi-layer dielectrics films, thick photoresists on both blanket and product wafers. Measurements are routinely made post-deposition, post-etch and pre- and post CMP process. Wafer stress/wafer bow measurements provide information on the mechanical integrity of the films. The rapid non-contact, non-destructive technology enables full wafer characterization and provides information in minutes on product wafers.

Resonant micro-sensors are single-sided fabricated in non-SOI single wafer and experimentally used for ppm-level organo-phosphorous gas detection.Display Omitted We develop a single-side fabrication in non-SOI wafer for dog-bone microresonator.The IC-foundry compatible process has been transferred to a foundry company.Much small sized resonator is fabricated with the low-cost high-yield technique.New resonator has similar high resonant performance to the traditional SOI one.The resonant biochem sensor achieves rapid precise detection to ppm-level VOC gas. This study presents 'dog-bone' structured bulk-mode resonant gas sensors that can be low-cost volume fabricated in standard IC foundries. Without the need for MEMS-specific processes like double-side aligned photolithography and wafer-to-wafer bonding, the sensor fabrication can be completed in standard IC-foundries, thereby showing advantage in low-cost mass production and application. Based on a diaphragm-on-cavity structure made by a MIS (micro-openings inter-etch and sealing) micromachining technology in ordinary (non-SOI) single-wafer, the resonator fabrication is further completed with simple dry etching and metal interconnection. With similar fabrication scheme to semiconductor IC chips, herein the 3-D micromachining processes are only implemented from the front-side of the wafer (with unpolished wafer backside) and all the fabrication steps utilize IC-foundry available processes. After loading with gas sensitive material, the resonant sensors are ready for application. For comparison, traditional sensors with identical resonator structure are also fabricated in SOI wafer with double-sided process. Besides the measured similar resonance performance for the two sensors, the new sensor is advantageous in smaller dimensions (0.5mmi?0.5mm) and much lower volume-fabrication cost (in ASMC, a 6-inch IC foundry company in Shanghai) of one US-cent per sensor. By loading an organo-phosphor sensitive chemical-group modified hyper-branched polymer onto the new resonator, the disposable biochemical micro-sensor is used to rapidly detect organophosphorous pesticide residue for food-safety and agriculture applications. The resonant chemical sensor experimentally performs linear and repeatable detection of ppm-level organo-phosphorous vapor.

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

The development of adhesives that enable handling, processing, and assembly of thin wafers and die is a key technical challenge for the realization of 3D devices. We will present on temporary adhesive technology for processing of thinned wafers that is amenable to either mechanical or laser-assisted debonding that can occur at room temperature. Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, thermal stability to 300 °C or higher, and clean room-temperature release directly from the device wafer using either mechanical or laser-assisted debonding We will present successful temporary wafer bonding using a BCB (benzocyclobutene)-based material that can meet these requirements. The mode of adhesive release from a device wafer will be discussed in detail as it relates to wafer thinning and handling, and material physical properties and resistances will be expressed. Formulation requirements needed for successful debonding will be presented, with an emphasis on a laser-debonding scheme that utilizes either a 248nm or 308nm laser source capable of ablating a laser sensitive layer residing between a glass carrier and the temporary wafer bonding material. Successful room temperature tape-peeling of the adhesive film after ablation and carrier removal will be discussed.

Nanoimprint lithography manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. In this paper, we review the advancements in both wafer imprinting and mask replication systems. To address high volume manufacturing concerns, an FPA-1200 NZ2C four station cluster tool is used in order to meet throughput and cost of ownership requirements (CoO). The status of the tool overlay is discussed. Application of a High Order Distortion Correction system to the existing magnification actuator has enabled correction of high order distortion terms up to K20. Because mask replication is required for nanoimprint lithography, improvements to the FPA-1100 NR2 mask replication system are reviewed. Criteria that are crucial to the success of a replication platform include both particle control and image placement (IP) accuracy. Data is presented on both of these subjects. Particle adders were studied over a nine month period. Additionally, with respect to image placement, an IP accuracy (after removing correctables) of 1.0nm in X, 1.1nm in Y has been demonstrated.

Low temperature eutectic solder as an intermediate layer materials for wafer bonding based MEMS packaging, and thin film encapsulation for wafer level vacuum packaging are reviewed. Wafer level vacuum packaging technologies for MEMS micromirrors, micro-relays and NEMS switches are investigated.

We present a novel design of re-usable wafer carrier for safe manual or robotic handling of wafers from tens of μm in thickness. The carrier wafer stack then remains stable through a wide variety temperature, pressure and chemical environments. The carried wafer can then be easily debonded in a bespoke debonding tool with no residue or cleaning steps.

Wafer Level Package (WLP) is a packaging technology focusing on IC packaging at wafer level instead of chip level. Conventional WLPs are designed for fan-in chip scale packaging but the shrinkage of pad pitch and size at the chip to package interface is much faster than the shrinkage at the package to board interface. Fan-Out Wafer Level Package (FO-WLP) is key technology to solve this problem. FO-WLP is generally break into two categories: Mold-first and RDL-first. General Mold-first FO-WLP process steps are follows. 1) Wafer patterning form, 2) Wafer mount on the dicing tape, 3) Dicing, 4) Pick-up and place chips to separate it to necessary distance onto carrier material, silicon or glass wafer, 5) Mold to cover the whole chips, 6) Remove the carrier material, 7) Redistribution Layer (RDL) form, 8) Under Bump Metallization, 9) BGA Ball attach and reflow 10) Dicing. The merit of WLP is wafer level process instead of chip level to decrease manufacturing cost. However, process step 4, pick-up and place is still chip level process, thus this process is a bottleneck process for FO-WLP. We propose a novel pick-up and place process for FO-WLP using tape expansion machine device. We develop a tape expansion machine device that can expand a tape to X-Y lateral expansion, individual control for X-Y. Using this machine device, tape can be widely expanded to control the distance of chip to chip voluntarily.

As technology nodes become smaller it is getting more important to control all aspects of influencing parameters on the deposition of thin films using a CVD process. It is well known that physical parameters like gas flow or temperature heavily influence the deposition rate and the quality/properties of the deposited thin films. To achieve good chamber to chamber matching of the deposition rate and high quality films it is crucial to control the physical parameters. In this paper we will present the wireless measurement of the temperature on the wafer surface up to 400°C under real temperature and process like conditions using the SensArray HighTemp-400 wafer. This approach paves the way for the control or the monitoring of the temperature on the wafer surface for the thin film deposition processes.

Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.

In this paper, a fully BiCMOS integrated microfluidic technology platform for Lab-on Chip (LoC) applications is presented. Fusion bonding and adhesive bonding techniques are applied to realize a 3-wafer-stack integration. A glass wafer is used on top of the BiCMOS wafer and the Si channel wafer to enable simultaneous optical and electrical measurements. An alignment accuracy of less than 1 µm between BiCMOS and channel wafer is achieved while having channel heights between 30 and 100 µm. All the microfluidic process integration steps are kept below 300 °C. The microfluidic inlet and the outlet are positioned on the backside of the wafer stack to provide both the optical inspection and the electrical measurements from the wafer's front side. The developed wafer level integration technique provides high throughput solutions for emerging chemical and biological LoC applications.

Plasma Dicing uses Deep Reactive Ion Etch (DRIE), also known as The Bosch Process. This is a well-established "front-end" technology, used in silicon MEMS micromachining and via etching in 3D packaging, which is now finding a new home as a dicing technology in the "back-end" of semiconductor processing. This paper will discuss the key issues and integration challenges. This is not only in wafer design and preparation, but also how the process flow is not disrupted to the extent where it becomes a hindrance to the adoption of a technology that offers so many potential benefits.

Fan-Out Wafer Level Packaging (FOWLP) is one of the latest trends in microelectronics packaging. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, low thermal resistance, high RF performance due to shorter interconnects together, as the direct IC connection by thin film metallization instead of wire bonds or flip chip bumps yields low parasitic effects. Especially inductance of FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also integrate embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications. FOWLP is in volume manufacturing since a couple of years and services are offered in Asia as well as in Europe. But especially for low volume quantities and prototyping no dedicated packaging services are available. Adapting the success story of Si-based Multi-Project Wafer technology that offers fast and cost-effective access to low numbers of chips, Multi-Project Fan-out Wafer Level Packaging might be an option to address heterogeneous integration for the prototyping market. Within this study such a Multi-Project Fan-out Wafer Level Package (MPFOWLP) technology has been developed and evaluated with focus on RF applications. To demonstrate an entire prototyping run Si dies from a Multi-Project Wafer were used. For technology evaluation six different chips have been selected where five of them were functional dies for application frequencies up to 120 GHz. Additionally one dedicated test die was used, allowing on the one hand RF characterization of the technology approach and on the other hand interconnect testing and reliability characterization. A uniform package size of 10 × 10 mm2 was chosen and design rules for the redistribution layer (RDL) have been fixed at the beginning. A two metal layer design and a BGA pin-out have been chosen allowing also the integration of antenna structures in the RDL. Based on these boundary conditions package designs have been done. Reticle and fan-out wafer design were integrated on a 200 mm reconfigured wafer. Based on this approach around 38 packages of each type come out of one wafer. Packaging technology followed the RDL last approach, where dies are first embedded into mold compound forming a reconfigured wafer and subsequently a thin film redistribution layer is applied to the reconfigured wafer. Final process steps are solder ball placement and package singulation by dicing. In summary this paper describes the development and evaluation run of a Multi-Project Fan-out Wafer Level Package approach for RF application.

Specifications and fabrication process suitable for a small wafer with the diameter of half-inch, which is used for a minimal fab, is presented. We beveled wafer edge by rapping and polishing in order to clean the edge and to suppress the strong surface tension at the edge. To show the crystallographic orientation of the wafer, we introduced laser marking process. By the processes, we have formed silicon wafer that is suitable for fabricating electronic devices. Formed MOS capacitor on the wafer revealed that the density of interface states (D it ) was 7.8×1010 states/cm2 as the average of 37 wafers.

This chapter provides technological information on the manufacturing of crisp sheet wafers—flat wafer sheets and hollow or shaped wafer sheets. Then, using the example of sugar wafer cookies from flat wafers, it discusses all the steps required—from baking the sheet to packing the final product. Flat wafer-based wafer cookies are the main wafer products worldwide. Special emphasis is on the technologies of batter mixing, the technical basics, the mechanisms of wafer baking, details on potential manufacturing issues as well as the ways to resolve them, and quality assurance issues.

This chapter provides technological information on the manufacturing of crisp nonsheet wafers—molded wafer cones and cups, rolled sugar wafer cones, sugar wafer reels, fan wafers, and flute wafers (wafer sticks). This includes steps such as ingredient selection, batter preparation, wafer baking, and packing the products. Further details on potential manufacturing issues as well as the ways to resolve them are included.

Through-Silicon-Via (TSV) wafer processes have been reviewed by several authors previously, including temporary adhesive wafer bonding, high aspect ratio silicon etch, and wafer singulation. This chapter starts with a brief overview of TSV wafer fabrication and singulation processes. Then, it focuses on several key process issues which have not been discussed in previous review articles. The first process issue discussed in details here is the device wafer buckling or wrinkling postwafer thinning. This challenge might cause yield loss at the downstream lithography process. The fundamental mechanism behind this issue is investigated and several solutions are proposed. The second process discussed in details here is wafer debonding. Based on viscosity definition and wafer geometry, a closed-form analytical solution is proposed for the thermal sliding wafer debonding process, which can be used for process control and throughput optimization. The next two processes discussed are laser scribe and saw dicing, which impact die edge chipping and low-k inter layer dielectric (ILD) delamination. A closed-form solution of chipping induced by saw dicing is also investigated. The last process discussed in this chapter is the challenges and solution options for die pick and place.

To meet the changing demands of consumer product form factors, there has been a steady shift to thinner and smaller semiconductor die, both of which increase the challenges for die singulation. The traditional approach of saw dicing is facing new limitations due to die damage and throughput. Compounding these issues is the finite width of saw blades, saw blade loading from clearing multiple materials, and orthogonal layout restrictions. Laser dicing has been introduced to address some of these issues, but faces other limitations such as damage from the heat affected zone, ablation residues, throughput, and material incompatibilities (changes in transparency and absorption in the street). In some cases, a combination of both saw and laser has been utilized to surmount some of the technical obstacles. The recently introduced approach of front-side plasma singulation circumvents many of the limitations of saws and lasers. The technology presented in this work uses standard dicing tape and frames, is through-wafer complete die separation, and does not involve a subsequent wafer thinning or die cleaving step. Our approach utilizes lithographically defined singulation lines with typical widths of 10–15μm, and delivers chip/crack-free edges with low-stress rounded corners. The parallel nature of this singulation method enables non-orthogonal and non-linear singulation streets allowing die layout and design flexibility not achievable by saws and/or lasers. As a consequence, plasma singulation produces increased good die per wafer through better wafer area utilization, lower die failure (reduced corner stress with rounded geometry), and flexibility in die placement near wafer edge on larger die. One of the unique advantages is that this technology can be implemented without addition of any new masking layers but instead the use of the existing passivation, metals and/or upper dielectrics as masks. Implementing this technology across a wide range of die applications such as power, memory, logic, imaging sensors, LEDs, and MEMS must address a diverse range of variables such as compatible materials, bond pads/bumps, and backmetal. For dies with backside metal, a non-etch based method to allow full die separation while the dies are still attached to tape has been demonstrated.

the paper introduced the bare silicon crystal how to become a wafer .then, it told the processing of wafers to produce integrated circuits .Today, most integrated circuits (ICs) are made of silicon. every integrated circuit is tested and functional and formed a dies. At last , the article explain feature size and the number of gross die per wafer (DPW).

By co-integrating optics and electronics on the same chip, high-functionality, high-performance and highly integrated devices can be fabricated with a well-mastered microelectronics fabrication process. Different integration schemes with bonding are presented either with die-to-wafer or wafer to wafer bonding. Depending of the applications and the maturity level of the technologies, the strategies for integration will differ.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

The success of any fixed prosthesis is multifactorial right from preparation to passive fit during cementation, various phases both in clinical and laboratory procedures. Die preparation is a procedure without which the success of any prosthesis is compromised. Different systems have been used for preparing die which serves as a platform for the construction of pattern for future prosthesis. Over the years, these die systems passed various modifications and innovations striving towards precision that governs the fit of any prosthesis. This article evaluates two such systems which evolved independently for their positional accuracy through-out a simulated laboratory procedure.

wafer processing is one process of the IC industry which is a booming area nowadays, the quality of the production of this course depends on the performance of the film which is formed by deposition. And one of the most important factors influencing the performance is working pressure. Variable structure chamber for flowing experiment and testing which is a multifunction testing platform with changeable structure and sufficient measurement points all-covered the chamber, a device has been designed and manufactured to measure and research vacuum flow filed. By using this equipment, the pressure in vacuum chamber could be measured precisely and promptly, thus relationships among the size and shape of the chamber, the pressure, and the gauges would be clear, there would be helpful for vacuum measurement. Background The course of manufacturing a chip of IC production including 400~500 processes which could be divide into two categories: wafer processing which is FEOL (front-end-of-line) and chip packaging which is BEOL (back end of line), as it illustrated in Fig. 1. Wafer manufacturing is a process of exacting and refining high purity silicon (usually 99.999%) from silica; Wafer processing is depositing a thin film (among 100umto 22nm, according to the requirement and depending on technology) which contains required elements on the face of the original wafer; Dicing is chipping out wafer into little blockages to face different requirement; Assemble and packaging is fabricating chip into IC component. During the course of Wafer processing, the working condition is usually under low velocity, high vacuum and high temperature condition (depends on the characteristics of sediment), take the projectDeposition of Hydrogenated Amorphous Siliconas an example---- 5.0sccm, 11.0~16.0mtor, and 250°C[1]. The performance of wafer is decided by the nature of reactors and the processing condition of which a little change would lead a different property of the production. Thus it is necessary and imperative to figure out the relationship among the factors influencing depositing process. And the most important among these factors are pressure, velocity, and temperature. In this paper, a method of pressure measurement based on a device of variable structure chamber for flowing experiment and testing will be introduced. Fig. 1, Semiconductor manufacturing process

In the silicon wafer polishing process, the mounting of wafer on the polishing head could be greatly influential in final quality of finished wafers. This paper focuses on the waxless wafer mounting technique which could replace the traditional wax wafer mounting. Mounting of wafers on the carrier block using a wetted porous template provides a simple way of securing wafer on polishing head for precision wafer polishing. Demounting of wafers from the porous pad is carried out by using the water jet impingement which takes only a couple of seconds for wafer demounting. A series of wafer polishing tests of 8 inch silicon wafers using the present wafer mounting system found that the developed waxless wafer mounting could be quite suitable for producing the wafers of the excellent surface qualities by meeting industry standard such as SBIR, LLS, and production yield.