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The development of on-chip nonlinear optical devices in silicon is of great importance to silicon photonics and silicon chip based quantum information processing technologies. With the aim for a viable solution to overcome the lack of second harmonic generation (SHG) in Si, which is fundamentally limited by its centrosymmetric lattice structure, our work investigates SHG behaviors from Si (100) crystals with silver nanostructures formed following deposition of an ultrathin silver film and subsequent annealing. This study is aided by additional techniques, including x-ray photoelectron spectroscopy for measuring surface band bending, secondary electron microscopy for monitoring surface morphology, and Raman scattering for assessing crystal stress. The resultant Ag nanostructures are found to strongly impact the second order nonlinear polarizations in the Si surface regions rather than the bulk. The SHG intensities are increased following the Ag deposition but reduced below the Si control levels after annealing at 600 and 700 °C, which may be due to charge transfer from Ag to SiO2/Si and/or passivation of interfacial defects. Interestingly, annealing at higher temperatures (800 and 900 °C) leads to the formation of Ag nano-shell structures embedded below the SiO2/Si interface, different from the as-deposited and low-temperature annealing cases with Ag nano-spheroid structures appearing on the surface, and concomitantly, the SHG intensities are recovered and even exceed the level for the as-deposited sample in the p-Si case. The enhanced SHG following high-temperature annealing, particularly at 800 °C, is attributed to a redshift of the localized plasmon resonance of these embedded Ag nano-shells relative to the surface-covered nano-spheroids that leads to localized surface plasmon resonance around the fundamental light wavelength. Other factors including electric-field-induced SHG and the effects of stress or oxide thickness can be ruled out. This work suggests a novel approach to enhance second-order optical nonlinearity in Si through the formation of embedded metal nanostructures. [ABSTRACT FROM AUTHOR]

The development and application of an analysis methodology for charge pumping (CP) measurements in order to extract spatial distributions of traps in Hf[O.sub.2]/Si[O.sub.2] gate stacks is discussed. An increase in the trap density in the SiO2 layer closer to the high-k dielectric is observed.

The image quality in electron microscopy often suffers from lens aberration. As a result of lens aberrations, critical information appears distorted at the atomic scale in high-resolution transmission electron microscopy (HRTEM). In scanning TEM (STEM), the spatial resolution of images and the quality of spectroscopic data are greatly reduced. With the recent introduction of aberration-corrected lenses and monochromators, new and exciting images with sub-0.1-nm spatial resolution are now recorded routinely, and electron energy loss data has been used to determine the location of a single atom in an atomic column. As a result of the decreased focal depth of an aberration-corrected lens used in STEM, the dream of three-dimensional (3-D) atomic resolution is one step closer and for HRTEM it was shown that 3-D imaging with atomic resolution is feasible. However, understanding imaging and spectroscopy in HRTEM and STEM still requires refined modeling of the underlying electron scattering processes by multislice image simulation. Since research into the physics and technology of nanoelectronic devices has already moved into sub-10-nm transistor gate lengths, the need for well-understood imaging and spectroscopy at nanoscale dimensions is already upon us. Fortunately, nanowires and other nanotechnology materials serve as useful test samples as well as being potential materials for future nanoelectronics. This enables early development of microscopy methods that will be used to investigate future generations of integrated circuits. Index Terms--Defects, nanowire, simulation, transmission electron microscopy (TEM).

New methods for monitoring via and line voiding in metal interconnect structures are described. A focused laser beam injects heat into a structure such as a line or via chain, which may have width considerably smaller than the spot size. Conduction of heat, and therefore temperature under the spot, is a function of via or line integrity. Probing the temperature using laser reflection provides a direct nondestructive measure of via continuity or line voiding. Index Terms--Copper interconnect, damascene copper, via, void.

Below the 70-nm node feature sizes and aspect ratios will require great advances in metrology and defect detection capability. Although the International Technology Roadmap for Semiconductors (ITRS) prediction becomes more aggressive with each revision, isolate gate lengths for the 70-nm node are predicted to be below 40 nm for microprocessors (see 2000 ITRS). 70 nm and below feature sizes and high aspect ratios will be characteristic of on-chip interconnect. Memory devices will achieve line densities that will drive all areas of metrology. The device performance required for increasing clock speed and reducing leakage current has been driving new gate stack materials development which is expected to be ready for manufacture at this node and below. On-chip interconnect will have integrated low [kappa] dielectric, copper metal lines, and copper diffusion barrier layer materials predicted by the roadmap will require interconnect design advancements to meet increased clock speeds even if the present rate of advance in clock speed decreases. In this paper, the key metrology and defect detection trends for wafer manufacture are covered. The best available information on critical dimension, gate stack, and interconnect measurement and data management are described in light of the need to obtain statistically relevant information from microscopic features. Index Terms--Critical dimension, junction depth, metrology, thickness measurement.