Search

High-precision hardware tools and innovative technologies developed for the analysis of activity and neuroimaging of intracentral relations of the brain using electroencephalographic methods are important for the diagnostics and correction of the functional state of athletes, prediction of the psychoactive properties of biologically active compounds and their combinations, improvement of the results of clinical studies of neuropsychoactive drugs to optimize their practical application.

The practical aspect of nanotechnology includes the production of devices and their components needed to create, process and manipulate atoms, molecules and nanoparticles. The phenomena of aging and self-heating significantly affect the operation of microelectronic circuits. This paper developed a model of a three-bit, parallel analog-to-digital converter with low power consumption, as a result of which the circuit does not use resistors and comparators. The absence of resistors improves the static power consumption of the circuit and reduces the problems associated with aging and self-heating, while the absence of comparators has a positive effect on the dynamic power consumption. The Parallel A/D converter has been designed for a 14 nm process, at 25°C, for input signals with an amplitude of 1.8 V. The results obtained show that the developed converter uses about 100 times less energy compared to the classical architecture. Since the eight resistors were removed from the circuit, the area of the resulting converter was reduced by at least 8Rnom, where Rnom = 0.7225 μm is the area of the 1 KΩ resistor.

This article presents a BJT-based temperature-to-digital-converter (TDC) that achieves ±0.25 °C 3 sigma -inaccuracy from -40 °C to +180 °C after a heater-assisted voltage calibration (HA-VCAL). Its switched-capacitor (SC) ADC employs two sampling capacitors and, thus, the minimum number of critical sampling switches, which minimizes the effects of switch leakage at high temperatures and improves accuracy. The TDC is also equipped with an on-chip heater, with which the sensing BJTs can be rapidly (2 and operates from 1.8 V.

This brief proposes a 0.3-V resistance and capacitance-to-digital converter (RCDC) using a negative charge-pump switch. The proposed RCDC operates at a subthreshold supply voltage by using the negative charge-pump switch, which turns on a precharge pMOS switch with a negative supply voltage. It converts resistance or capacitance to digital signals. The proposed RCDC was fabricated using a 65-nm CMOS process. It achieves ENOBs of 10.6 bits for the resistance of 1–100k $\Omega $ and the capacitance of 10 pF–10 nF, which correspond to figure-of-merits (FoMs) of 3.03 pJ/step and 2.54 pJ/step, respectively, at the supply voltage of 0.3 V.

This paper proposes a complementary metal oxide semiconductor wearable infrared (IR) light intensity digital converter for monitoring the unplanned self-extubation of patients. The proposed converter could process the IR light intensity without limitations of the field-of-view and is immune to ambient optical noise. Furthermore, the output of the proposed converter can be easily transmitted to Internet of things devices. The sensing area of a monolithic photodiode was $120 \times 120\,\,\mu \text{m}^{2}$ , and the complete size of the chip was $1.21 \times 2.04\,\,\text {mm}^{2}$ . The measured distance between an IR light source and the proposed converter was 15–29 cm, and the measured signal-to-noise-distortion ratio was corresponding to 80.9–74.9 dB. Finally, an experiment was conducted for monitoring the unplanned self-extubation of patients. The results indicate that the proposed chip is suitable for usage in medical institutions.

A Time-Domain Resistance-to-Digital Converter (RDC) with a referential 1-bit ΔΣ Modulated variable resistor is proposed. The proposed RDC converts an input resistance to a frequency and compares a referential variable resistor to decrease a sensor read-out error caused by a non-linearity of an oscillation frequency. A 1-bit ΔΣ modulated variable resistor is demodulated by an oscillator and a counter. Hence a low-pass filter circuit is not required. In addition, non-linearity canceling feedback is proposed to decrease comparison time. This prototype RDC achieves 10.1bits conductance resolution at 1kSps in 10μS to 110μS full-scale range.

In most of digital systems, which require to have high level of resolution, time for digital converter is among the most significant blocks. Time difference amplifier (TDA) is utilized in time to digital converter in order to increase the level of accuracy. In this article, an all-digital TDA is suggested. The proposed TDA consumes delay lines with variation delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and obtain gain of six and chip areas about 0.002 mm2. The maximum calculated addition error is about 5%. The TDA harnesses 0.74 mW power under 1.1 V supply voltage.

A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of VDD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.

This paper proposes a complementary metal–oxide–semiconductor (CMOS) seawater-salinity-to-digital converter for Internet of Things (IoT) applications in fish farms. In contrast to previous studies, the proposed converter not only is suitable for processing seawater salinity but also has immunity to environmental low-frequency noise. Another innovation is that it can be easily delivered through transmission media before the IoT. The performance and functions of the proposed converter were successfully verified through measurements. The measured salinity range was 20–80 g/L, and the corresponding measured signal-to-noise-distortion ratio was 81.3–62.5 dB. The proposed converter is, therefore, suitable for IoT applications in salinity-monitoring devices.

A multifunctional digital signal converter is described, which is used as a channel for the digital conversion and formatting of radio-interferometric signals with bandwidths of up to 512 MHz. The converter allows changes in its function by only a change in the control program, which is administered by the radio-telescope computer. The multifunctional computer can be used for radiometric and spectral measurements and for tests of the receiving–amplifying equipment of the radio telescope.

In this paper, design and simulations of an optoelectronic circuit for the conversion of the optical signal, coming from an interrogation system for FBG sensors, into a digital signal, is presented. The approach is divided into an optical introduction of the interrogation system, an analog section and, finally, digital considerations. The analog processing part is mainly based on the realization of a double stage transimpedance amplifier to obtain, in the working conditions, the best performances required in terms of high gain and wide bandwidth. The output voltage from the analog section is then converted to digital via a 12-bit ADC and sent to an FPGA that processes the defined algorithm in order to obtain the needed optical-electrical linear conversion. The circuit simulations, digital stability and other consideration, including the stability to optical power variability obtained by the numerically simulated interrogation system, are performed, highlighting the peculiarities of this new type of high frequency FBG interrogator.

This paper describes an energy-efficient BJT-based temperature-to-digital converter (TDC) with a state-of-the-art resolution FoM (RFoM) of 5.4pJ·K2. It consists of a BJT front-end, a capacitively-coupled instrumentation amplifier (CCIA) and a 2nd-order continuous-time (CT) ΔΣADC. The front-end and the CCIA employ bitstream-controlled dynamic element matching (DEM) and chopping to mitigate mismatch and 1/f noise without incurring quantization noise fold-back. The sensor achieves ±0.13°C (3σ) inaccuracy from -40 to 125°C and has a supply sensitivity of 8.2mK/V.

A novel resistance-to-digital converter (RDC), based on the integrating type analogue-to-digital converter principle, is presented in this study. The conversion time of the proposed scheme is not a function of the current value of the parameter being measured. Thus, by suitably setting this parameter, the converter can be made to reject the effects of interference at a particular frequency, such as, that due to power-line at 50/60 Hz. Error analysis was conducted to ascertain the effects of non-idealities of various components of the circuit, on its output. Simulation studies were carried out in LTSPICE to verify the linearity and the interference rejection capability of the converter. Further, a prototype RDC was developed in the laboratory and tested to confirm the results of the simulation.

Rethinking analog to digital conversion has become extremely crucial in the race towards aggressively scaled technology nodes with decaying signal swings. The concept of more recent TDCs, which are completely designed in digital domain, make them simpler, easier to manufacture and faster to market. In previous work, LUCOS J. Doge, G. Schonfelder, G. Streil, and A. Konig. An HDR CMOS image sensor with spiking pixels, pixel-level ADC, and linear characteristics. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 49(2):155–158, Feb 2002. , a high dynamic range image sensor using spike based processing with high pixel uniformity had been designed. This motivated a generic ADC concept, which makes use of spike processing, to design a highly effective sensor signal processing system, which carries the promise of robustness to technology scaling, for effective use in IoT and Industrie 4.0. In this work, an ADC concept based on acoustic localization in biological sensory systems has been pursued. An ADC has been designed based on this concept using biological models of spiking neurons. The first proof-of-concept prototype chip SSDCα has been designed in ams 350 nm technology node with area of the chip is 8.5 mm2, sampling rate from DC to 150 kHz, resolution from 8-bit to 13-bit, with 28, 200 transistors, 263 neurons and 517 synapses. The future work will move from 350 nm to 90 nm technology node to show the improvement and robustness of the SSDC with technology scaling.

An improved direct digital converter (IDDC) suitable for bridge-connected resistive sensors is presented in this paper. The input stage of a dual-slope analog-to-digital converter is altered to accommodate a resistive sensor bridge, as its integral part and the logic of conversion incorporate automatic compensation for offset, offset drift, and gain errors. Through a detailed error analysis of the DDC presented earlier, the effects of the non-ideal characteristics of practical components on the performance of the DDC are quantified. From the analysis, it is determined that mismatch between the bridge elements and the input offset of op-amps significantly affect the output. While the earlier version of the DDC requires offline correction for offset and gain errors, the proposed IDDC provides in situ correction for these and hence can also compensate drifts. Simulation studies and experimental results demonstrate the practicality of the proffered scheme and indicate that the worst case error of ±0.2% due to offset in op-amps and mismatch in nominal resistances of sensing elements reduces to ±0.05% with the use of the proposed compensation technique.

In this study will simulate steady state of Digital Down Convertor (DDC) for GSM signal with a narrow frequency range. The MATLAB model that is described in this article simulates the work of the TIGC4016 Quad Digital Down Converter. This converter is used for digital mixing (down conversion) of signals, narrow band low-pass filtering and decimation. To implementation of the model, we use high sample-rate (69,333 MSPS) bandpass signal. The result contains low sample-rate (270.83 KSPS) baseband signal, thus facilitating the demodulation process.

This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator. The TDC is used to measure the fractional part of oscillation period, which realize a high resolution and conversion rate with moderate oscillation frequency. Proposed fractional period estimation technique reduce the required number of TDC and save power consumption. A prototype system was developed and 23 ppm resolution of resistance change at conversion rate of 5kSps was experimentally demonstrated.

This paper presents an ultra-low-power intersignal time-delay-to-digital converter. It introduces polarity-coincidence adaptive time-delay estimation, a mixed-signal processing technique that consumes only 78.2nW for a 3-channel delay estimation. A 0.18um CMOS implementation of the converter has been tested and characterized with controlled and real-life stimuli. This analog-to-feature converter has further been used to estimate the time difference of arrival in an audio-based vehicle-bearing IoT system.

Capacitive sensors have profoundly found their way in everyday life. Devices and instrumentation ranging from specialty equipment to smartphones all employ in one way or the other a capacitive sensor and its associated readout circuit, making the latter ubiquitious. We present a capacitive readout system that automatically adapts its range to the unknown measured capacitance, thereby extending its functional input range, as well as its application and instrumentation compatibility. The proposed system achieves a constant resolution for a range of input capacitance up to 690 pF.

電子通信エネルギー技術研究会 (EE) (2016年1月28-29日, 久留米ホテル エスプリ ), 久留米市, 福岡, 人工衛星のコストパフォーマンス向上のためにバス機器の小型軽量化が期待されている。また、小型軽量化と並行して、新たな付加価値を生み出すインテリジェントなバスシステムの開発が求められており、例えば、宇宙という特殊な環境下における様々な制約を取り払えるようなバス機器開発が進められつつある。JAXAでは、電源の小型軽量化を進めており、現在軌道上にある最新のJAXA開発衛星は、従来機器から質量半減を達成している。更なる小型軽量化及びインテリジェント化を目標に次世代の電力制御技術としてデジタル電源に着目し、研究を行っており、本稿では、デジタル制御技術をベースに衛星の電源開発における種々の制約を排除し、開発におけるフレキシビリティを向上することを目標として行っている分散協調制御電源システムについて、そのシステム構成及び制御アルゴリズムを説明し、実現性の確認を行った試作評価について報告する。, Spacecraft have many components required for existence in orbit, which are known as “BUS systems”. To increase the mass and volumetric ratio of mission payloads in spacecraft, a compact and lightweight BUS system is demanded, in one of response to which JAXA has developed an analog circuit power control unit with half of the ratio of mass and handling power. For future, we has been studying the distributed and cooperation power control with digital circuit to realize not only for lightweight and compact but also for design flexibility of satellites. In this paper, we describe an algorithm of distributed and cooperation power control and a test of an experimental model., 形態: 図版あり, Physical characteristics: Original contains illustrations, 資料番号: AC1600062000

A novel 9-bit time–digital-converter (TDC)-assisted analogue–digital-converter (ADC) supporting energy-efficient high-speed compressive-sensing (CS) operation is presented. With a voltage–time-converter serving as the cross-domain residue conveyer, the proposed two-stage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC front-end and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

Oil palm is one of the famous commercial crops of Thailand. The production is in the 3th rank of the south east Asia, and plantation is still increasing every year. To investigate the feasibility of using electrical capacitance measuring technique as an alternative method for low-cost non-destructive, oil palm fresh oil (CPO) and water have been prepared and studied. One group is concerned with the immiscible fluid and another is all ultrasonic shakes. The mass concentration (x) of CPO varied from 0 g/cm3 to 0.9 g/cm3 and then all experiments were tested on room temperature (25oC). Guard parallel structure has been used in conjunction with AD7747 capacitive to digital converter to obtain capacitance value (y). The results show that y = 0.11987x2 − 0.46104x + 0.47418 with r2 = 0.98098. The model for second sample is y = 0.08965x2 − 0.41335x + 0.3731 with r2 = 0.9554. The capacitance of first sample is higher than the second sample. As previously mentioned, this project aims to make benefit of interest on seasonable optimistic harvests.

A displacement-to-digital converter (DDC) based on inductive (eddy-current) sensor is presented. The sensor is embedded in a self-oscillating front-end, whose 145MHz output is then digitized by a ratiometric ΔΣ ADC. Over a 10μm range, the DDC achieves 1.85nm resolution (1.02 pH), in a 2kHz bandwidth. It draws 9.1mW from a 1.8 V supply making it the most energy-efficient ECS interface ever reported.

A dual slope direct digital converter (DSDDC) suitable for resistive sensor elements already connected in a bridge form is presented. A conventional dual slope analog to digital converter (DS-ADC) is altered with an intentionally introduced instrumentation amplifier (INA) to realize the proposed DDC. The DSDDC accepts bridge connected resistive sensor elements as input and provides a digital output that is proportional to the quantity being sensed by the sensor elements. The results obtained from simulation of the proposed DSDDC indicate a worst case error in the output to be < ±0.03 %. Experimental results from a prototype unit, presented herein, demonstrate the practicality the scheme. Worst case error of the prototype unit was found to be < ±0.07 % with test conducted using standard decade resistance boxes emulating the sensor elements. The worst case error in the prototype was < ±0.05 % when tested with a load-cell made of four strain gauges.