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Biosensors are a type of sensor that have gained prominence in recent years due to their advantages over traditional sensing methods, which are expensive and time-consuming. They are composed of two main parts: a recognizer bioelement and a transducer—both can be of different types depending on the desired application. An optical biosensor based on Surface Plasmon Resonance (SPR) achieves high sensitivity, is label-free and its multilayer construction allows an increase in the selectivity of the target analyte. As the choice of layers in SPR-based biosensors and the analysis of the obtained multilayer configuration is very difficult and expensive, in this work, we present an SPR-based biosensor simulation tool, developed through mathematical modeling, with an easy-to-use interface and several design options for calculating and analyzing the reflectance and angle of incidence of this type of device. The application, developed in Matlab, behaved as expected, offering the user the possibility to export data to Excel and becoming a useful alternative for mathematical analysis of SPR biosensors and its parameters, such as quality factor, detection accuracy and sensitivity.

In this paper it is analysed the performance dependence on the ambient temperature of the constant temperature Wheatstone Bridge architecture for a radiometer. The parameters considered in this analysis are the sensitivity, response time, and circuit power consumption. The analysis was carried out through simulations in SPICE using a developed model of a positive temperature coefficient thermoresistive sensor. The results show that the ambient temperature plays a major influence of the architecture performance evidencing as main limitation of this architecture.

Thermal sigma–delta modulator is a closed-loop measurement approach, where the sensing element performs part of the $\Sigma \Delta$ modulation in the thermal domain. A new architecture is proposed in this paper for measuring the thermal incident radiation using thermoresistive sensors, where the modulator input range is automatically adjusted to fit the complete thermal radiation. The proposed architecture is compared with a similar one, which uses the same transducer interface circuit but without range adjustment, and is validated experimentally with a reference pyranometer. The proposed architecture has the main advantage of presenting a signal-to-noise ratio and sensitivity that is independent of the ambient temperature range definition. Experimental results for an ambient temperature range of 45 °C show a gain of 13 dB over the similar one.

Incremental sigma-delta (IΣΔ) converters are adequate to be used in time-multiplexed multichannel measurement systems, where low frequency and high resolution are required. To achieve low latency channel switching, Cascade of Integrators (CoI) digital decimator filters are normally employed in these converters. Still, the search for higher resolution and bandwidth leads the designers to consider high-order converters, especially in multichannel systems. This paper presents a detailed analysis of the impact of using high-order CoI filters on the input referred noise of IΣΔ converters, which is affected by the different weighting of the filter coefficients. This analysis is carried out for a fourth-order Cascaded-Integrator/Feed-Forward (CIFF) modulator and a fourth-order CoI filter. Then, a general equation is derived that provides an approximation and upper limit of this impact for incremental converters of any order. Furthermore, the stability limits imposed by a single-bit quantizer in such converters is discussed. The proposed analysis is validated through several simulations performed at system-level using Simulink Matlab.

In this paper, we present a complete multi-standard receiver based on a variable-gain LNA and an RF subsampled Sigma-Delta ADC. The receiver includes an RF digital down-conversion mixer and a polyphase multistage multi-rate decimation filter. The receiver is measured for 3 different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79, 73 and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply.

Advanced technology is needed every day for wireless, wearable sensors/potentiostats to record real-time measurements and monitor the chemical processes and physiological signals of the human body. Most of the potentiostats present on the market work as "black boxes" without access to their internal structure and their limited information of circuitry makes it challenging to develop new measurement methods and further integration with other instruments. Despite high resolution (e.g., measure low currents with high precision and low noise) of commercial potentiostats, the potentiostats used in laboratories are heavy, non-portable, and expensive. To fill this void, we introduce KAUSTat, a wireless, wearable, open-source potentiostat. The KAUSTat device interfaces with a smartphone to generate cyclic voltammetry curves using a Bluetooth Low Energy (BLE) protocol. Experiments with buffer and hexacyanoferrate solutions were conducted to assess the efficiency of the device. The results generated by KAUSTat are in agreement with those of the commercial potentiostat "Emstat." Considering wireless and wearable features of KAUSTat, it represents a convenient portable device for on-site sensing with low-power requirements.

This paper presents the design and evaluation of two low-power and low-noise operational transconductance amplifiers (OTA) topologies for wearable applications. Current-Mirror OTA and Folded-Cascode OTA are designed using gm/ID method for optimal sizing focusing on low-power design in order to meet the specifications needed for wearable applications. Simulation results and comparative discussion are presented for the two topologies designed on a 0.5 /µm CMOS process.

The design of a fully integrated multi-standard UHF receiver front-end to be embedded in environmental data collection satellites is proposed. The circuit operates under the requirements of both SBCDA and the ARGOS 3. For that, the specifications of a multi-standard receiver front-end are firstly derived and then the implementation of a 70.4 dB voltage gain, 2.3 dB NF, 48 mW energy consumption, single-ended input and differential quadrature output receiver front-end in 130-nm CMOS standard technology is presented. The design is validated through post-layout simulation.

This work presents an analysis performance for a Wheatstone-Bridge Constant Temperature Anemometer architecture (WB-CTA) using a NTC sensor and taking into account its energy consumption, sensitivity and settling time. The best design parameters are investigated considering the trade-off between these performance requirements. The study is conducted using dynamic behavior and circuit-level models of the thermo-resistive sensor and Wheatstone bridge. Simulations results are presented and discussed.

In this paper, we present the design and implementation of an RF bandpass modulator where the loop filter is a 4th order capacitively-coupled LC filter. A design methodology using coupling capacitor and the feedback Finite Impulse Response Digital-to-Analog Converter (FIRDAC) coefficients in order to obtain the desired Noise Transfer Function (NTF) is presented. The proposed capacitively-coupled bandpass LC is implemented in a 130nm CMOS process. The fabricated chip, operating under a supply voltage of 1.2V, has a varying center frequency range of 400442MHz with a corresponding sampling frequency range of 533589MHz. A maximum Signal-to-Noise Ratio (SNR) of 50dB in a 4.5MHz bandwidth for a power consumption of 20mW was achieved. The effect of the clock jitter on the Analog-to-Digital Converter (ADC) performance is measured and presented.

This paper presents the development of a custom SRAM island-style FPGA, covering the information needed and the steps involved in hardware implementation, bitstream configuration and design alternatives to facilitate the overall implementation effort from an academic point of view. To achieve the state of the art, commercial FPGAs can employ a large team, a high time-to-market, and high non-recurring engineering costs. In contrast, by taking the challenge of building a custom FPGA with a small team of researchers, the development of custom architecture and size focuses on the proof of concept. This baseline methodology result can be a start point for the development of new technologies or circuit enhancements.

The Thermal Sigma-Delta (TΣΔ) modulator is a thermal-electric system where the resistive element performs in the thermal domain part of the ΣΔ modulator (sum and integration). In this work, we propose the modeling and we perform simulations of 1st and 2nd order TΣΔ modulators using bolometers as the thermal-electric device. This study has the purpose of achieving a complete solution of a bolometer with increased sensitivity, while providing a digital output, using only thermal sigma-delta converters, which is suitable solution to integrated transducers.

This paper proposes an architecture of a conditioning circuit for dual-modality wire-mesh sensors, applied to multiphase flow measuring. The proposed circuit topology uses an AC-based impedance measurement technique, and is able to process signals from a 4×4 wire-mesh structure, performing an I/Q demodulation for the direct extraction of fluid permittivity and conductivity values. System-level considerations are taken into account to derive the requirements for the main circuit blocks, which are aimed to be integrated on standard CMOS technology.

International audience; This paper presents a continuous-time 8-bit folding analog-to-digital converter. The clock-less architecture is composed of 8 identical stages with 1 bit/stage. The circuit is designed in a 350nm CMOS process with a supply voltage of 3.3V. Simulation results show that the 8-bit clock-less ADC can achieve a Signal-to-Noise and Distortion Ratio of 53dB. The ADC has a power consumption of 5.51mW. The proposed circuit is compared with a similar continuous-time 8-bit pipeline ADC with 1 bit/stage.

International audience; This work proposes a methodology to design linear transconductors based on three circuit topologies previously reported in literature. The design is done to be used in a synthesis tool, containing the MOS transistor model. The topologies has been analyzed using a more improved small-signal equivalent circuit of a MOS transistor to obtain a more accurate expression for the transconductance (Gm) and to extend the use for high frequencies range. A design examples in 945Mhz is given in a 130nm CMOS process.

International audience; In this paper, we present a systematic design procedure for Q-enhanced integrated LC filters, which does not require any simulations and is thus suitable for design automation. The design procedure has been described in the CAIRO+ analog design environment, containing the BSIM3v3 models of the MOS transistors. Precise estimations of the quality factor and the resonance frequency were made possible by adding the integrated inductance pi-model into the design environment. Several design examples of 2.4 GHz Q-enhanced LC filters are given in a 0.13 um CMOS process.

This work proposes an architecture of a programmable conditioning circuit for dc level adjustment and gain programming to be implemented for systems on chip. The conditioning circuit is developed using a methodology to minimize the number of passive components used for programming the gain guaranteeing the full measurement range. The circuit is designed using the switched capacitors technique with two gain stages, for a total gain varying from one to 512. It can operate in four different modes, single-ended with or without dc level adjustment, differential, and calibration. Simulation results are presented for the schematic and for the circuit extracted from the layout.