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Current filament (CF)-related double-hysteresis ${I}$ – ${V}$ behavior and holding current, ${I} _{\text {HOLD}}$ , are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. ${I} _{\text {HOLD}}$ is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. ${I} _{\text {HOLD}}$ exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that ${I} _{\text {HOLD}}$ values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. ${I} _{\text {HOLD}}$ calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD ${I}$ – ${V}$ analysis and provides a safe margin for ${I} _{\text {HOLD}}$ prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of ${I} _{\text {HOLD}}$ .

Multi-finger floating-base silicon controlled rectifiers (SCRs) of discrete technologies are investigated by transmission line pulses (TLP) with short (300ps) and long (10ns) pulse rise times (RT). Transient interferometric mapping (TIM) is applied to study the finger triggering dynamics. The measurements are correlated with TCAD simulation. It is found that for short RT the fingers trigger simultaneously which is due to the positive influence of a voltage overshoot related to delayed conductivity modulation. For long RT the fingers trigger sequentially which is accompanied by the voltage drops near the holding voltage. The time delay between the triggering of neighboring fingers is in the 3–150ns range and depends on the actual current density in fingers. The sequential finger triggering is due to lateral carrier diffusion-limited processes and the coupling via substrate currents.

During triggering of an on-board ESD protection, e.g., an SCR, its voltage may temporarily rise to a large value. This work identifies and distinguishes the two major factors that contribute to this voltage overshoot: (1) the conductivity modulation in the silicon and (2) the inductance of the metal traces. The overshoot is shown to have a major impact on the residual current into the IC during a system level discharge (ESD gun test), in particular in high-speed interfaces, such as USB3. This work presents a physics-based behavioral model which accurately describes both contributions to the voltage overshoot. The conductivity modulation model is based on the premise that the doping concentration of a region in the SCR is insufficient to conduct the trigger current. It follows that a minimum charge must be injected into the low-doped region to enable conduction of the trigger current. SCR triggering is delayed until this minimum charge has been injected. During the delay time, the SCR voltage is determined by the high ( $\sim 1~\text{k}\Omega $ ) off-resistance of the device. After triggering, the voltage is determined by the low-impedance ( $\sim 0.25~\Omega $ ) on-resistance. The net effect is a voltage overshoot. This first overshoot is followed by a second inductive voltage overshoot at the time when L.dI/dt is maximum. The paper demonstrates how the resulting model can be used to improve system level robustness for a typical USB3 interface.

We investigated the Phase Change Memory (PCM) capabilities of In-doped Sb nanowires (NWs) with diameters of (20-40) nm, which were self-assembled by Metalorganic Chemical Vapor Deposition (MOCVD) via the vapor-liquid-solid (VLS) mechanism. The PCM behavior of the NWs was proved, and it was shown to have relatively low reset power consumption (~ 400 μW) and fast switching capabilities with respect to standard Ge-Sb-Te based devices. In particular, reversible set and reset switches by voltage pulses as short as 25 ns were demonstrated. The obtained results are useful for understanding the effects of downscaling in PCM devices and for the exploration of innovative PCM architectures and materials. Keywords: Phase change memories, Nanowires, MOCVD, In-Sb, TEM, XRD

Capacitance transient spectroscopy and dc current–voltage ( I–V ) characterization are employed to analyze charging/discharging effects and transport in 200-nm-thin carbon-doped GaN layers (GaN:C) with a low ( ${N}_{\textsf {C}} = \textsf {10}^{\textsf {18}}$ cm $^{-\textsf {3}}$ ) and high ( ${N}_{\textsf {C}} = \textsf {10}^{\textsf {19}}$ or ${N}_{\textsf {C}}= \textsf {7}\times \textsf {10}^{\textsf {19}}$ cm $^{-\textsf {3}}$ ) carbon concentration ${N}_{\textsf {C}}$ . The discharging and charging events are found to be governed by transport properties of GaN:C for whole ${N}_{\textsf {C}}$ range. However, distinct temperature behavior has been found as a function of ${N}_{\textsf {C}}$ . In the samples with low ${N}_{\textsf {C}}$ , an Arrhenius-like behavior with an activation energy of 0.8 eV indicates that the hole transport in valence band (VB) is the limiting process and the carrier exchange occurs between VB and the defect level. In contrast, in samples with high ${N}_{\textsf {C}}$ , a non-Arrhenius charging/discharging behavior with exp( aT )-dependence ( ${a}$ being a constant) in a wide temperature range (150–560 K) indicates that the transport is governed by defect bands (DBs) where the carrier exchange occurs between DBs and the carbon defect level. For samples with ${N}_{\textsf {C}} \ge \textsf {10}^{\textsf {19}}$ cm $^{-\textsf {3}}$ , the large charge accumulation in GaN:C produces a large energy barrier to prevent electron injection from n-GaN to GaN:C, thus making GaN:C blocking. This is in contrast to samples with ${N}_{\textsf {C}} = \textsf {10}^{\textsf {18}}$ cm $^{-\textsf {3}}$ where the barrier is low, rendering thus the bilayer leaky. Detailed physical models for carrier capture and emission processes and carrier transport are provided for both cases. The developed knowledge is important for understanding the role of growth parameters such as ${N}_{\textsf {C}}$ and dislocation densities, as well as for reliability testing and defect analysis.

The operation of stacked MOSFET circuit for RF switch application under electrostatic discharge (ESD) conditions is studied by transmission line pulse (TLP) and transient interferometric mapping (TIM) techniques combined with circuit simulation. TLP pulses with 100–840 ns durations were applied to the device composed of 16 stacked multifinger MOSFET blocks with gate and drain resistors, fabricated in a bulk technology. ESD discharge paths related to MOSFET channel and to open-base breakdown have been identified to have dominant role in explaining the complex voltage and current waveforms. The overall circuit behavior during TLP pulses is analyzed taking into account calibrated breakdown measurements on test structures. In order to explain the heat dissipation in MOSFET blocks measured by TIM, additional discharge paths related to block-to-block coupling due to parasitic bipolar action have been modeled and discussed. Besides the analysis of the device behavior, we have also investigated peculiar optical TIM signal related to anisotropic reflectivity and phase response due to dense multifinger block structure.

Carbon impurities in GaN form both acceptors and donors. Donor-to-acceptor ratios (DARs) determine the semi-insulating behavior of carbon-doped GaN (GaN:C) layers and are still debated. Two models are discussed; both can theoretically achieve semi-insulating behavior: the dominant acceptor model (DAM, DAR

Transient interferometric mapping (TIM) and backside light emission microscopy (EMMI) are applied to study the trigger behavior and on-state spreading in discrete-technology electrostatic discharge (ESD) protection silicon controlled rectifier (SCR) test-structures without and with trigger taps. The trigger taps or device corners are clearly identified as regions where the avalanche breakdown and SCR action are initiated. The regions relevant to the holding current can be identified by EMMI. In SCR mode the injection regions from the npn and pnp emitters have been localized by TIM. The on-state spreading (OSS) speed of 1–4 μm/ns obtained from TIM is consistent with the results of 3D TCAD simulations. The driving force of the OSS is discussed on the basis of TCAD results.

Successive voltage drops near the holding voltage associated with sequential finger triggering (SFT) are observed in multi-finger floating-base SCRs. A time delay between the triggering of neighboring fingers is in the 3–150ns range and it is observed only for long pulse rise times (10ns). TCAD simulation explains that SFT is due to lateral carrier diffusion-limited processes.

In this work, current multiplication at high electric field in epitaxial boron-doped diamond with high acceptor concentration is analyzed, including self-heating effect and impurity impact ionization. Quasi-static current-voltage (I-V) characteristics were measured using a transmission-line pulse setup with 100 ns pulse duration on samples with two Ohmic titanium/gold electrodes. Unambiguous exponential and super-exponential behaviors are observed in the I-V curves along with, in some cases, negative differential resistance. The self-heating effect is analyzed using transient interferometric mapping of the thermal energy distribution between electrodes with an ns time scale. Measured I-V characteristics are modelled by finite element method and by considering boron acceptor ionization due to self-heating effect and impurity impact ionization. Simulated I-V characteristics, in particular the appearance of the negative differential resistance region attributed to self-heating, are in good agreement with experimental data.

This paper reports an analysis of the degradation mechanisms of GaN-based normally-off transistors submitted to off-state stress, forward-gate operation and electrostatic discharges. The analysis was carried out on transistors with p-type gate, rated for 600 V operation, developed within the European Project HIPOSWITCH. DC measurements, thermal analysis by transient interferometric mapping (TIM), and transmission line pulse (TLP) were used in combination to achieve a complete description of the degradation and failure processes. The results of this investigation indicate that: (i) the analyzed devices have a breakdown voltage (measured at 1 mA/mm) higher than 600 V; in off-state, drain current originates from gate–drain leakage for drain voltages (VDS) smaller than 500 V, and from vertical leakage through the conductive substrate for higher drain bias. (ii) step-stress experiments carried out in off-state conditions may induce instabilities in both drain–source conduction and gate leakage. Failure consists in the shortening of the gate junction, and occurs at VDS higher than 600 V. (iii) in forward bias, the p-type gate is stable up to 7 V; for higher gate voltages, a time-dependent degradation is detected, due to the high electric field across the AlGaN barrier; (iv) TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region, thus indicating that these regions may behave as weak spots under high bias operation. Cumulative device degradation under such repeating pulses has also been revealed. (v) TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions. The results described within this paper provide relevant information on the reliability issues of state-of-the-art normally-off HEMTs with p-type gate.

The dynamic voltage overshoot of an ESD protection during triggering is determined by conductivity modulation in the silicon and inductive overshoot in the metal traces. The paper describes how to separate the two contributions and how to model these phenomena. It shows how to use this result to boost system protection for a typical USB3 interface beyond 15kV.