Search

In recent years, field-programmable gate array (FPGA) devices have attracted a lot of attentions due to the increasing performance they provide thanks to technology scaling, besides their high flexibility through in-field reprogramming and/or partial reconfiguration capability. However, when such devices are to be deployed in safety- and mission-critical applications such as avionic and space applications, it is mandatory to verify the reliability of the device in the target environment where radiation effect is considered as one of the major sources of faults in the system. For static random access memory (SRAM)-based FPGA devices, the SRAM cells holding the configuration data for the circuit implemented on the devices are highly susceptible against single-event upset (SEU) induced by charged particle striking the device and one single SEU in the configuration memory may corrupt the implemented circuit design causing system misbehavior. In this paper, we present the radiation test data on Xilinx Kintex-7 SRAM-based FPGA using ultrahigh energy heavy-ion test beam for the first time available to third-party radiation test in CERN. [ABSTRACT FROM AUTHOR]

General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches such as Duplication With Comparison, Triple Modular Redundancy and Algorithm Based Fault Tolerance. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation. [ABSTRACT FROM AUTHOR]

Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation. [ABSTRACT FROM PUBLISHER]

A methodology is proposed to emulate and assess the single event effect in configuration memory on 16 nm Ultrascale+ MPSoC. The solution depends on fault injection and fault tree analysis. Three image processing applications, including histogram computation, image stretch and sobel edge detection, are used as the benchmarks. The results demonstrate 38.1% to 40.5% system errors cannot be recovered, although the SEM sub-system is adopted to recover the corresponding upset in the configuration memory. • A methodology is proposed to emulate and assess single event effect in configuration memory on 16 nm Ultrascale+ MPSoC. • Fault injection and event tree analysis are employed in the method. • 38.1% to 40.5% system errors cannot be recovered although the SEM sub-system is applied. [ABSTRACT FROM AUTHOR]

General Purpose Graphics Processing Units (GPGPUs) have been extensively used in the last decade as accelerators in high demanding applications, such as multimedia processing and high-performance computing. Nowadays, these devices are becoming popular even in safety-critical applications, such as in autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of transient faults, such as those produced by radiation effects. Among those effects, Single Event Upsets (SEUs), which are the focus of this paper, can cause application misbehaviors, which may lead to catastrophic consequences. In this work, we first describe how we extended the capabilities of an open-source VHDL GPGPU model (FlexGrip) and developed a new version named FlexGripPlus to study and analyze the effects of SEUs in a GPGPU in a much more detailed manner. We also performed extensive fault injection campaigns using FlexGripPlus, which allowed identifying the most critical effects within the GPGPU architecture. We finally focused on the scheduler controller since it represents a module that is specific to the GPGPU architecture and showed that it has different levels of SEU sensibility depending on the affected location. Moreover, the results of additional analyses varying the number of parallel execution units in the system are presented, demonstrating the correlation between the number of execution units in a GPGPU and the system reliability. The paper • describes a new model of a GPGPU (named FlexGripPlus) derived from FlexGrip and compliant with the NVIDIA G80 GPUs. • highlights a multi-platform fault injection environment aimed at evaluating the sensibility to transient faults • reports extensive results showing that different modules behave rather differently and show different sensitivity to SEUs • evaluates the fault sensibility of a GPGPU, analyzing the impact of different workloads, configurations and coding styles. [ABSTRACT FROM AUTHOR]

The 28 nm system-on-chip (SoC) was irradiated by 12 MeV electron at the China Institute of Atomic Energy (CIAE) for the first time. Soft errors in the on-chip memory (OCM), D-Cache, Register and BRAM blocks were investigated. The obtained device cross sections are almost in the range of 10−13 cm2 to 10−11 cm2 for the blocks. The results demonstrate that electron fluence per pulse and the corresponding prompt dose rates have no influence on the soft errors in 28 nm SoC. The discrepancy was analyzed between proton and electron inducing soft errors in D-Cache and BRAM blocks, too. The secondary electron is considered as the dominant reason for soft errors caused by 12 MeV electron in 28 nm SoC. [ABSTRACT FROM AUTHOR]

With the high flexibility, increasing computing power and lower power consumption, FPGA devices have gained a lot interest in space and avionic applications. Among different types of FPGA devices, Flash-based FPGA is becoming increasingly attractive since their configuration memory is almost immune to Single Event Upset (SEU) induced by energetic particles. However, when applied in such applications, especially long term space missions, the FPGA devices are subject to cumulative ionizing damage, as known as Total Ionizing Dose (TID). The TID may affect the FPGA causing performance degradation and possible eventual permanent damage leading to functional failure. In this paper, we propose a new workflow for analyzing the TID effect on Flash-based FPGA considering the different distributions of TID over the chip and the different impact factors when the configurable logic is programmed to implement different logics in the design. The experimental results show the feasibility of such workflow to be used as assessment tool at early stage of design development. [ABSTRACT FROM AUTHOR]

The robust guaranteed cost consensus problem of high‐order discrete‐time linear multi‐agent systems (MASs) with parameter uncertainties and time‐varying delays is studied, and a linear consensus protocol of it is designed. Norm‐bounded uncertainties and polytopic uncertainties are considered. First, the idea of robust guaranteed cost control is introduced into consensus problems for the MASs, where a cost function is defined based on state errors among neighbouring agents and control inputs of all the agents. Second, by constructing suitable Lyapunov functions and using the stability theory of discrete‐time linear systems, two sufficient linear matrix inequality conditions are derived to insure that high‐order discrete‐time linear MASs with the two types of parameter uncertainties and time‐varying delays reach robust guaranteed cost consensus. At the same time, two upper bounds of the guaranteed cost function are also given. Third, convergence results are given as final consensus values of the MASs with parameter uncertainties and time‐varying delays. Finally, two numerical comparisons are given to illustrate the correctness and availability of the theoretical results. [ABSTRACT FROM AUTHOR]