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With the rising of Hybrid Bonding (HB) as an interesting solution for fine-pitch 3D integration, the influence of process induced variations on performances is a demanding and crucial task. A 3D stacked test vehicle with hybrid bonding pitch ranging from 6.8 down to $1.44\ \mu \mathrm{m}$ was processed and analyzed. A deep analysis on the influence of process variations is conducted and correlated to electrical measurements thanks to a dedicated simulation methodology. This allows a better understating of the process variation parameters that affects electrical resistance and capacitance along with their relative importance which is essential for optimization. The common parameter affecting both capacitance and electrical resistance is Wafer-to-Wafer overlay between top and bottom wafers arising the need for high accuracy in bonding alignment. The quality of the hybrid bonding interface is discussed thanks to the simulation model, before and after robustness tests depending on hybrid bonding pitch, leading to an estimation of contact resistivity around $2. 10^{-10}\Omega.cm^{2}$ for the $1.44\ \mu \mathrm{m}$ -pitch structure.

Cu/oxide Hybrid Bonding (HB) technology is currently the ultimate fine pitch 3D interconnect solution to reach submicron pitches. It's an attractive technique to address the needs of several applications such as smart imagers, high-performance computing and memory-on-logic folding. But test and characterization of such fine-grained 3D interconnect is still an open issue; Cu-Cu interconnects are prone to many structural defects due to fabrication process, such as misalignment, which needs to be thoroughly tested to ensure the performance of 3D-ICs. In this work, we focus on testing and characterizing, on-wafer, misalignment defect induced at the bonding step. A misalignment test structure was fabricated in a Wafer-to-Wafer (W2W) assembly configuration with a pitch of 3.42µm and 1.44µm using a very small measurement step for an accurate misalignment measurement (respectively 45nm and 22nm). Electrical tests have been performed using five multi-pitch wafers with 71 measurements points per wafer. The experimental results show that the results of the proposed test structure are aligned with conventional overlay measurements. Finally, the impact of misalignment defect on resistance and capacitance parameters was demonstrated.

This paper presents the description of direct hybrid bonding technology for the fabrication of vertical interconnects thanks to wafer-to-wafer bonding. Process robustness is analyzed through morphological and electrical results. The electrical characterizations are discussed versus hybrid bonding pad dimensions and pitches. Electromigration study is carried out on different test vehicles with hybrid bonding interconnect dimensions below 5 μm. Experimental tests provide the parameters for lifetime extrapolation and show that the hybrid bonding module is immune to electromigration failures. Finally perspectives and key challenges for 3D interconnects scalability are given.

Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A study of the influence of hybrid bonding pitch shrinkage on a 3D stacked backside illuminated CMOS image sensor was performed from a process, device performance and robustness perspectives, from $8.8\ \mu\mathrm{m}$ down to $1.44\ \mu \mathrm{m}$ bonding pitches. As a result no defect related to smaller bonding pads was evidenced neither by thermal cycling nor by electromigration, thus validating fine-pitch hybrid bonding robustness and introduction for next generation image sensors.

Among the numerous ways to address 3D stacking of integrated circuits, a promising method is Cu/SiO 2 hybrid bonding, which is the simultaneous metallic bonding of the interconnection pads and direct bonding of the dielectric surfaces. Prior to bonding, a chemical-mechanical polishing step is necessary, resulting in copper pads being slightly overpolished compared to the surrounding oxide regions (dishing effect). This effect, if too important, can prevent bonding and thereby lead to electrical connection failure between top and bottom parts. In order to better understand the involved phenomena and to perform virtual prototyping, a 3D finite element model for the thermal annealing of Cu/SiO 2 hybrid bonded pads is presented, taking into account the dishing effect. In this work, the contributions to bonding of thermoelastic deformation and cohesive interactions are investigated, and the impact of pad shape on Cu-Cu interface closure during thermal annealing studied. In addition, a parametric study is conducted, in order to identify the most efficient design and process parameters to improve bonding quality.

This paper presents, for the first time, an electromigration study for a hybrid bonding-based integration for advanced image sensor applications. This work demonstrates that the hybrid bonding module has no impact on the electromigration resistance of the present integration. The weakest link is always the BEoL level. There is no hybrid bonding-related failure.

3D Stacked Image sensor is the stacking of a Back-Side Illuminated (BSI) CMOS Image Sensor on a logic die. It enables compact size, higher performances and additional functionalities compared to standard BSI sensors. The highest footprint reduction is obtained with 3D hybrid bonding with metal interconnects between top and bottom tiers. Hybrid bonding process with oxide / copper direct bonding allows the highest scalability of interconnect pitch. In this study we present the morphological and electrical characterizations of a test vehicle. The hybrid bonding of wafers from two different technology nodes is performed using a dual damascene integration for the hybrid bonding level. The main parameters to assess the bonding interface quality are analyzed such as the influence of the pad design, the impact of reworkability and wafer -- to-wafer overlays. The process robustness is studied through reliability tests and electromigration measurements.

Sub 200 nm wafer-to-wafer (w2w) overlay accuracy on the entire 300 mm wafer was successfully demonstrated via wafer level Cu/SiO2 hybrid bonding. Cu bonding pads relevant for back-side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS) were used for the experiment. Further, a crucial component to improve the overlay accuracy, namely the overlay model which identifies systematic alignment errors, was described.

From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple high-k/metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well suited for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk 45 nm technology in terms of variability and noise. A 0.499 μm2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1 V.

By introducing high-K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35 nm CMOS devices that exhibit high-performance drive currents (2230/1000 muA/ mum for N/ P at Vd = 1.2 V), low off-state currents (3/5 nA/mum), and excellent subthreshold characteristics. When benchmarked with other published multigate data, the results presented in this paper are proved to be among the best and underline the potential of planar self-aligned GAA devices for the 32 nm technology and below. In particular, it is demonstrated that an optimized supply voltage can bring a significant improvement in circuit time delay and power when using GAA devices.

To face with the continuous integrated circuit densification, passive components size has to be reduced, particularly for RF and analog applications where lots of them are needed. A Metal-Insulator-Metal (MIM) capacitor is integrated with a high developed area architecture to increase the capacitance density and limit encumbrance. The combination of this architecture with Ta"2O"5 dielectric with a permittivity of 25 allows capacitance densities of more than 15fF/@mm^2. As metal insulator interface is critical, two stacks TiN/Ta"2O"5/TiN and TiN/Ta"2O"5/Cu are integrated among copper interconnects, evaluated and compared.

Tantalum oxide (Ta 2 O 5 ) is widely used for MIM (Metal-Insulator-Metal) capacitor owing of its high dielectric constant. This work examines current–voltage and capacitance–voltage characteristics in the 5 K–300 K temperature range. Working at low temperature was chosen in order to freeze trapping mechanisms of the MIM capacitor. The curvature of C – V characteristics radically changes from 5 K to 300 K. The capacitance variation under voltage at 50 K and below can be investigated using the Langevin theory. From this model the permanent dipole moment and the number of dipoles have been extracted. From Poole–Frenkel identification curves, activation energy around 0.20 eV and a dielectric constant of 26 were found for positive polarisation. However, conduction mechanisms cannot be reduced to strick Poole–Frenkel modelling.

We present here our latest results on chips-to-wafer 3D structures obtained with the self-assembly technology adapted on copper/oxide patterned surfaces. Technological integration, bonding quality and alignment accuracy are presented and the electrical contact of the interconnection is evaluated. High speed high alignment accuracy chip-to-wafer hybridation technique is mandatory for 3D technology. Chip-to-wafer self-assembly processes coupled to direct bonding hybridization is on the merge to breakthrough this issue. In a previous work [1], we demonstrated submicronic alignment accuracy and a 90% self-assembly process yield with this technique. In this paper, we discuss on interconnect electrical characterization of self-assembled chips compared to chips assembled with conventional Pick and Place method. Interface resistance is evaluated on daisy chain and Kelvin structures. The quantification of the alignment is measured thanks to vernier and is in the range of a few hundred nanometers. The liquid drop impact on assembled structure, considering the different aspects (bonding quality, Cu-chemical oxidation, mechanical chip level bow and electrical resistance) is discussed.

3D technologies need a high speed high alignment accuracy chip-to-wafer hybridation technique. This paper will focus on chip-to-wafer self assembly processes coupled with direct bonding hybridation. Submicronic alignment accuracy and a 90 per cent self-assembly process yield are obtained. The self-assembly process yield is analyzed in term of alignment accuracy and direct bonding quality. The impact of the chip's surface state (hydrophilic, hydrophobic, and mixed) on fluid containment efficiency and self-assembly process yield will be discussed. Topological containment (canthotaxis effect) is also evaluated with regards to structures height. Finally, the alignment yield as a function of deposition parameters will be described.

For WLP and 3D integration, wafers are processed through several steps which generally include bounding and thinning processes. Those processes are generally realized by the use of carriers typically glass or Silicon substrates. In this paper, we present results about thickness measurements using optical techniques namely Infra-Red interferometer and white-light spectrometer on various stacked structures. These non contact optical techniques are demonstrated to be helpful methods for the in-line monitoring.

This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide u ltra t hin b ody and b uried oxide (UTB 2 ) devices with improved drive current I on for a given designed footprint W design when scaling the device width . We compare the fabrication and electrical behavior between 〈1 1 0〉 channel, i.e. 0°-rotated wafer, and 〈1 0 0〉 channel, i.e. 45°-rotated wafer, for the same (1 0 0) surface orientation.

This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint Wdesign. We compare the fabrication between channel, i.e. non-rotated wafer, and channel, i.e. 45deg-rotated wafer, for the same (100) surface orientation.

Atomic layer deposition (ALD) recently emerged as an enabling technology for microelectronic device fabrication. This technique provides the unique capability to deposit ultra thin films with the thickness control, uniformity, step coverage, and electrical/mechanical properties required to support device manufacturing at the 45 nm node and beyond. This paper will review the fundamentals of ALD processing and describe the equipment used. Applications of ALD in the fabrication of advanced gate stacks, on-chip capacitors, and thin film magnetic heads are presented.

A new simple 3D Damascene architecture requiring only one additional mask is introduced for high-density MIM capacitors. TiN/Ta2O5/TiN stack deposited by PEALD has been integrated between Cu interconnect levels to maximize quality factor Q, reaching up to 17 fF/μm2 capacitance. High-performance, breakdown voltages over 15 V and good linearity, C1 = 76 ppm/V and C2 = 63 ppm/V2 at 100 kHz, make this capacitor an unique solution for analog and RF applications embedded in Cu BEOL.

This paper deals with the realization of new high performances metal-insulator-metal (MIM) capacitors. Using PEALD deposited HfO2, ZrO2, A12O3 and their combination with Ta2O5, MIM stacks have been realized. By controlling high-κ deposition characteristics and dielectric stack architecture, state of the art electrical results for high performances analog design (weak non- linearity and sustaining high operating bias) are obtained. The use of 3D architecture allows combining such characteristics with very high capacitance density. A first realization with Ta2O5 leads to 30fF/mum2 and demonstrates the interest of such an approach for next generation high performances MIM capacitors.

The need for increased MIM capacitance density has led to the introduction of new high-k dielectric materials into both CMOS and BiCMOS technologies. These materials, Ta/sub 2/O/sub 5/ and Al/sub 2/O/sub 3/, exhibit several non-idealities which require more careful study than more conventional SiO/sub 2/ and SiN dielectrics. In particular, the evolution and physical mechanisms for C versus V non linearity as a function of both frequency and temperature are reported, as well as the high temperature capacitance hysteresis and capacitance linearity variations over time. The characterization and understanding of these non-idealities is required to guarantee their acceptable performance for analog IC MIM applications.