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A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. [ABSTRACT FROM AUTHOR]

Copyright of Safety & EMC (1005-9776) is the property of China Electronics Standardization Institute and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.

The FY-3E satellite plasma analyzer marks China's first detection of the characteristics, occurrence, and development of the typical plasma environment in the dawn–dusk orbit space. It provides data source support for operational space weather alerts and forecasts, helps ensure the in-orbit safety of the satellite, and accumulates space environment detection data for space environment modeling and space physics research. This paper gives a detailed introduction to the detection technology adopted by the FY-3E satellite plasma analyzer. We calibrated its performance through a calibration experiment and then analyzed and compared it with similar instruments in China. It is indicated that the instrument is capable of measuring an ion energy spectrum of 24 eV~32 keV and an electron energy spectrum of 23.7 eV~31.6 keV, its field of view reaches 180° × 90°, and the inversed measurement range of spacecraft absolute potential is better than −30 kV~+30 kV. All these contribute to a notably improved technology for plasma and satellite potential detection of China's LEO satellites. [ABSTRACT FROM AUTHOR]

In the process of TFT manufacturing, the display device IGZO‐ TFT is more likely to produce electrostatic discharge due to the complexity of the process, and the performance of the device will be reduced due to the destruction of the device. Based on the process steps and mechanism analysis of ESD occurrence, the method to improve static electricity is applied for the 95‐inch 8K OLED display without ESD mura. [ABSTRACT FROM AUTHOR]

To design SCR devices that can meet the requirements of different electrostatic discharge (ESD) design windows, a method is proposed to improve the holding current of SCR devices for ESD protection. This method is based on the device simulation software MEDICI. By simulating and analyzing the current flow direction, carrier distribution, and conductivity modulation process of SCR devices under ESD operating conditions, the holding current of SCR devices was optimized from three aspects: device size, doping concentration, and current path. The simulation results demonstrate that the holding current of the optimized SCR device has increased by 10 times. This simulation optimization method can improve students' device simulation ability and provide them with a more intuitive and comprehensive understanding of the optimization design process of microelectronic devices. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Test & Measurement Technology is the property of Publishing Center of North University of China and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, using calibrated 2-D simulations we have reported a new gate grounded trench impact ionization MOS (GGTIMOS) electrostatic discharge (ESD) protection device for sub-2V operating voltage applications. The proposed GGTIMOS ESD device exhibits ~3x, and ~1.75x reduction in the trigger voltage in comparison to the traditional GGIMOS, and GGNMOS, respectively. The proposed GGTIMOS ESD device also exhibits a hold voltage of ~2.2 V, which is ~2x higher than the recently published $\pi $ -SCR ESD device, hence, the proposed GGTIMOS is a suitable ESD device for the sub-2V operating voltage applications. Moreover, for the 2 kV human body model (HBM) the proposed GGTIMOS ESD device requires ~28% less device width than its counterpart GGIMOS ESD device, which makes it more area efficient. In addition, through 2 kV HBM simulation, we have shown that the GGTIMOS ESD device eliminates ESD stress $\sim 1~\mu \text{s}$ and the maximum temperature reached during the event is approximately 750 K which is well within the failure limits. Therefore, the results demonstrated in this paper can pave the way for future ESD design for the technology nodes where the maximum voltage handling capacity of the input/output (I/O) driver is in the range of 1.2 V to 1.8 V.

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- $\mu \text{m}$ CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Electrostatic discharge (ESD) events are causing an increasing amount of damage in advanced integrated circuits (ICs). Among the onchip ESD protection devices, the silicon controlled rectifier (SCR) is the most robust. We have proposed a new SCR with an embedded n-type metal-oxide-semiconductor field-effect transistor (nMOSFET). By properly adjusting the gate work function of the nMOSFET, the SCR obtains a low trigger voltage of 1.5 V and a low leakage current of 7.6 x 10-10 A. The overshoot voltage under a fast ESD event is also reduced owing to the strong conduction of the nMOSFET. By numerical simulation, we evaluate the impact of the temperature, noise, and stress waveform on the ESD performance. The results are discussed and detailed physical insights are given. [ABSTRACT FROM AUTHOR]

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications. [ABSTRACT FROM AUTHOR]

The FY-3E satellite plasma analyzer marks China’s first detection of the characteristics, occurrence, and development of the typical plasma environment in the dawn–dusk orbit space. It provides data source support for operational space weather alerts and forecasts, helps ensure the in-orbit safety of the satellite, and accumulates space environment detection data for space environment modeling and space physics research. This paper gives a detailed introduction to the detection technology adopted by the FY-3E satellite plasma analyzer. We calibrated its performance through a calibration experiment and then analyzed and compared it with similar instruments in China. It is indicated that the instrument is capable of measuring an ion energy spectrum of 24 eV~32 keV and an electron energy spectrum of 23.7 eV~31.6 keV, its field of view reaches 180° × 90°, and the inversed measurement range of spacecraft absolute potential is better than −30 kV~+30 kV. All these contribute to a notably improved technology for plasma and satellite potential detection of China’s LEO satellites.

In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid trigger mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed power clamp circuit is capable of achieving $\mu \text{s}$ -level transient response time with RC time constant of only 10 ns, thus greatly improving area efficiency. Compared to traditional transient circuit with same response time, the proposed one achieves a trigger circuit (TC) area reduction of over 90%. The proposed circuit achieves strong false-trigger immunity under fast power-on conditions. In addition, the circuit also has low standby leakage current of less than 10 nA at different BigFET widths. To verify the proposed circuit, the simulation and test results are analyzed in detail for this paper.

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

In this paper, a novel all-high- K metal gate (HKMG)-bounded silicon-controlled rectifier (AHBSCR) is proposed for advanced electrostatic discharge (ESD) protection in FinFET processes. Depart from its prior arts, in AHBSCR, both the main SCR path and the triggering diode path are placed along the Fin direction, and all active areas are bounded by HKMG, thus expressing superior conduction capability under various ESD stresses and a more compact silicon footprint. Experimental results show that the proposed AHBSCR owns a suitable snapback window of 1.1 Vâ€"1.6 V, a fast turn-on speed of only 400 ps, an extreme low leakage current of less than 100 pA@-1 V as well as a figure of merit of 24.3 mA fFâˆ'1, indicating it is competent to replace the conventional FinFET diodes in rail-based ESD network to further improve the efficiency of ESD protection. [ABSTRACT FROM AUTHOR]

System-efficient electrostatic discharge (ESD) design (SEED) models of a diode and transient voltage suppressor (TVS) were developed to study their transient response in a high-speed input/output interface. Previously reported SEED models were improved to strengthen their convergence stability and facilitate accurate predictions over a wide range of conditions. These improvements were required to accurately capture the race conditions between the TVS and on-chip diode, where the diode's turn on may prevent turn on of the TVS. Simulations and measurements were performed to demonstrate the impact of the ESD pulse's rise time on race conditions. During a race, results showed the worst-case quasi-static diode current could be twice as high for long rise-time pulses than for short rise-times where the TVS does not turn on, and on-chip diode current may be larger at low test voltages than at high test voltages where the TVS does turn on. Adding a small passive impedance between the external TVS and the on-chip diode helps the TVS turn on and reduce the current through the on-chip diode by more than 50%. Similarly, lengthening the trace between the TVS and diode could reduce on-chip diode current by up to a factor of two. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) failure results in about 35% of integrated circuit (IC) field return and causes several billion-dollar losses to the semiconductor industry per year. Most modern ICs include on-chip ESD protection circuitry which comes at the cost of I/O performance. Static charge accumulation during transport and handling may exceed the limits of this ESD protection and cause damage to the ICs. Modern advanced packaging technologies are not amenable to rework if one or more components are ESD compromised. An on-chip ESD sensor is useful in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging technology. Two approaches for on-chip ESD sensor that can be employed on any die, following the ground rules within that technology are presented. Both approaches are designed, simulated, fabricated, and experimentally characterized using GlobalFoundries 22-nm fully depleted silicon-on-insulator (FDSOI) technology. While determining ESD voltage using sensors, we encounter two events that are naturally random. First, ESD is a random event with some probability distribution function (PDF) with respect to voltage. In addition, oxide breakdown within the ESD sensors is also random with a Weibull distribution. A Bayesian method is developed for the estimation of ESD voltage PDF using sensors. Experimental testing of the sensors using an ESD gun and ESD voltage estimation from the number of sensors that broke down is presented. The estimated ESD voltage closely matches the ESD voltage that the dies were subjected to during experimental verification. [ABSTRACT FROM AUTHOR]

In this paper, a series of Low Voltage Triggering Silicon-Controlled Rectifier (LVTSCR)-based devices were designed and fabricated in a 0.25 μm Bipolar-CMOS-DMOS (BCD) process. Two distinct methods, the integration of additional doping regions and current paths, are investigated to improve the proposed devices' holding voltage (V h). Two-dimensional device simulation is employed to elucidate the working mechanism of these ESD protection devices, complemented by the introduction of a transmission line pulse (TLP) measuring system to assess their ESD protection capabilities. Comparative analysis of TLP results reveals that both methods contribute significantly to the augmentation of holding voltage in LVTSCR ESD protection devices. The refined structure, LVTSCR_BN, with two additional current paths, surface and buried, demonstrated a noticeable increment in holding voltage. With its holding voltage of 7.619 V and trigger voltage of 10.61 V, LVTSCR_BN is proved suitable for the ESD protection of circuits operating at the voltage of 5 V. [ABSTRACT FROM AUTHOR]

In this article, a novel low trigger and fast turn on electrostatic discharge (ESD) protection device, called deep N-well diode-triggered silicon-controlled-rectifier (DNWTSCR), is proposed for 1.8 V I/O protection applications in the advanced 40-nm CMOS technology. By incorporating a deep N-well parasitic diode path into the conventional DTSCR, the triggering diodes-string gets prolonged and possesses higher impedance without area penalty. Owing to this, more current will branch to the inherent SCR during the operation, and consequently the DNWTSCR will present improved turn-on characteristics. The ESD characteristics of the proposed DNWTSCR and the conventional DTSCR were evaluated by Transmission Line Pulse (TLP) and Very Fast TLP (VFTLP). As results, the DNWTSCR presents a low trigger voltage of 3.4 V and an extremely fast turn-on time of 0.85 ns, which are 41 % and 51 % lower than the conventional DTSCR, respectively. Moreover, the TCAD simulation results agree well with the transmission line pulse testing results, further confirming that the proposed DNWTSCR can be widely used as an effective ESD protection device for high-speed ICs. • The proposed DNWTSCR is a novel low trigger and fast turn on electrostatic discharge protection device for 1.8 V I/O protection applications. • By incorporating a deep N-well parasitic diode path into the conventional DTSCR, the triggering diodes-string gets prolonged and possesses higher impedance without area penalty. • The DNWTSCR presents a low trigger voltage of 3.4 V and an extremely fast turn-on time of 0.85 ns. • The DNWTSCR is suitable for ESD protection of high-speed ICs, without the limitation of additional layout area and technology process. [ABSTRACT FROM AUTHOR]

In this paper, a novel silicon-controlled rectifier (SCR) electrostatic discharge (ESD) protection device, called low voltage triggered SCR (LVTSCR) triggered SCR (LVTSCRTSCR), is proposed for 3.3 V I/O protection applications in 0.18 μm CMOS technology. One side of the device is the traditional LVTSCR structure, and other side is the traditional SCR structure. The two structures are connected by a floating P+ diffusion layer. The working principle of LVTSCRTSCR was verified by the TCAD simulation results and TLP test results. The test results show that the triggering voltage of LVTSCRTSCR is determined by the traditional LVTSCR, with a value of 9.850 V. The holding voltage of the device can be effectively improved by increasing the size of the floating diffusion layer D4. When D4 = 6 μm, the holding voltage can be 4.491 V, suitable for 3.3 V I/O. [ABSTRACT FROM AUTHOR]

This article introduces a silicon carbide (SiC)-based high-voltage silicon-controlled rectifier (HV-SCR) for on-chip electrostatic discharge (ESD) protection. The SiC HV-SCR is formed by implanting a $\text{p}^{+}$ region into the n-well of SiC laterally diffused metal-oxide semiconductor (LDMOS) structures. Both LDMOS and HV-SCR structures were characterized using a transmission line pulse (TLP) system to investigate their ESD behaviors. The TLP measurement results show that the trigger voltage (${V}_{\text {t1}}$) of the SiC HV-SCR is $\sim 230$ V and has minor dependence on the drift length. The ${V}_{\text {t1}}$ value of the SiC LDMOS decreases from 224 to 202 V when its drift length decreases from 6 to 4 $\mu \text{m}$. TLP measurements with 500- $\Omega $ impedance were conducted to obtain an accurate holding voltage (${V}_{\text {h}}$) and failure current (${I}_{\text {t2}}$) of HV-SCR and LDMOS. Relatively high ${I}_{\text {t2}}$ (i.e., 33 mA/ $\mu \text{m}$) of the HV-SCR structure was observed, which is much stronger than the LDMOS structure (i.e., 0.2 mA/ $\mu \text{m}$). The ${V}_{\text {t1}}$ and ${V}_{\text {h}}$ values of HV-SCR were also investigated with varying gate bias voltages. Moreover, technology computer-aided design (TCAD) simulations of the SiC HV-SCR and LDMOS were carried out to further understand their ESD behaviors. [ABSTRACT FROM AUTHOR]

Direct bidirectional current discharge paths between input/output (I/O) and ground (GND) are imperative to achieve robust charged device model (CDM) protection for very stringent design window in advanced low-voltage (LV) processes. In this brief, a compact and fast response dual-directional silicon-controlled rectifier (CFR-DDSCR) has been proposed. Using P-electrostatic discharge (ESD) implantation layer to implement each diode-triggered silicon-controlled rectifier (SCR) within only one n-well, the inherent defect of the prior art (i.e., the cumbersome p-well/n-well triggering diode) is eliminated, ensuring the low resistance of auxiliary triggering path and the compactness of silicon footprint. Moreover, by shielding all internal shallow trench isolation (STIs) with floating high- ${k}$ metal gates (HKMGs), an all-gate-bounded SCR structure is realized, and all triggering diodes evolve into gated diodes with compact current paths, thus improving the CDM protection capability greatly. Experimental results indicate that the CFR-DDSCR, with a design window suitable for 1.2 V-CMOS technologies, acquires a higher effective CDM robustness (73% improved), a faster turn-on speed (64% improved), and a more compact layout (31% shrunk) compared with its conventional counterpart, which is promising for the advanced LV CDM protection. [ABSTRACT FROM AUTHOR]

In electric power and electronic systems, localized breakdown of air in the form of corona, partial discharge (PD), and electrostatic discharge (ESD) occurs frequently. These processes are known to be sources of electromagnetic fields. Corona on overhead line conductors produces electromagnetic noise over a wide frequency range leading to electromagnetic interference. The magnetic field due to PD can be employed to detect and possibly locate PD inside the apparatus. The fields due to ESD assume importance in designing suitable protection systems. Therefore, there is a need to relate the electromagnetic field produced by the discharge phenomenon to the physical ionization process, which constitutes them. The basic mechanism behind naturally initiated electrical discharges is the electron avalanche and an expression for its total electric field has been derived and validated in the literature. The next step in this direction is to obtain the magnetic field produced by it. An expression for the complete magnetic field, i.e., both near- and far-field components, is derived starting from Lienard–Wiechert potentials. The derived expression is validated with the numerical solution of Maxwell's equation. A simplified procedure to extend avalanche results for practical discharges is demonstrated. Close agreement is obtained between the estimated results and measured results reported in the literature. [ABSTRACT FROM AUTHOR]

In this letter, a broadband millimeter-wave (mm-wave) electrostatic discharge (ESD) protection structure is proposed and verified in a 40-nm CMOS process. The main ESD protection device is a diode-triggered silicon-controlled rectifier (DTSCR) with a tunable trigger voltage. Two weakly-coupled inductors are embedded to increase the operating bandwidth. Both theoretical analysis and simulation results show that a low coupling factor is necessary to obtain the wideband characteristic. The proposed design exhibits good ESD protection performance (HBM robustness >1.875 kV), fast turn-on speed, wideband reflectionless characteristic (${S}_{{11}} < -15$ dB within 33.6-50GHz), tunable trigger voltage and low leakage current. Therefore, this new device is suitable for ESD protection of input/output (I/O) pads in mm-wave-communication applications. [ABSTRACT FROM AUTHOR]

In this paper, we present N-channel laterally diffused MOSFET (nLDMOS) devices for electrostatic discharge (ESD) contact-mode sensors in ultrahigh voltage (UHV) applications. These circular UHV nLDMOS devices have concentric circles of poly-layer 2 (Poly2) with different potential configurations and a discrete high-voltage P-well (HVPW) in the drift region. The Poly2 on the drift region is made of polysilicon to reduce the peak electric field in the drift region, thereby reducing the on-resistance. When the Poly2 was connected to the positive VDD potential, the trigger voltage of the device decreased due to the change in the interface electric field in the drift region; thus, this device more easily triggered conduction than the Poly2 grounded type. We used five radial methods to insert the HVPW into the drift region and evenly distributed it into two, four, eight, 16, and 32 equal partitions. When the Poly2 was grounded and the HVPW layer of the drift region was divided into 32 partitions, it had the highest secondary breakdown current of 3.56 A. This is because the more uniform the distribution of the superjunction (SJ), the higher the ability of the component to discharge the ESD current. Therefore, changing the potential of Poly2 changes the electric field distribution and affects the trigger voltage. Adding an HVPW SJ structure in the drift region will increase the on-resistance, thus improving the discharging current capability. [ABSTRACT FROM AUTHOR]

In this paper, electrostatic discharge (ESD) reliability sensing components for use in ultrahigh- to low-voltage environments were fabricated via a Taiwan Semiconductor Manufacturing Company (TSMC) 0.5 μm ultrahigh voltage (UHV) bipolar-CMOS-DMOS (BCD) process. To understand the trend of the capability of different voltage components under ESD stress, we designed ESD sensing components that can be used at different voltages. These ESD sensing components will be implemented using a circular layout. By changing the drift region and Poly2 parameters with a fixed gate terminal, we proposed a new design with eight sets of parameters. As the length of the drain-side drift region (LD) increases, the parasitic resistance of the drift region also increases, which will improve the ability of the device to withstand ESD currents. Eventually, to further analyze the ESD capability of the component, a transmission-line pulse (TLP) test system was used for the DUT. When LD is 28 μm, the device is optimal. The It2 of the device can reach 4.43 A. The FOM is also used to determine the ESD capability of the component, which can reach a maximum of 3.15 × 102 (A·V/μm²). [ABSTRACT FROM AUTHOR]

In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications. [ABSTRACT FROM AUTHOR]

This article discloses a unique failure mode in high-voltage bidirectional (Bi-Di) silicon-controlled rectifier (BDSCR) cells during International Electrotechnical Commission (IEC) air discharge electrostatic discharge (ESD) events. Failure was found to be sensitive to IEC measurement conditions or variabilities such as the speed of IEC gun and angle of approach, which causes different stress rise times. Hence, observed failure was a peculiar function of the rise times of the discharge current waveform. Remarkably, failure in high-voltage BDSCR was observed only for a window of current rise times. A new approach is presented using 3-D TCAD simulations of multifinger BDSCR to study and probe the failure mechanism dependent on these system-level stress parameters and variabilities. By emulating the experimental conditions in a 3-D TCAD environment, physical insights are developed to probe the root cause of the observed air discharge failures. Furthermore, a device engineering approach has been proposed, with the help of 3-D TCAD simulations of multifinger BDSCR, which computationally demonstrated improved robustness of BDSCR multifinger cells against IEC air discharge failures. The proposed design mitigates the nonuniform turn-on and failure due to IEC stress or rise time variability at the cost of a negligibly small area overhead. [ABSTRACT FROM AUTHOR]

This article presents novel methodologies and practical design considerations for a $D$ -band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology for beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch (SW) topology, including the power amplifier (PA) output and the low noise amplifier (LNA) input matching networks, to minimize the losses in both Tx and Rx modes. Based on this synthesis, an asymmetric T/R SW topology is realized with intrinsic electrostatic discharge (ESD) protection. Both the stacked-field-effect transistor (FET) PA and LNA adopt differential topologies with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics. Passive gain-boosting techniques are used for both PA and LNA to enhance different TRx specifications. A reusable unit-cell layout strategy is applied for transistor arrays to accelerate the multiple-stage PA implementation and maintain uniform performance and minimal parasitics. At 140 GHz, the Tx achieves a power gain $G_{p}$ of 33.6/35.7 dB, a saturated output power $P_{\mathrm{ sat}}$ of 12.5/14.7 dBm, a peak power-added efficiency (PAE) of 10.8/11.3%, and an output 1-dB compression point (OP1dB) of 9.4/11.2 dBm with nominal/boosted supplies. An average output power (${P_{out}}_{avg}$)/PAE of 4.9 dBm/2% is obtained for a 4-GHz bandwidth 64-QAM single-carrier signal at an error-vector magnitude (EVM) of −24.8 dB. Moreover, its Tx-mode reliability has been assessed. At 140 GHz, the Rx achieves a 20-dB $G_{p}$ , a −24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA/LNA core area of 0.024/0.032 mm2, respectively. [ABSTRACT FROM AUTHOR]

An on-die oscilloscope circuit is proposed to monitor the power noise waveforms inside IC due to the transient stress events for a more complete analysis of the effects of the transient stress events on the electronic systems. When the transient stress event occurs, the induced noise voltage waveform in the power supply is sampled and converted to digital data in real time. A trigger signal created by the event detector circuit is used to hold the digital data. The stored digital data inside the on-die oscilloscope are reconstructed back to the analog noise waveform based on the sampling process. The operation of each circuit block in the on-die oscilloscope is analyzed and validated by simulation and measurement results. The approximate bandwidth of the proposed on-die oscilloscope is extracted from simulation results. The power noise waveforms due to the transmission line pulse events and electrostatic discharge events are measured with an external oscilloscope instrument using cables and directly sampled and reconstructed by the on-die oscilloscope, and these measured and reconstructed analog noise waveforms are compared with each other. [ABSTRACT FROM AUTHOR]

In this paper, we propose a double diode network including an additional stacked diode, which provides robustness against Electrostatic discharge (ESD) and high-frequency interference signals. The proposed stacked diode in the conventional double diode network protects the integrated circuit from instantaneous voltage events by providing an additional current path to the double diode network. Also, it can structurally minimize the parasitic capacitance generated in the diode. The general operating principle and limitation of the conventional double diode network for ESD events and high-frequency interference signals were analyzed and simulated. For experimental verification, a cascode LNA with inductive source degeneration was designed in a 130nm CMOS Silicon-on-insulator (SOI) process for the time-division long-term evolution (TD-LTE) application at the coexistence band. The LNA with the proposed double diode network provides a noise figure of 1.08 dB and a small-signal gain of 18.7 dB at 2.65 GHz (Band 41). And it was measured to be able to protect the internal circuit at 2000 V HBM event, and the RF performances were not affected even with a high-frequency interference signal close to 30 dBm.

Electrostatic discharge (ESD) transient events can often damage semiconductor components. Therefore, the ultrahigh-voltage (UHV) circular n-channel lateral diffused metal-oxide-semiconductor transistor (nLDMOS) usually used in power electronics needs to have ESD self-protection capabilities. In this paper, the geometric parameters of 300-V and 200-V UHV circular nLDMOSs were modulated using different layouts at the drain side. The high-voltage p-well (HVPW) layer was used to form various super junctions (SJs) in the drift region. The modulations were classified as SJ length, SJ concentration-gradient thickness, HVPW ring-sector, and rotated SJ concentration gradient modulations in the drift region. Various HVPWs were used to produce several SJs in the drain drift region. According to the final measurement results, all modulation processes maintained the original physical characteristics of high breakdown voltage. Devices with the SJ length and SJ concentration-gradient thickness’s modulations provided the best ESD robustness. The ESD testing value of the human-body model (HBM) will increase with the increase of the SJ length and SJ thickness modulations. The HBM value increased from the 1500 V reference to 4000V (increased by 166.66%).

The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18- ${\mu }\text{m}$ CMOS technology.

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific on-resistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers' local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness. [ABSTRACT FROM AUTHOR]

In this article, a novel design approach for improving electrostatic discharge (ESD) robustness of high-voltage laterally double-diffused MOS (LDMOS) devices is presented using detailed 3-D TCAD simulations. The proposed method considers engineering both static filament and dynamic/moving current filaments in LDMOS design. Physical insights and engineering approaches for moving filaments at higher stress current levels are presented. Dynamic filament motion and its relation to n-p-n turn-on engineering with an optimum p-well profile and substrate biasing are revealed. A unique window failure in LDMOS near snapback is discussed for the first time. A detailed analysis is presented on filament width engineering by using optimum drain diffusion length (DL) and its influence on static filament-induced window failures. This approach resulted in ten-time improvement in ESD robustness for self-protecting concepts. Finally, different fundamental questions related to the origin of filament motion are explored (using 3-D TCAD) with the help of engineered LDMOS Designs. [ABSTRACT FROM AUTHOR]

It is challenging to simulate the snapback behaviors under electrostatic discharge (ESD) stresses due to the limitation of simulation program with integrated circuit emphasis (SPICE) simulation tools. In this brief, a new model is proposed to investigate the avalanche breakdown effect using the voltage-controlled current source (VCCS), which greatly facilitates the calculation of the avalanche multiplication factor ${M}$ and improves the convergence characteristics. In particular, this new method transfers the exponential relationship of ${M}$ into the linear relationship of the VCCS gain. The versatility of the model is validated by its operations in various ESD protection circuits with MOS as the discharge device, while the scalability is demonstrated by its applications in varied device sizes. [ABSTRACT FROM AUTHOR]

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

Accurate analysis of susceptibility of circuits from damage due to electrostatic discharges (ESDs), electromagnetic pulses, and lightning effects is required to ensure reliable operation of electronic devices and systems. A generalized theory of calculating semiconductor device thermal failure was developed for the use in circuit simulation. Thermal convolution integrals were developed from simple physical assumptions and used to predict device damage. This basic model was normalized to a generic failure function, and then, generalized to better match empirical test data of semiconductor device failure. This representation was transformed into the Laplace domain and further generalized to incorporate the steady-state thermal response of the device and provide numerical stability. The thermal convolution integral representation was used to derive a simple expression for Wunsch–Bell burnout parameters from ESD ratings of devices. A model was developed using the Laplace domain representation of the device failure theory. This circuit model allows for burnout predictions using commercial circuit simulation software and follows the theoretical equation with 2% error. The developed equations and circuit models allow for a simple susceptibility analysis of circuits using commercial software and readily available ESD ratings of semiconductor devices. [ABSTRACT FROM AUTHOR]

This paper studies a composite power n-channel lateral-diffused MOSFET device with a super junction (SJ) and parasitic silicon-controlled rectifier structure (nLDMOS-SJ-SCR) in the drain side, which can be used for electrostatic discharge (ESD) and latch-up (LU) reliability enhancements of 60-V power electronics. For ESD and LU protection considerations, the drain side with an SJ structure integrated with p-n-p- and n-p-n-arranged types of nLDMOS-SCR transistors is demonstrated. According to the experimental data, the layout of the SJ structure in the drain side has positive effects on ESD and LU capabilities. The layout type of nLDMOS-SJ with a pillar width W = 9μm has the highest secondary breakdown current (It2) values; the ESD (LU) improvement was 46.3% (13.3%) compared with the nLDMOS reference sample. Meanwhile, an nLDMOS-SJ with a pillar width W = 27μm has the highest figure of merit (FOM) value. By contrast, an embedded p-n-p-(n-p-n-)arranged type SCR structure was added into the drain side once again. Initially, it has a positive (negative) effect on the ESD reliability. Furthermore, the ESD (figure of merit; FOM) improvement was 37.9% (13.72%) of the corresponding nLDMOS-SJ device for nLDMOS-SJ-SCR (p-n-p) with W = 27μm. Overall, an nLDMOS-SJ device integrated with the p-n-p-arranged-type SCR in the drain side is a favorable choice for ESD and LU improvements.

A new behavioral model of gate-grounded NMOS (ggNMOS) device is proposed for electrostatic discharge (ESD) simulation of snapback behavior. The concise snapback model is a solution for the lack of snapback characteristics of build-in SPICE models in high voltage conditions. Modeling analysis, verification of snapback behavior and transient response under ESD stress are shown in this work. The new snapback model is intuitive to be understood and useful for ESD designers who do not have extensive modeling experience and skills. All the parameters in the proposed model like triggering voltage (Vt1), holding voltage (Vh) and on-resistance (Ron) can be directly extracted by transmission line pulsing (TLP) test. Further, simulation of transient response to human body model (HBM) stress is performed and the predicted currents and voltages are verified by the relevant HBM test.

In this paper, a tunnel field-effect transistor (TFET)-based voltage detector is proposed and its electrical characteristics are investigated using technology computer-aided design (TCAD) simulation. The operating principle of the proposed voltage detector is explained and possible applications in electrical overstress (EOS) and electrostatic discharge (ESD) protection are explored. Moreover, the impact of the key parameters on device performance is also discussed. The simulation results show that the proposed TFET-based voltage detector has a low leakage current and high detection sensitivity under EOS events compared to traditional diode-based detectors. With an additional nMOSFET capacitor, the proposed circuit can also be used for ESD protection.