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This paper presents an ultra-low power 3T gain-cell embedded DRAM (GC-eDRAM) cell in fin field-effect transistor (FinFET). This memory structure uses fast and low leakage FinFET transistors to improve frequent refresh issue and reduce retention power consumption. To achieve high retention time and low leakage power, we use series low power transistors in the path of data failure reducing the leakage current thanks to the stack effect. Due to the slower failure of data '1' and '0', data retention time (DRT) and thus refresh frequency improving, refresh power and retention power reduction would be achieved. The 2-kB array was simulated in FinFET sub-22 nm process nodes using HSPICE. The proposed structure at 20 nm FinFET technology demonstrates over 130× higher DRT, 70% lower static power consumption, and over 50% lower cell area than the 4T cell in 28 nm fully-depleted silicon-on-insulator (FD-SOI) technology. Additionally, it offers three orders of magnitude reduction in retention power consumption compared to 4T DRM and 4TSS cells. The proposed 3T cell provides 100–1000× higher DRT than the 4TSS cell in FinFET sub-22 nm technologies. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) inference and training produce a large amount of intermediate data. To achieve high energy efficiency, sufficient on-chip buffer is preferred to reduce the energy and time consuming off-chip DRAM access. However, SRAM buffer suffers from large area cost and high standby power due to its large cell size and high leakage current. Although embedded DRAM (eDRAM) offers higher memory density, its energy consumption is high due to frequent refresh operation, which is induced by the short refresh interval (40∼100μs). In this paper, a dual-mode buffer memory based on the CMOS compatible HfZrO2 ferroelectric material is proposed for DNN accelerators. It can operate in both volatile eDRAM mode and non-volatile ferroelectric RAM (FeRAM) mode. The functionality of the proposed dual-mode memory bit-cell design is verified using SPICE simulation with the multi-domain Preisach physical model. A data-lifetime-aware memory mode configuration protocol is proposed to optimize the buffer access energy for both DNN inference and training. Detailed circuitry and architectural support for the dual-mode memory are presented. For DNN training with ferroelectric-field-effect-transistor (FeFET) and SRAM-based compute-in-memory (CIM) accelerator, the proposed dual-mode buffer design improves the overall energy efficiency by 92.2%∼98.7%, 44.1%∼47.6%, 12.6%∼13.0% compared to baseline designs using SRAM buffer with the same buffer area, eDRAM and FeRAM with the same buffer capacity, respectively. For DNN inference with tensor-processing-unit (TPU)-like systolic array, the energy efficiency during computing is improved by 40.7%∼45.6%, 18.4%∼29.6% compared to the designs with eDRAM and FeRAM buffer, respectively. By storing the persistent data using the non-volatile mode, the energy efficiency of systolic array is improved by 2.3×∼5.5× over SRAM-based design when standby is frequent. The chip area overhead of the dual-mode buffer design is 5.2%, 4.1% and 7.2% for FeFET-based-CIM, SRAM-based-CIM and systolic-array-based accelerators using eDRAM buffer, respectively. [ABSTRACT FROM AUTHOR]

Computing-in-memory (CIM) shows high energy-efficiency through the analog DNN computation inside the memory macros. However, as the DNN size increases, the energy-efficiency of CIM is reduced by external memory access (EMA). One of the promising solutions is eDRAM based CIM to increase memory capacity with a high density cell. Although the eDRAM-CIM has a higher density than the SRAM-CIM, it suffers from both poor robustness and a low signal-to-noise ratio (SNR). In this brief, the energy-efficient eDRAM-CIM macro is proposed while improving computational robustness and SNR with three key features: 1) High SNR voltage-based accumulation with segmented BL architecture (SBLA), resulting in 17.1 dB higher SNR, 2) canceling PVT/leakage-induced error with common-mode error canceling (CMEC) circuit, resulting in 51.4% PVT variation reduction and 51.4% refresh power reduction, 3) a ReLU-based zero-gating ADC (ZG-ADC), resulting in ADC power reduction up to 58.1%. According to these new features, the proposed eDRAM-CIM macro achieves 81.5-to-115.0 TOPS/W energy-efficiency with 209-to-295 $\mu \text{W}$ power consumption when 4b $\times $ 4b MAC operation is performed with 250 MHz core frequency. The proposed macro also achieves 91.52% accuracy at the CIFAR-10 object classification dataset (ResNet-20) without accuracy drop even with PVT variation. [ABSTRACT FROM AUTHOR]

Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both "1" and "0" data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology. [ABSTRACT FROM AUTHOR]

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped ${n}^{+}$ source and drain junctions, nearly intrinsic ${n}^{-}$ channel, 500-nm gate length (${L}_{{{\mathrm {G}}}}$), and 50-nm poly-Si body thickness (${T}_{{{\mathrm {body}}}}$). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of $3.2~{\mu }\text{A}/{\mu }\text{m}$ and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems. [ABSTRACT FROM AUTHOR]

Conventional static random access memory (SRAM) suffers from high leakage power when implemented in advanced CMOS nodes, while modified bitcells or assist techniques are required to achieve robust low-voltage operation. Gain-cell eDRAM (GC-eDRAM) is an interesting area-efficient alternative to SRAM, but requires refresh cycles and typically a boosted write word-line (WWL). This brief proposes a hybrid GC-eDRAM/SRAM bitcell addressing the leakage power and low voltage robustness issues of SRAM, while avoiding bandwidth-consuming refresh and WWL boost of conventional GC-eDRAM. In the hybrid 8T bitcell, an SRAM keeper latch is connected to the storage node (SN) of a gain cell. The SRAM keepers are power gated most of the time for leakage reduction; the keepers are powered on only during zero bandwidth consuming refresh cycles, after write, and before read, to ensure strong data levels on the SN. Compared to a conventional 6T SRAM bitcell, the hybrid 8T bitcell has a 2T read port and an interruptible keeper for both robust read and write at low voltages. Simulations in 65-nm CMOS show that the hybrid bitcell enables 35% (at 400 mV) to 55% (at 1 V) lower data retention power than an 6T SRAM cell at 25 °C. [ABSTRACT FROM AUTHOR]

This paper describes a three- dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SOI (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D wafer-to-wafer bonding process because of the absence of deep etched and filled trench capacitor structure, and the improved thickness control tolerance in wafer thinning. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with a microprocessor, achieving low cost, high-density on-chip main memory. A 394Kbits test chip has been designed and fabricated using the Lincoln Labs 3-Tier 3D 0.18um fully depleted SOI CMOS process where an earlier (and previously reported) successful 3D SRAM was obtained. The measured retention time under holding conditions in this 180 nm process is greater than 10 ms. The test chip measures an access time of 50 ns and operates at 10 MHz.

A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with \0.0174~\mu\m^2 deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1~Mb macro composed of 8\times2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor. [ABSTRACT FROM PUBLISHER]

Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18- $\mu $ m CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals. [ABSTRACT FROM PUBLISHER]

As CMOS technology scales, frontend wearout mechanisms, such as bias temperature instability, hot-carrier injection, and gate oxide breakdown significantly degrade transistor performance. We investigate the impact of these frontend wearout mechanisms on embedded DRAM cells, which are used for last-level caches owing to their high-density characteristics. Our results show that a cell transistor of eDRAM is more susceptible to gate oxide breakdown than bias temperature instability and hot-carrier injection. The impact of all such wearout mechanisms on a cell capacitor is negligible. Based on observations from our simulations, which estimate the performance degradation of eDRAMs resulting from frontend wearout mechanisms, we propose monitoring methods to proactively detect the failures of eDRAMs caused by frontend wearout mechanisms. [ABSTRACT FROM AUTHOR]

Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power consumed during periodic refresh operations. Refresh timing is traditionally set according to a worst-case evaluation of retention time under extreme process variations, and worst-case access statistics, leading to frequent power-hungry refresh cycles. In this brief we present a replica technique for automatically tracking the retention time of a gain-cell-embedded dynamic-random-access-memory macrocell according to process variations and operating statistics, thereby reducing the data retention power of the array. A 2-kb array was designed and fabricated in a mature 0.18- \mu\m CMOS process, appropriate for integration in ultralow power applications, such as biomedical sensors. Measurements show efficient retention time tracking across a range of supply voltages and access statistics, lowering the refresh frequency by more than $5\times$, as compared with traditional worst-case design. [ABSTRACT FROM PUBLISHER]

The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a general-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and further improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline coupling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm 2 65 nm LDPC decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the LDPC decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b. [ABSTRACT FROM AUTHOR]

An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains randomly chosen in 4 Mb embedded DRAM. Authentication is accomplished by regenerating various encrypted intrinsic fingerprints, which are then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average of 32 retention fails per domain, the strings are unique and authentication is statistically guaranteed without bit correction even when unstable bits are introduced. The preliminary results are confirmed in > 50 parts containing 4 Mb memory implemented in 22-nm SOI hardware under the target voltage ±10% conditions. The analytical model predicts > 10^20 years to crack the encryption by brute force, while satisfying > 99.9999% successful authentication for one million parts. [ABSTRACT FROM AUTHOR]

A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the corresponding challenge numbers. The algorithm further includes field-tolerant authentication by detecting a number of common bits analytically guaranteed for successful recognition, while preventing ID spoofing during the read operation. This results in 100% successful unique ID generation and recognition in two temperature and three voltage conditions per chip for a total of \sim420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 10^6 parts. Finally, a method to enable a field-tolerant ID using multiple domains will be discussed. [ABSTRACT FROM PUBLISHER]

Abstract: This paper presents a low-leakage 128kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90nm technology and achieves a low static power consumption of 130μW and an access time of 2ns. It has a worst case retention time of 175μs. This performance is achieved by introducing an optimised hierarchical organisation and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation. The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflicts with the refresh operation, the memory handles access recovery internally. [Copyright &y& Elsevier]

With 30nm-class memory cells in production and 20nm-class (20-29nm feature-size) memory targeted for next year, the standard 1-Transistor + 1-Capacitor (1T+1C) DRAM industry is making prominent efforts to improve the scalability of the cell capacitor while maintaining the minimum capacitance requirements for state discrimination, immune to noise (C~25fF/cell). To achieve the capacitance requirement, the DRAM cell has evolved from its initial planar implementation to complex three-dimensional structures. The increment in complexity and the large difference in size between the transistor and capacitor of each cell have motivated the search for Floating-Body Single-Transistor DRAM (1T-DRAM). The underlying idea behind 1T-DRAMs is the development of single-device memory cells with a pronounced hysteresis effect and fast operation. This chapter is focused on the floating-body effect as a primary source of hysteresis. We present new concepts able to deal with the basic limitations of 1T-DRAM while maintaining its simplicity. The floating-body 1T-DRAMs can be reconciled with the aggressive scaling constrains by considering new ideas which make possible the coexistence of electron and holes in the same ultrathin transistor. The best approach is to isolate each type of carrier in an specific potential well which is not created specifically by the bias conditions (unlike standard 1T-DRAMs) but by the physical structure of the device. [ABSTRACT FROM AUTHOR]

An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm^2/Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performances. A 32 KB DRAM buffer macro with 1.5 \mu\m^2 cell has been fabricated with a 32 nm NAND flash memory process. Even with small 3 fF cell using a planar MOS capacitor, an enough \pm100 mV cell signal has been obtained by introducing a technique to self-boost cell node up to 4 V using a merit of high-voltage NAND flash process, and two techniques to curtail parasitic bitline capacitance down to 60 fF at 128 wordlines per bitline. An undershoot problem of cell nodes due to unwanted plateline bounce is resolved by a two-step-rise/fall wordline scheme. Installation of dummy cell scheme to obtain a half of “1” data (not an average of “1” and “0” data) cuts out 32 KB macro size by 1.3% while suppressing mismatch to 3 mV at the grounded bitline precharge. The 32 KB test vehicle shows 90 ns random cycle time with 15 ns burst cycle time (66 Mb/s/pin). The measured characteristics of 2\,\times\,\10^-18 bit error rater (BER) by soft error and 10 ms data retention at 85\,^\circ\C are enough for page buffer application in a NAND flash memory. The measured active current of 32 KB macro is 7 mA at 90 ns random cycle, but only 3.2 mA at practical use of 15 ns burst with 256B page access. [ABSTRACT FROM PUBLISHER]

This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm^2 die, employing 1.2B transistors in a 45~nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 \mum^2 DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning. [ABSTRACT FROM AUTHOR]

We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability. [ABSTRACT FROM AUTHOR]

This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower latency. This speed increase is achieved by not conserving the content of the DRAM cell after a read operation. Random access time to DRAM was reduced from 6 ns to 3 ns in a prototype made by Hwang et al. A write-back buffer was used to conserve data. We have proposed a new scheme for write-back using the usually smaller cache instead of a large additional write-back buffer. Write-back is performed whenever a cache line is replaced. This increases bus and DRAM bank activity compared to a conventional architecture which again increases power consumption. On the other hand computational performance is improved through faster DRAM accesses. Simulation of a CPU, DRAM and a 2 kbytes cache show that the power consumption increased by 3% while the performance increased by 14% for the applications in the SPEC2000 benchmark. With a 16 kbytes cache the power consumption increased by 0.5% while performance increased by 4.5%. [ABSTRACT FROM AUTHOR]

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D²RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D²RAM fabricated by a 0.15-μm standard CMOS process. [ABSTRACT FROM AUTHOR]

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 µm². In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the OTCAM cell and the PHS architecture, small silicon area of 32 mm² for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips. [ABSTRACT FROM AUTHOR]

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a powerdown data retention (PDDR) mode is developed. A 13.98-mm² 16-Mb embedded DRAM macro is fabricated in 0.13 µm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-µW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes. [ABSTRACT FROM AUTHOR]

High-performance and low-power microprocessors are key to PDA applications. In this paper, a dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM. The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6 V in steps of S mV, achieving 82% power reduction in Personal Information Management scheduler application and 40% power reduction in MPEG4 movie playback. This low-power embedded microprocessor, fabricated with 0.18-µm CMOS embedded DRAM technology, enables high-performance operations such as audio and video applications. As process technology shrinks, this adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power mobile consumer applications. [ABSTRACT FROM AUTHOR]

We have evaluated the role of embedded dynamic random access memory (eDRAM) in the performance of programmable mediaprocessors, focusing on video/image computing. eDRAM’s contributions to improving the total system performance can be assessed by measuring the number of CPU stall cycles caused by the memory transactions. We decomposed the CPU stall cycles into three components: latency due to row access, latency due to the pipeline of memory transactions, and burst transfer time. We used a cycle-accurate cache and eDRAM model to measure the system performance in executing selected low-level video/image computing functions on a mediaprocessor core. We simulated various values for data bus width, page size, and row-access time of eDRAM, pipeline delay of a memory transaction, and data cache line size. While the wider data width of eDRAM does reduce the burst transfer time, the actual reduction in the total stall cycles when the width was expanded from 8 to 16 bytes was lower than expected, ranging from 6.2% to 18.9%. Instead, we found that the row-access latency and memory transaction pipeline delay represent the major portion of the CPU stall cycles. For example, in case of 32-byte wide data bus, they account for 85.3–95.1% of the memory busy time during which data cache misses are serviced. We show how to lower the CPU stall time further, e.g., using no-write-allocate data cache to reduce the total burst transfer time, efficient memory banking to reduce the number of eDRAM page misses, and various software/hardware methods to bring data to the cache before they are needed by the CPU. In particular, the regular memory access pattern in video/image computing allows several methods to enhance the memory performance in using eDRAM, e.g., enlarging the cache line size and data prefetching. This paper presents our methodology, experimental results, and findings, which would be useful to the design of highly integrated systems on a chip with eDRAM in the future. [Copyright &y& Elsevier]

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported functionality. However, GC-eDRAM requires periodic refresh cycles to maintain its data due to its dynamic storage mechanism. The refresh operation is typically handled at a memory controller level, resulting in an energy overhead and limited memory availability. In this paper, we propose a new approach for the realization of the refresh operation using an internal refresh mechanism, which supports an efficient row-wise refresh operation within a single clock cycle, providing 100% write access availability at a reduced refresh latency and power. An 8 kbit GC-eDRAM array with integrated internal refresh and replica bit-line was implemented, demonstrating up-to 30% reduced refresh latency and 65% reduced read energy at a low cost of 2.4% array area overhead, compared to a conventional GC-eDRAM array without internal refresh capabilities. [ABSTRACT FROM AUTHOR]