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A comprehensive range of static measurements and UIS tests have been conducted for Silicon PiN diodes, SiC JBS diodes and SiC MPS diodes with temperatures ranging to up to 175°C. The results shows that the forward voltage of Silicon PiN diode is lower at the on-state, even at high temperatures and at high currents. Higher forward voltage and positive temperature coefficient are observed for SiC devices during the static measurements, while they outperform the Silicon devices in terms of the electrothermal ruggedness, as validated by the UIS measurements and its subsequent calculated avalanche energy and die area as measured by means of CT-Scan imaging of the devices.

In GaN e-HEMTs, Threshold Voltage (VTH) shift from gate voltage (VGS) stress depends on the VGs magnitude, stress time, recovery time (time between stress removal and VTH measurement), temperature and pulse polarity (0 to +VGS or −VGS to +VGS ). In this paper, unipolar (0 to VGS) and bipolar (−VGS to +VGS) pulsed gate stresses have been performed on GaN e-HEMTs with different VGS magnitudes. The pulse frequency ranges from 25 Hz to 200 kHz. The results show negative VTH shifts for unipolar VGS pulses (between 5V and 8V) at long recovery times (above 500 seconds). The VTH shift is proportional to the VGS pulse magnitude. When the recovery time is increased from 50 milliseconds to 500 seconds, the measured VTH shift becomes more negative, indicating a faster release of trapped electrons than holes. In bipolar stresses, results show both positive and negative VTH shifts with no clear magnitude or frequency dependencies.

This paper investigates the peculiarities and challenges of accurate threshold voltage ( VTH ) measurement after gate bias stress in SiC MOSFETs and GaN e-HEMTs. Traditional techniques historically used in silicon MOSFETs involve test sequences typically comprising preconditioning, VTH measurement, gate voltage stress and VTH measurement after stress. However, with Wide bandgap (WBG) devices like SiC and GaN transistors, the repeatability of VTH measurement, the impact of VTH measurement duration, delay between successive measurements and the role of preconditioning on the accuracy of VTH are currently under study. With current industrial and academic research interest in bias temperature instability in WBG devices, this paper provides significant insight into how repeatable VTH measurement is in WBG devices since measuring VTH can change it. The impact of repeated measurements on the cumulative VTH shift is investigated in both WBG technologies with different delay times between successive measurements with and without preconditioning. Unipolar and Bipolar preconditioning pulses are compared regarding VTH measurement in SiC MOSFETs.

Using experimental measurements and finite element simulations, this paper investigates the failure mode of SiC Cascode JFETs under short circuit (SC) conditions. Unlike SiC MOSFETs, where failure results in a shorted gate-source terminal (resulting from gate oxide failure), in SiC Cascode JFETs, failure usually occurs in drain-source short with the gate of the Low Voltage (LV) silicon MOSFET still operational. Measurements show that after the LV Si MOSFET gate is turned OFF, a high tail current results in the Cascode drain terminal with the drain-source voltage falling to approximately half of the blocking voltage, suggesting that the JFET is in linear mode. Finite element simulations show that thermally generated carriers in the JFET depletion region cause high leakage currents through the internal JFET gate terminal capable of turning-ON the JFET (after turn-OFF of the LV Si MOSFET) into linear mode. The measured short circuit withstand time (SCWT) is shown to be independent of temperature unlike silicon MOSFETs where the SC withstand time increases with the initial temperature.\ud

This letter reports on the improvement of a SiO2 layer formed by atomic layer deposition on 4H-SiC, using a post-deposition anneal in forming gas ambient. Capacitance–voltage measurements revealed good electrical properties, compared to a thermal oxide which was grown in N 2 O, with flatband voltage values averaging at -0.29 V and a low positive mobile ion charge density in the order of 1010 cm−2. XPS analysis revealed the FG annealed sample to have the most Si rich interface comparatively to other PDAs, with a C:Si ratio of 0.72, allowing more Si bonds to be terminated. SIMS analysis identified an increase in hydrogen near the interface of the FG-annealed sample with a peak concentration of 2.12 × 1021 cm−3. It is concluded that the improvement in electrical performance is due to the hydrogen passivating trap states at the SiO2/4H-SiC interface.

Short-Circuit (SC) current sharing in parallel connected SiC MOSFETs and SiC Cascode JFETs have been investigated using experimental measurements and finite element models. Device parametric variation between parallel devices contributes to uneven current sharing and reduced module robustness against SC events. Experimental measurements show that threshold voltage variation is the most critical parameter in SiC MOSFETs, more so than device switching rate and initial junction temperature. The temperature coefficient of the ON-state and saturation resistance of SiC Cascode JFETs is higher than that of the SiC MOSFETs, hence, the short-circuit energy is lower because the SC current is limited more quickly in the SiC Cascode JFETs compared to SiC MOSFETs. Also, the input silicon MOSFET in the Cascode arrangement ensures better performance regarding VTH mismatch between parallel devices under SC. This is because the threshold voltage variation is less in silicon MOSFETs compared to SiC MOSFETs. Finite element models have been used to explore the differences between SiC MOSFETs and SiC Cascode JFETs under SC conditions and to explain why JFETs are better at suppressing SC currents than MOSFETs.

To control power flow and manage fault level in meshed MV networks, back-to-back voltage source converters (B2B-VSCs) are being used. However, their high cost and relatively low efficiency are of concerns. Partially rated series compensators, such as SSSCs or UPFCs, are desired but come with the challenge of protecting the device during grid faults. Their potential of use has been limited in comparison with the fully rated back-to-back converters. This paper proposes a new system topology including thyristor crowbars and a varistor to protect the SSSC in an MV network and improve the reliability and flexibility of the network operation. Using the proposed method, the time required for isolating the series compensator from the grid is reduced from at least 20 ms, corresponding to the interruption time of conventional circuit breakers, down to 3 μs in the worst case in addition to the grid fault detection delay. The performance is evaluated by simulation. A small-scale single-phase prototype operating at 230 V/16 A is tested in order to demonstrate the concept.

A new packaging structure for clamping the temperature of a thyristor die is analysed in this paper. The proposed structure aims to absorb the heat released from the thyristor during a short circuit protection operation, to maintain the temperature within a defined range even when the current through the thyristor is temporarily very high. The defined range is below the maximum tolerable temperature and is controlled by using phase-change material (PCM). This has the potential to reduce both space and cost when compared to traditional packaging structures which utilise heat sinks. In the course of this investigation, a thermal model of a thyristor is used for comparison. COMSOL Multiphysics was used to simulate the thyristor temperature during a fault and the effect that the PCM has on the thyristor temperature. Experiments have been performed to verify the models and validate the feasibility of the proposed concept.

The main requirements of the wide-area monitoring system is to acquire the real-time measurement of state variables that can be provided by phasor measurement units (PMUs). The optimal PMU placement is the leading object of this paper, which is presented as an integer linear programming problem. The zero injection buses (ZIBs) and conventional measurements (CMs) enhance the system observability. In this paper, a novel integrated model is presented to consider the effects of the ZIBs and CMs for PMU placement. The proposed model considers limitations caused by ZIBs and CMs that have not been studied earlier. The single branch and single PMU outage, as two common contingencies, are also separately and simultaneously taken into account. The proposed method is applied to five different IEEE test systems (14, 30, 39, 57, and 118 bus) in order to demonstrate its effectiveness. The obtained results are compared with that of the other studies.

Magnetic gears (MGs) offer significant potential advantages relative to conventional mechanical gears, such as: no contact, no friction, no lubrication, inherent overload protection and free from noise and vibration. Despite of these superior features they have received little attention due to complexity of operation and relatively low torque density transmission. This paper introduces a new magnetic gear topology with a highly competitive torque density transmission capability. This configuration is inspired of combination of the traditional radial and axial flux MGs. The assurance of accuracy based on a basic design of axial flux magnetic gear dimensions leading to Proof-of-Concept “Arcuate Double-Sided MG”. The Proof-of-Concept seeks to provide a better solution to the problems of flux maldistribution and concentration compared to what has been proposed previously. Thus, torque density performance of this MG is intensively augmented. The cogging torque is also computed in further simulations. However, the above requires advanced numerical techniques and hence 3-Dimensional simulations for calculating localized flux density and the corresponding torque density. Completion of this development will mark an important milestone in magnetic gear technology, and significant performance improvement will be realized.