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Faster-than-Nyquist (FTN) signaling has attracted increasing interest in the past two decades. However, when the fifth-generation (5G) communication low-density parity check (LDPC) code is applied to FTN signaling with low Bahl–Cock–Jelinek–Raviv (BCJR) states of detection and few turbo equalization iterations, an error floor near 10 − 5 is found, which does not exist in the original LDPC used for orthogonal signaling. This can be eliminated through many detection and decoding iterations, but this is unacceptable considering the increase in latency and storage. To solve this problem, we propose an LDPC and Reed–Solomon (RS) concatenation code, shortening, and perturbation scheme to lower the error floor. We propose a parallel encoder architecture for RS component code and a concise algorithm to calculate its constant multiplier coefficients, leveraging a traditional serial encoder, which can also be used for other parallelisms, rates, and lengths. The simulation results show that the proposed concatenation and shortening scheme can lower the error floor to about 10 − 7 . The proposed scheme has an error correction capability for coded FTN signaling and successfully lowers the error floor with the limitation of few turbo iterations and few BCJR states. [ABSTRACT FROM AUTHOR]

A key problem of low-density parity-check (LDPC) codes analysis is estimation of an extremely low error floor that occurs at a high level of the signal-to-noise ratio (SNR). The importance sampling (IS) method is a popular approach to address this problem. Existing works typically use a normal sampling probability density function (PDF) with shifted mean, which yields a large variance of the estimate. In contrast, uniform distribution has equally probable samples on the entire range and thus should reduce the variance, but results in a biased estimation. This paper proposes a modified IS approach (IS-U) that allows considering the uniform distribution as a sampling PDF, and shows that this estimation is better than the traditional one. Also, this paper demonstrates that the existing criteria cannot be applied to evaluate the accuracy of the IS-U on the whole SNR range. To address this issue, a new metric is proposed, which uses only the convergence rate and does not depend on the true data. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel state-space model to represent the behavior of sum-product algorithm (SPA) in the vicinity of a trapping set (TS) of a low-density parity-check (LDPC) code over the additive white Gaussian noise (AWGN) channel in the error floor region. The proposed model takes into account the non-linear behavior of SPA in the initial iterations using a quadratic approximation, and dynamically adjusts the operating point of the model in accordance to the statistical properties of TS messages. This is in contrast to the existing linear state-space models which linearly approximate the non-linear behavior of SPA at around the operating point of zero in all iterations. Simulation results are provided to demonstrate the higher accuracy of the proposed model in estimating the error floor of LDPC codes compared to the linear state-space model. We also make connections to the semi-analytical code-dependent technique proposed by Richardson for the error floor estimation of LDPC codes, and demonstrate that the proposed state-space model not only is a fully-analytical code-independent counterpart to that method, but also has less complexity and, in some cases, more accuracy. [ABSTRACT FROM AUTHOR]

This paper considers channel-unaware two-way relay networks (TWRNs) with a single-antenna decode-and-forward (DF) relay. These networks typically rely on differential signalling which results in error propagation and error floors. To overcome this drawback, we develop a novel differential signalling scheme, which, in contrast with existing ones, does not cause detection errors to propagate from one block to the next. We obtain a union bound on the block error rate (BLER), which shows that the proposed differential method exhibits superior performance to existing schemes, eliminates error floors and results in a BLER that decays as the inverse of the signal-to-noise ratio. Furthermore, the proposed scheme removes the unitarity restriction on the transmitted symbols in conventional differential signalling. Therefore, non-unitary symbols can be used in the differential signalling which provides more degrees of design freedom and better performance. Our numerical results confirm our analytical findings. [ABSTRACT FROM AUTHOR]

In this letter, we analyze the error floor of column layered decoders, also known as shuffled decoders, for low-density parity-check (LDPC) codes under saturating sum-product algorithm (SPA). To estimate the error floor, we evaluate the failure rate of different trapping sets (TSs) that contribute to the frame error rate in the error floor region. For each such TS, we model the dynamics of SPA in the vicinity of the TS by a linear state-space model that incorporates the information of the layered message-passing schedule. Consequently, the model parameters and the failure rate of the TS change as a result of the change in the order by which the messages of different layers are updated. This, in turn, causes the error floor of the code to change as a function of scheduling. Based on the proposed analysis, we then devise an efficient search algorithm to find a schedule that minimizes the error floor. Simulation results are presented to verify the accuracy of the proposed error floor estimation technique. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC) codes decoded by the sum-product algorithm (SPA) with row layered message-passing scheduling. For this, we develop a linear state-space model of trapping sets (TSs) which incorporates the layered nature of scheduling. We demonstrate that the contribution of each TS to the error floor is not only a function of the topology of the TS, but also depends on the row layers in which different check nodes of the TS are located. This information, referred to as TS layer profile (TSLP), plays an important role in the harmfulness of a TS. As a result, the harmfulness of a TS in particular, and the error floor of the code in general, can significantly change by changing the order in which the information of different layers, corresponding to different row blocks of the parity-check matrix, is updated. We also study the problem of finding a layer ordering that minimizes the error floor, and obtain row layered decoders with error floor significantly lower than that of their flooding counterparts. As part of our analysis, we make connections between the parameters of the state-space model for a row layered schedule and those of the flooding schedule. Simulation results are presented to show the accuracy of analytical error floor estimates. [ABSTRACT FROM AUTHOR]

Distributed Luby transform (DLT) codes achieve a significant performance improvement in multi-source relay networks compared with the individual Luby transform (LT) code designed for each source. Since the DLT codes preserve the properties of the LT codes, the error floor is dominated by the low variable-node degrees in the bipartite graph, developed for iterative message passing decoding. Therefore, we analyze the error floor of the DLT codes for a multi-source, single relay, and a single destination network over additive white Gaussian noise (AWGN) channels. We modify the encoding process at the sources and propose a new relay combining scheme at the relay. The encoding process at the sources and the combining scheme at the relay are coordinated with the aim of improving the error floor performance of the proposed DLT codes. We derive a lower bound of the bit error probability of the DLT codes over AWGN channels. Furthermore, we optimize the relay degree distribution in terms of the overhead by using the framework of extrinsic information transfer chart analysis. The numerical results confirm that the proposed DLT coding scheme significantly outperforms the conventional scheme, especially in the error floor region.

In this paper, we propose a design technique for the construction of variable-regular time-invariant spatially-coupled low-density parity-check (SC-LDPC) codes with small constraint length and low error floor. The proposed technique reduces the error floor by imposing simple constraints on the short cycles in the code’s Tanner graph, which in turn, result in the elimination of the most dominant trapping sets of the code. In some cases, we also derive lower bounds on the syndrome former memory for satisfying such constraints. The designed codes are superior to the state-of-the-art in terms of error floor performance and/or decoding complexity and latency. [ABSTRACT FROM AUTHOR]

In this article, we design finite-length irregular protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) codes with good waterfall performance and low error floor. To achieve a low error floor, we eliminate a targeted set of dominant elementary trapping sets (ETS) ${\mathcal{ L}}$ in the Tanner graph of the code. For a given rate and girth, the codes are designed to be free of the largest set of problematic ETSs for a given block length, or to have the shortest block length while a given set of ETSs is avoided. The design is based on a search algorithm that identifies whether any instance of any structure within ${\mathcal{ L}}$ exists in the Tanner graph of the constructed code or not. The search algorithm performs this task with minimal complexity, making it feasible to construct practical codes by running the search algorithm a large number of times. Simulation results are provided to demonstrate the superior performance of designed codes compared to similar state-of-the-art irregular QC-LDPC codes. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Chongqing University of Posts & Telecommunications (Natural Science Edition) is the property of Chongqing University of Posts & Telecommunications and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This letter presents a low-complexity error floors estimation method for bit-interleaved coded modulation with quasi-cyclic low-density parity-check (LDPC) codes. Using surrogate bit-channels (SBCs) as hypothetic equivalent channels, the importance sampling method based on the stable trapping sets is applied to evaluate the error floors. It is shown that the error floors of bit-interleaved coded modulation systems can be effectively estimated, and the presented method is appropriate for various types of modulators and interleavers. [ABSTRACT FROM AUTHOR]

In this paper, we study the performance of spatial modulation (SM) employing Euclidean distance-based antenna selection (EDAS) operating in a realistic error-infested feedback channel, which has hitherto only been studied under ideal feedback channel conditions. Specifically, we model the feedback channel by a bit-flip probability δ and study its impact on the forward link employing EDAS. We show that the erroneous feedback channel severely degrades the performance of EDAS-aided SM (EDAS-SM) system by imposing an error floor in the forward link. Furthermore, we quantify the error floors associated both with the spatial and with the conventional symbols with the aid of asymptotic symbol error rate analysis. The expressions derived for the error floors in the forward link are utilized for optimizing the feedback signaling, which are shown to help reduce the error floor levels. Furthermore, a pilot-aided selection verification (PSV) algorithm is proposed for mitigating the effects of antenna-set mismatch between the transmitter and the receiver, which eliminates the error floor in the forward link. Simulations are conducted in order to validate the theoretical results presented in this paper. Furthermore, the bit-error ratio (BER) performance of the EDAS-SM is compared with that of the conventional antenna selection (C-AS) both in the PSV as well as in the no selection verification scenarios. It is observed that EDAS-SM outperforms C-AS in both the scenarios considered. Specifically, at a BER of 10-5, EDAS-SM is observed to give a 3-dB signal-to-noise ratio gain compared with the C-AS, when operating at a spectral efficiency of 7 bits per channel use in the face of a feedback BER of δ = 0.05.

In a joint source-channel coding (JSCC) system, excessive source compression can cause an error floor. In the original JSCC scheme based on double protograph LDPC (DP-LDPC) codes, only connections exist between check nodes (CNs) of the source protograph and variable nodes (VNs) of the channel protograph, and error floors are observed. In this paper, we investigate the joint protograph that forms the basis of a DP-LDPC code. The joint protograph consists of a source protograph, a channel protograph, and connections between the two protographs. Our main focus is on the complete-source-variable-linking (CSVL) protomatrix of the joint protograph, which determines the error floor of the DP-LDPC code. We propose a generalized source protograph extrinsic information transfer (GSP-EXIT) algorithm for evaluating the source decoding thresholds of the CSVL protomatrix. Based on the proposed algorithm, we analyze CSVL protomatrices with regular or irregular source protographs. We present design criteria for connections between VNs of the source protograph and CNs of the channel protograph. Such design rules will result in a higher source decoding threshold, which implies a lower error floor. We also propose a differential evolution algorithm for optimizing the source protograph. We present/compare analytical results and/with simulation results, and conclude that they are consistent. [ABSTRACT FROM AUTHOR]

The linear state-space model is a well-known code-independent method to estimate the contribution of a trapping set (TS) structure to the error floor of low-density parity-check (LDPC) codes. In this paper, we provide an in-depth analysis of this method by incorporating a more accurate model for the incoming messages to the TS structure that takes into account the randomness and the correlation among such messages. Based on this analysis, we demonstrate that both randomness and correlation result in the over-estimation of the failure probability of the TS. We then propose an alternate code-independent technique for the error floor estimation of iterative LDPC decoders that can accurately estimate the contribution of different TS structures in the error floor. Compared to the linear state-space model, the proposed method is not only more accurate, but also more general, in that, it is applicable to any saturating iterative message-passing decoder, symmetrically quantized or unquantized, over any memoryless binary-input output-symmetric channel. The proposed technique can be viewed as the local application of importance sampling (IS) to the message-passing algorithm over the subgraph induced by the TS in the code’s Tanner graph. In the message-passing process, to account for the effect of the rest of the Tanner graph, density evolution along with a simple correlation model is used to generate the messages coming into the TS from the rest of the Tanner graph. Extensive simulations demonstrate that the proposed technique can accurately estimate the error floor of LDPC codes over both additive white Gaussian noise (AWGN) channel and binary symmetric channel (BSC), for a variety of iterative decoding algorithms and quantization schemes. [ABSTRACT FROM AUTHOR]

A circulant-permutation-based spatially-coupled (SC) code is constructed by partitioning the circulant permutation matrices (CPMs) in the parity-check matrix of a block code into several components and piecing copies of these components in a diagonal structure. By connecting several SC codes, multi-dimensional SC (MD-SC) codes are constructed. In this paper, we present a systematic framework for constructing MD-SC codes with notably better cycle properties than their one-dimensional counterparts. In our framework, the multi-dimensional coupling is performed via an informed relocation of problematic CPMs. This work is general in the terms of the number of constituent SC codes that are connected together, the number of neighboring SC codes that each constituent SC code is connected to, and the length of the cycles whose populations we aim to reduce. Finally, we present a decoding algorithm that utilizes the structures of the MD-SC code to achieve lower decoding latency. Compared to the conventional SC codes, our MD-SC codes have a notably lower population of small cycles, and a dramatic BER improvement. The results of this work can be particularly beneficial in data storage systems, e.g., 2D magnetic recording and 3D Flash systems, as high-performance MD-SC codes are robust against various channel impairments and non-uniformity. [ABSTRACT FROM AUTHOR]

Irregular quasi-cyclic (QC) low-density parity-check (LDPC) codes with the block dual-diagonal (BDD) parity structure are widely adopted in many communication standards because the BDD structure supports an efficient encoding and many degree-2 variable nodes inside are adequate for the construction of mid- to high-rate codes. However, we observe that low-rate irregular QC LDPC codes with the BDD parity structure inherently contain too many degree-2 variable nodes and suffer from error floors in high signal-to-noise ratio (SNR) region. In this paper, a generalized BDD structure including double-weight circulants as well as circulant permutation matrices is proposed for low-rate irregular QC LDPC codes with low error floors which is achieved with a little bit giving up error performance in the waterfall region. When constructing the parity part of a code with the generalized BDD structure, the portion of double-weight circulants is variable so that the resulting LDPC code can achieve a desired degree distribution including degrees 2 and 3 while supporting the efficient encoding. We show that low-rate QC LDPC codes constructed with the proposed BDD structure have better theoretical properties and lower error floor than those with the conventional BDD structure. [ABSTRACT FROM AUTHOR]

In this letter, we design time-invariant spatially coupled low-density parity-check (SC-LDPC) codes with small constraint length and low error floor. For this, we modify the codes in the literature that have (close to) minimal constraint length for a given degree distribution and girth, to improve their error floor. This is performed by eliminating (or minimizing the multiplicity of) some of the dominant trapping sets (TSs) of the codes and/or increasing the minimum distance. To reduce the multiplicity of the TSs effectively and efficiently, we devise a technique based on the parent/child relationship between TSs that aims at successively minimizing the multiplicity of TSs depending on their harmfulness. [ABSTRACT FROM AUTHOR]

Quasi-cyclic low-density (QC-LDPC) codes benefit from efficient encoding hardware and display excellent error correcting performance. Therefore, they have been accepted into the 5G standards in addition to being potential candidates for next generation mobile systems. However, dominant trapping sets in the Tanner graphs cause some failures for the iterative decoding algorithm. In this letter, we propose a simulated annealing based method to find regular QC-LDPC codes without dominant trapping sets and have good error floor performance. Simulation results show that our proposed method generates QC-LDPC codes that have the best trapping sets distribution among recent works and better frame rate performance than others. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Data Acquisition & Processing / Shu Ju Cai Ji Yu Chu Li is the property of Editorial Department of Journal of Nanjing University of Aeronautics & Astronautics and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Ambient backscatter technology has attracted much attention recently, because it enables battery-free devices, such as tags or sensors, to communicate through wireless energy harvesting and radio backscattering. Existing studies about ambient backscatter assume that the tags have only two states: backscatter or non-backscatter. Actually, some references have shown that the tags can readily realize three states: positive and negative phase backscatter, and non-backscatter. In this paper, we propose a new coding scheme for these tags with three states to improve the throughput of the ambient backscatter communication system. We then design a maximum a posteriori (MAP) detector for the reader to extract binary information from ternary coded signals. We also analyze the detection performance in terms of closed-form bit error rate (BER) expressions. It is found that the proposed coding scheme can improve the throughput of an ambient backscatter system, and there exists an error floor for the BER curve. Finally, simulation results are provided to corroborate our theoretical studies.

In this letter, we propose a new technique to design quasi-cyclic low-density parity-check (QC-LDPC) codes with girth 8 and variable node degrees 3 and 4. Small trapping sets are avoided in the designed codes by imposing simple constraints on the cycles of length 8 in the code’s Tanner graph. We also derive lower bounds on the block length of the codes that can satisfy such constraints. Simulation results are provided to demonstrate the superiority of the designed codes in comparison with similar codes in the literature. [ABSTRACT FROM AUTHOR]

In this paper, the definition of threshold of elementary absorbing sets is extended to scaled Min-Sum low-density parity-check (LDPC) decoding. Based on the analysis of the behavior of scaled Min-Sum LDPC decoders in the Tanner graph of the absorbing set, it is proven that correct decoding is guaranteed with received channel messages above threshold. A fast algorithm for the threshold computation is derived. Many examples of absorbing sets taken from LDPC codes of various variable node degrees are investigated, and it is shown that all of them can be deactivated with low enough scaling factors. [ABSTRACT FROM AUTHOR]

Multilevel flash memories enable multiple bits to be stored in a single memory cell and hence a significant increase of the storage capacity. The multiple bits that are used for labeling the threshold voltage level of a memory cell belong to different pages. A multilevel flash memory channel resembles a multi-user channel with asymmetric noise, while the data of different pages, which are encoded independently, resembles data of multiple users. In this paper, performance analyses are proposed for this channel by using the union bound technique. In particular, we investigated two different binary labeling schemes of a cell level, the Gray labeling and non-Gray labeling with three maximum-likelihood (ML)-based decoding schemes, which are the joint multi-page ML decoding, page-separate ML decoding, and default setting ML decoding. Our analysis reveals an asymptotic diminishing rate of decoding errors as the channel noise approaches zero, based on which the code design criteria are proposed. It is shown theoretically that the Gray mapping has no joint (i.e., multi-page) decoding gain. The corresponding diminishing decoding error rate is dominated by the weakest code in each page and hence a separate decoding scheme is adequate. On the other hand, the non-Gray mapping has a joint decoding gain which means the weak code can exploit the decoding of the strong code and the diminishing rate of its decoding errors is not subject to the cask effect. Therefore, for Gray mapping, a symmetric coding scheme using equal-strength code for each page achieves better error performance, while for non-Gray mapping with joint decoding, the symmetric coding is not necessary. Moreover, by using the asymmetric coding scheme through assigning different code rates to different pages, the non-Gray mapping can achieve higher overall sum rate than Gray mapping with a similar decoding error rate performance. [ABSTRACT FROM AUTHOR]

This paper presents a novel log-likelihood ratio (LLR) calculation for high order coded modulation schemes over an additive white Gaussian noise channel at the presence of residual phase noise (RPN). Residual phase noise is known to significantly degrade the error rate performance of such systems, particularly at lower error rates, resulting in an early error floor. To model RPN, we consider the commonly used pilot symbol assisted modulation schemes for carrier recovery. We derive the exact formula for the calculation of LLR for such systems. To simplify the implementation, we also derive an approximation of LLR which reduces the complexity significantly with almost no loss in performance. The simulation results are presented for coded modulation schemes based on quadrature amplitude modulations and low-density parity-check codes. The simulations demonstrate significant performance improvement in the error rate as a result of using the new LLR calculation instead of the conventional calculation of LLR which ignores the RPN. [ABSTRACT FROM AUTHOR]

Cages, defined as regular graphs with minimum number of nodes for a given girth, are well-studied in graph theory. Trapping sets are graphical structures responsible for error floor of low-density parity-check (LDPC) codes, and are well investigated in coding theory. In this paper, we make connections between cages and trapping sets. In particular, starting from a cage (or a modified cage), we construct a trapping set in multiple steps. Based on the connection between cages and trapping sets, we then use the available results in graph theory on cages and derive tight upper bounds on the size of the smallest trapping sets for variable-regular LDPC codes with a given variable degree and girth. The derived upper bounds in many cases meet the best known lower bounds and thus provide the actual size of the smallest trapping sets. Considering that non-zero codewords are a special case of trapping sets, we also derive tight upper bounds on the minimum weight of such codewords, i.e., the minimum distance, of variable-regular LDPC codes as a function of variable degree and girth. [ABSTRACT FROM AUTHOR]

Non-binary (NB) low-density parity-check (LDPC) codes are graph-based codes that are increasingly being considered as a powerful error correction tool for modern dense storage devices. Optimizing NB-LDPC codes to overcome their error floor is one of the main code design challenges facing storage engineers upon deploying such codes in practice. Furthermore, the increasing levels of asymmetry incorporated by the channels underlying modern dense storage systems, e.g., multi-level Flash systems, exacerbate the error floor problem by widening the spectrum of problematic objects that contribute to the error floor of an NB-LDPC code. In a recent research, the weight consistency matrix (WCM) framework was introduced as an effective combinatorial NB-LDPC code optimization methodology that is suitable for modern Flash memory and magnetic recording (MR) systems. The WCM framework was used to optimize codes for asymmetric Flash channels, MR channels that have intrinsic memory, in addition to canonical symmetric additive white Gaussian noise channels. In this paper, we provide an in-depth theoretical analysis needed to understand and properly apply the WCM framework. We focus on general absorbing sets of type two (GASTs) as the detrimental objects of interest. In particular, we introduce a novel tree representation of a GAST called the unlabeled GAST tree, using which we prove that the WCM framework is optimal in the sense that it operates on the minimum number of matrices, which are the WCMs, to remove a GAST. Then, we enumerate WCMs and demonstrate the significance of the savings achieved by the WCM framework in the number of matrices processed to remove a GAST. Moreover, we provide a linear-algebraic analysis of the null spaces of WCMs associated with a GAST. We derive the minimum number of edge weight changes needed to remove a GAST via its WCMs, along with how to choose these changes. In addition, we propose a new set of problematic objects, namely oscillating sets of type two (OSTs), which contribute to the error floor of NB-LDPC codes with even column weights on asymmetric channels, and we show how to customize the WCM framework to remove OSTs. We also extend the domain of the WCM framework applications by demonstrating its benefits in optimizing column weight 5 codes, codes used over Flash channels with additional soft information, and spatially coupled codes. The performance gains achieved via the WCM framework range between 1 and nearly 2.5 orders of magnitude in the error floor region over interesting channels. [ABSTRACT FROM AUTHOR]

A Gilbert–Elliott channel for symbol errors is considered to analyze the performance of interleaved error correction codes with a fixed block size in the presence of burst errors. The proposed channel model for symbol errors is based on a simplified Gilbert channel for bit errors, which enables direct comparisons of the performance of block codes with different symbol sizes. The autocorrelation function between two erroneous symbols within an interleaved codeword is computed. An exact expression for the codeword-error probability is derived from the symbol-based channel model. A tight lower bound on the codeword-error probability and error floors, which are observed when the average raw bit-error rate is low, are analyzed using the bit-based channel model. [ABSTRACT FROM AUTHOR]

Staircase codes play an important role as error-correcting codes in optical communications. In this paper, a low-complexity method for resolving stall patterns when decoding staircase codes is described. Stall patterns are the dominating contributor to the error floor in the original decoding method. Our improvement is based on locating stall patterns by intersecting non-zero syndromes and flipping the corresponding bits. The approach effectively lowers the error floor and allows for a new range of block sizes to be considered for optical communications at a certain code rate or, alternatively, a significantly decreased error floor for the same block size. Further, an improved error floor analysis is introduced which provides a more accurate estimation of the contributions to the error floor. [ABSTRACT FROM AUTHOR]

In this paper, we propose a characterization for non-elementary trapping sets (NETSs) of low-density parity-check (LDPC) codes. The characterization is based on viewing an NETS as a hierarchy of embedded graphs starting from an ETS. The characterization corresponds to an efficient search algorithm that under certain conditions is exhaustive. As an application of the proposed characterization/search, we obtain lower and upper bounds on the stopping distance $s_{\min }$ of LDPC codes. We examine a large number of regular and irregular LDPC codes and demonstrate the efficiency and versatility of our technique in finding lower and upper bounds on, and in many cases the exact value of, $s_{\min }$. Finding $s_{\min }$ , or establishing search-based lower or upper bounds, for many of the examined codes are out of the reach of any existing algorithm. For a constant degree distribution and range of search, the worst case computational complexity of the proposed search algorithms for finding NETSs and stopping sets is linear in the code’s block length $n$. The average search complexity for stopping sets, however, is constant in $n$ , if the simple cycles required as input to the search algorithm are available. [ABSTRACT FROM AUTHOR]

Spatially-coupled (SC) codes are a family of graph-based codes that have attracted significant attention, thanks to their capacity approaching performance and low decoding latency. An SC code is constructed by partitioning an underlying block code into a number of components and coupling their copies together. In this paper, we first introduce a general approach for the enumeration of detrimental combinatorial objects in the graph of finite-length SC codes. Our approach is general in the sense that it effectively works for SC codes with various partitioning schemes, column weights, and memories. Next, we present a two-stage framework for the construction of high performance binary SC codes optimized for the additive white Gaussian noise channels; we aim at minimizing the number of detrimental combinatorial objects in the error floor region. In the first stage, we deploy a novel partitioning scheme, called the optimal overlap partitioning, to produce the optimal partitioning corresponding to the smallest number of detrimental objects. In the second stage, we apply a new circulant power optimizer to further reduce the number of detrimental objects in the lifted graph. SC codes constructed by our new framework have up to two orders of magnitude error floor performance improvement and up to 0.6 dB SNR gain compared to prior state-of-the-art SC codes. [ABSTRACT FROM AUTHOR]

Forward error correction (FEC) performance down to 10−15 bit error rate (BER) of a concatenated staircase and Hamming code (CSHC), which was recently proposed for the first 400G inter-data center interconnect standard, is verified with a 50-piece field-programmable gate array (FPGA) implementation at a record 200-Gb/s throughput. The effect of digital noise tail accuracy on the FEC emulation results is investigated. A converging criterion is proposed and demonstrated for achieving high confidence in artificial digital-noise-source-based FPGA emulations. The CSHC performance as a function of decoding iterations of the outer staircase code is investigated, and emulation results show that six staircase decoding iterations is the optimal choice. The FPGA emulations also reveal the existence of an error flare of the CSHC at 10−10 BER, which corrects the predicted BER threshold from 1.25 × 10−2 to 1.21 × 10−2. Further investigations on the effects of interleaving processes and staircase decoding buffer size show that the error flare behavior of the CSHC depends on the decoding buffer size of the outer staircase code. To remove the CSHC error flare, a proper choice of the staircase decoding buffer size is shown to be 6, which also moves the FEC threshold to 1.27 × 10−2. [ABSTRACT FROM AUTHOR]

In this paper, we propose novel terminated staircase codes for NAND flash memories. Specifically, we design a rate 0.89 staircase code whose component code is a Bose–Chaudhuri–Hocquenghem (BCH) code, for flash memories with page size of 16K bytes. Different from most conventional unterminated staircase codes, we propose a novel coding structure by performing cyclic redundancy check (CRC) encoding and decoding on each component codeword including information bits and parity bits. The CRC bits are protected by both row and column codewords. Furthermore, a novel iterative bit flipping algorithm is developed to solve stall patterns and lower the error floor. Based on our design, we perform an improved analysis on the error floor. We prove and show that our proposed decoding algorithm can solve more stall patterns which leads to a lower error floor compared with conventional staircase codes. Numerical results show that our terminated staircase codes outperform the stand-alone BCH codes and the conventional staircase codes. [ABSTRACT FROM AUTHOR]

Short cycles in a nonbinary low-density parity-check (NB-LDPC) code may be even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is important to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles. Finally, we propose a low-complexity algorithm for designing an NB-LDPC code with low error floor. Depending on the modulation scheme, the codes constructed by the proposed design algorithm have similar or slightly worse performance, compared with those constructed via the method by Poulliatet al.However, the proposed design algorithm does not require a cycle enumeration algorithm with high complexity, and therefore is feasible even in the case of large code length, say ${\geq}5000$. [ABSTRACT FROM AUTHOR]

In magnetic recording systems, consecutive sections experience different signal-to-noise ratios (SNRs). To perform error correction over these systems, one approach is to use an individual block code for each section. However, the performance over a section affected by a lower SNR is weaker compared to the performance over a section affected by a higher SNR. Spatially-coupled (SC) codes are a family of graph-based codes with capacity approaching performance and low latency decoding. An SC code is constructed by partitioning an underlying block code to several component matrices, and coupling copies of the component matrices together. The contribution of this paper is threefold. First, we present a new partitioning technique to efficiently construct SC codes with column weights 4 and 6. Second, we present an SC code construction for channels with SNR variation. Our SC code construction provides local error correction for each section by means of the underlying codes that cover one section each, and simultaneously, an added level of error correction by means of coupling among the underlying codes. Third, we introduce a low-complexity interleaving scheme specific to SC codes that further improves their performance over channels with SNR variation. Our simulation results show that our SC codes outperform individual block codes by more than one and two orders of magnitudes in the error floor region compared to the block codes with and without regular interleaving, respectively. This improvement is more pronounced by increasing the memory and column weight. [ABSTRACT FROM AUTHOR]

This letter presents a low-complexity redecoding-based error-floor lowering technique for quasi-cyclic low-density parity-check codes, where a predetermined set of variable nodes are attenuated before the redecoding. Using a two-stage off-line search, the attenuation set is determined based on the error patterns collected from the standard decoding simulation. It is shown that the error floor can be effectively lowered, and only a negligible amount of complexity is introduced. [ABSTRACT FROM AUTHOR]

In this paper, two new methods to construct low-density parity-check (LDPC) codes with low error floor and large girth are proposed. The first one is APPS-LDPC codes based on Arithmetic Progression theory and cycle classification, whose girth is at least eight. Based on the designed APPS-LDPC codes, we further construct Bi-diagonal APPS-LDPC codes with column degree 4, whose circulant permutation matrix is combined by two shifted identity matrix. The designed APPS-LDPC code has 0.25 and 0.2 dB coding gain compared to partition-and-shift (PS)-LDPC code and progressive-edge-growth (PEG)-LDPC code. And the Bi-APPS-LDPC code has similar performance to T2 LDPC code in CCSDS standard, but its effective structure is more suitable for high throughput decoder implementation on FPGA. Both codes have less construction complexity than PS-LDPC code and PEG-LDPC code. [ABSTRACT FROM AUTHOR]

In this paper, we propose a characterization of elementary trapping sets (ETSs) for irregular low-density parity-check (LDPC) codes. These sets are known to be the main culprits in the error floor region of such codes. The characterization of ETSs for irregular codes has been known to be a challenging problem due to the large variety of non-isomorphic ETS structures that can exist within the Tanner graph of these codes. This is a direct consequence of the variety of the degrees of the variable nodes that can participate in such structures. The proposed characterization is based on a hierarchical graphical representation of ETSs, starting from simple cycles of the graph, or from single variable nodes, and involves three simple expansion techniques: degree-one tree ( dot ), path , and lollipop , thus, the terminology dpl characterization. A similar dpl characterization was proposed in an earlier work by the authors for the leafless ETSs of variable–regular LDPC codes. The present paper generalizes the prior work to codes with a variety of variable node degrees and to ETSs that are not leafless. The proposed dpl characterization corresponds to an efficient search algorithm that, for a given irregular LDPC code, can find all the instances of (a, b) ETSs with size a and b \leq b\max , exhaustively. Although branch-&-bound exhaustive search algorithms for finding ETSs of irregular LDPC codes exist, to the best of our knowledge, the proposed search algorithm is the first of its kind, in that, it is devised based on a characterization of ETSs that makes the search process efficient. For a constant degree distribution and range of search, the worst-case complexity of the proposed dpl algorithm increases linearly with the block length $n$ . The average complexity, excluding the search for the input simple cycles, is constant in $n$ . Extensive simulation results are presented to show the versatility of the search algorithm, and to demonstrate that, compared to the literature, significant improvement in search speed can be obtained. [ABSTRACT FROM PUBLISHER]

Under the signal model of differential modulation and demodulation, two multi-antenna diversity receptions (linear combiner and statistic combiner) were proposed, and then the effective diversity reception scheme of train-to-ground wireless broadband communication for high-speed railway scenarios was concluded. Mathematical analysis and simulation results indicate that by increasing the diversity number, the proposals can reduce the error floor because of high mobility. The performance of linear combiner is much better than that of statistic combiner, but the re-ceiver complexity of linear combiner is also higher than that of statistic combiner. In term of practical application, the tradeoff between performance and complexity must be made according to the quality of service (QoS) requirements.