41 results on '"Everaert, J. -L."'
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2. Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology
3. Effectiveness of nitridation of hafnium silicate dielectrics: a comparison between thermal and plasma nitridation
4. Monitoring plasma nitridation of HfSiO x by corona charge measurements
5. Selective epitaxial p-SiGe Source-Drain Contacts: Low Contact Resistivity (1.5x10-9 ohm.cm2) by Optimizing Strain and Doping Concentration
6. Integration of SrBi2Ta2O9 thin films for high density ferroelectric random access memory.
7. Integration of SrBi2Ta2O9 thin films for high density ferroelectric random access memory
8. Comprehensive study of Ga activation in Si, SiGe and Ge with 5 × 10−10 Ω·cm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation
9. Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation
10. Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?
11. Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory
12. Noncontact metrology for inversion charge carrier mobility by corona charge and photovoltage measurements on blank wafers with a gate dielectric
13. Contactless mobility measurements of inversion charge carriers on silicon substrates with SiO2 and HfO2 gate dielectrics
14. Vapor phase doping and sub-melt laser anneal for the fabrication of Si-based ultra-shallow junctions in sub-32 nm CMOS technology
15. Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology
16. Fundamental study on the impact of C co-implantation on ultra shallow B juntions
17. Control of laser induced interface traps with in-line corona charge metrology
18. Use of Corona Charge Photo-Conductance Decay (Charge-PCD) for fast metal contamination monitoring of high temperature processes
19. Probing doping conformality in fin shaped field effect transistor structures using resistors
20. Basic Aspects of the Formation and Activation of Boron Junctions Using Plasma Immersion Ion Implantation.
21. Conformal Doping of FINFETs: a Fabrication and Metrology Challenge
22. Monitoring plasma nitridation of HfSiOx by corona charge measurements
23. The Application of an Ultrathin ALD HfSiON Cap Layer on SiON Dielectrics for Ni-FUSI CMOS Technology Targeting at Low-Power Applications
24. Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT
25. Wet Etch Characteristics of Hafnium Silicate Layers
26. Plasma-nitrided silicon-rich oxide as an extension to ultrathin nitrided oxide gate dielectrics
27. Integration of MOCVD SBT Stacked Ferroelectric Capacitors in a 0.35 μ m CMOS Technology
28. Spacers Alternatives for INTEGRATION OF (3D) STACKED SBT FeCAP s
29. Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications.
30. SiON Gate Dielectric Formation by Rapid Thermal Oxidation of Nitrided Si.
31. 45 nm nMOSFET with metal gate on thin SiON driving 1150 μA/μm and off-state of 10nA/μm.
32. A ballistic electron emission microscopy (BEEM) study of the barrier height change of Au/n-GaAs Schottky contacts due to mechanical polishing
33. Monitoring plasma nitridation of HfSiOx by corona charge measurements
34. Instrumental Method for Quantitative Evaluation of Cell or Particle Adhesion, Based on Transport Measurements in Capillary Flow.
35. Characterisation of CoSi2/- and TiSi2/n-GaAs Schottky barriers
36. Integration of MOCVD SBT Stacked Ferroelectric Capacitors in a 0.35 μm CMOS Technology.
37. Mass Metrology for controlling and understanding processes.
38. Contactless mobility measurements of inversion charge carriers on silicon substrates with SiO2 and HfO2 gate dielectrics.
39. Quantitative prediction of acceptor concentration reduction in boron doped silicon due to electron irradiation
40. 45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μ
41. Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology.
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