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Coherent Ising Machine (CIM) is a network of optical parametric oscillators that solve combinatorial optimization problems by finding the ground state of an Ising Hamiltonian. In CIMs, a problem arises when attempting to realize the Zeeman term because of the mismatch in size between interaction and Zeeman terms due to the variable amplitude of the optical parametric oscillator pulses corresponding to spins. There have been three approaches proposed so far to address this problem for CIM, including the absolute mean amplitude method, the auxiliary spin method, and the chaotic amplitude control (CAC) method. This paper focuses on the efficient implementation of Zeeman terms within the mean-field CIM model, which is a physics-inspired heuristic solver without quantum noise. With the mean-field model, computation is easier than with more physically accurate models, which makes it suitable for implementation in field programmable gate arrays and large-scale simulations. First, we examined the performance of the mean-field CIM model for realizing the Zeeman term with the CAC method, as well as their performance when compared to a more physically accurate model. Next, we compared the CAC method to other Zeeman term realization techniques on the mean-field model and a more physically accurate model. In both models, the CAC method outperformed the other methods while retaining similar performance. [ABSTRACT FROM AUTHOR]

In this paper, we design and analysis of mean filter using field programmable gate arrays (FPGAs) for digital images, FPGAs are integrated circuits consisting of interconnections that connect programmable internal hardware blocks allows users to customize operations for a specific application. FPGA is an ideal choice for real-time image processing, these FPGA devices are controlled in Verilog or VHDL languages, allowing to design at different levels and adapt to design changes or even support new applications throughout the life of the component. Digital image filtering is the most important task in image processing and with the help of computers, image recognition involves identifying and classifying objects in an image. This paper design of mean filter for digital image processing, implementation and analysis of image processing algorithms on FPGAs. The results obtained on the FPGA are compared and analyzed with the results by MATLAB software. [ABSTRACT FROM AUTHOR]

Traditional methods for identifying "hit" molecules from a large collection of potential drug-like candidates rely on biophysical theory to compute approximations to the Gibbs free energy of the binding interaction between the drug and its protein target. These approaches have a significant limitation in that they require exceptional computing capabilities for even relatively small collections of molecules. Increasingly large and complex state-of-the-art deep learning approaches have gained popularity with the promise to improve the productivity of drug design, notorious for its numerous failures. However, as deep learning models increase in their size and complexity, their acceleration at the hardware level becomes more challenging. Hyperdimensional Computing (HDC) has recently gained attention in the computer hardware community due to its algorithmic simplicity relative to deep learning approaches. The HDC learning paradigm, which represents data with high-dimension binary vectors, allows the use of low-precision binary vector arithmetic to create models of the data that can be learned without the need for the gradient-based optimization required in many conventional machine learning and deep learning methods. This algorithmic simplicity allows for acceleration in hardware that has been previously demonstrated in a range of application areas (computer vision, bioinformatics, mass spectrometery, remote sensing, edge devices, etc.). To the best of our knowledge, our work is the first to consider HDC for the task of fast and efficient screening of modern drug-like compound libraries. We also propose the first HDC graph-based encoding methods for molecular data, demonstrating consistent and substantial improvement over previous work. We compare our approaches to alternative approaches on the well-studied MoleculeNet dataset and the recently proposed LIT-PCBA dataset derived from high quality PubChem assays. We demonstrate our methods on multiple target hardware platforms, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), showing at least an order of magnitude improvement in energy efficiency versus even our smallest neural network baseline model with a single hidden layer. Our work thus motivates further investigation into molecular representation learning to develop ultra-efficient pre-screening tools. We make our code publicly available at https://github.com/LLNL/hdbind. [ABSTRACT FROM AUTHOR]

Image Compression is one of the emerging techniques of a Digital System for storing and retrieving of digital information. The main challenge in implementing Image Compression is to maintain the accuracy of the retrieved data. As the encoding techniques used for data compression are computationally intensive, new hardware architectures are required so that the processing of image consumes less space with increase in computation speed, reduction in area and power consumption. In this paper we address this problem and developed a Dynamic Adaptive coding technique based on probability of occurrence,where the variable and fixed length code are fused to generate a code word for eliminating the extra bit encountered at the entropy coder. Here the Entropy code has a maximum search overhead of 6 match per 4-bit pattern. Wherein a maximum of 5-bit search is observed in proposed approach. This reduces a search overhead of (N⨉m)-1 iterations. Here N is the number of unique patterns and m is the block size. The proposed architecture is developed using Very high speed integrated circuit Hardware Descriptive Language (VHDL) and implemented using Xilinx Aldec's Field Programmable Gate Array (FPGA). The adaptive coding approach attains a compression of 35% more as compared to the entropy coding. The implementation on to a targeted Xilinx FPGA results in power minimization and area coverage reduction. The speed of operation is observed to be improved by 135 MHz. The validation of proposed approach is made on image data to observe the coding accuracy. The mean square error of the output image is reduced by 35% with an increase in the signal to noise ratio of the output image. [ABSTRACT FROM AUTHOR]

Modular Multiplication (MM) plays a crucial role in public key cryptography and random numbers generation. Montgomery Modular Multiplication (MMM) Algorithm is the most popular method used for performing this operation. Currently, there are various Field Programmable Gate Array (FPGA)-based optimizations targeting the MMM implementation. However, many of these works suffer from complex critical path where multiplications and carry propagate additions are calculated at each clock cycle. This leads to a low computation throughput and limited frequency. This paper presents an efficient FPGA implementation of the MMM algorithm using compressors-4:2 (Comp-4:2s). Our objective is to realize a Hardware (HW) architecture which presents a best trade-off between computation throughput and occupied area. The execution performances of the MMM depend on both parameters: the radix-r and the modulus size. In fact, when the radix increases, the algorithm requires multiplications of form digits×operands. On the other hand, when a long modulus is used, the HW implementation of the MMM needs long carry propagation paths. In this work we propose an approach to circumvent the required multiplications by decomposing the digits into coefficients powers of 2. Then, the multiplications are carried out by simple shifts and additions. The Carry Save Adders (CSAs) are employed to avoid the use of long carry chains. However, the combination of CSAs and the used radixes requires four-input adders. Our implementation is based on using the Comp-4:2s for the realization of regular CSAs structures. The challenge consists in the development of an optimized Comp-4:2 which must be completely integrated in single FPGA Slice. Our implementation solution allows the achievement of high computation throughput. The obtained critical path delay is independent of the operand size. The implementation on Virtex-7 circuit using a modulus of 1024-bit size shows that the MMM run in 1.31 and requires 2342 Slices. [ABSTRACT FROM AUTHOR]

Multi-sensor information fusion (MSIF) technology based on deep convolutional neural networks (CNN) has been widely used in UAV obstacle avoidance. However, detection efficiency needs to be improved in practice because of its high computational complexity and limited airborne hardware resources. A lightweight CNN-based fast detection method based on the fusion of millimeter-wave (MMW) radar and camera is proposed in this paper. In the data preprocessing stage, the input images to the network were preprocessed based on the radar and image data. A rough detection algorithm calculates and segments the saliency image to obtain regions of interest (ROI). The computational complexity of the network training and prediction was reduced by setting the image pixels outside the ROI. In the detection stage based on deep learning, a lightweight network structure based on ResNet18 was designed to fuse the saliency images at different convolution depths. In the post-decoding stage, the calibration points are fused for local non-maximum suppression (NMS). In contrast to typical detection methods, the proposed method improves the detection speed by removing redundant pixels and local NMS, increasing the detection accuracy by fusing the feature information of the radar and camera in multiple stages. The experimental results indicate that compared with the latest lightweight network (YOLOv8n), the detection accuracy is increased by 10.51%, and the FPS increased by 44.43%. Compared with the latest YOLOv8s and YOLOv9m models, the FPS is increased by 3.0X-4.4X. The field programmable gate array (FPGA) implementation achieves a performance of 60.0 FPS. This is an improvement compared with typical methods, demonstrating that the proposed method is more effective than state-of-the-art models. [ABSTRACT FROM AUTHOR]

Dual active bridge (DAB) is an isolated DC‐DC converter gaining wider attention in power electronics applications. The high frequency (HF) transformer is an integral part of the DAB which is prone to saturation. Silicon carbide (SiC) based DAB are generally preferred for highly efficient power conversions, calling for an extremely low DC resistance of the transformer. This aggravates the DC bias issue significantly. The DC bias current generally flows due to the mismatch in static and transient switching of active devices, leading to eventual saturation of the transformer. This paper proposes an active method to precisely control the dead time of the devices (8–100 ns) without sacrificing the voltage utilization of the converter. This method does not require a sophisticated DC offset current measurement technique. The field programmable gate array (FPGA) based control platform on the gate driver side executes the proposed algorithm. The proposed control is experimentally verified in a 5 kW SiC based converter. The control implementation methodology is discussed with the support of necessary experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a three-dimensional Jerk chaotic system with saddle-focus equilibrium point and special rotational characteristics of attractors is proposed by constructing a three-dimensional chaotic system. Based on the three-dimensional Jerk chaotic system, a four-dimensional chaotic system based on the sign function and cosine function is proposed. Through detailed numerical simulations and theoretical analysis, we induce and control the emergence of multi-vortex structures in the system by adjusting system parameters, thereby influencing the overall dynamic characteristics of the system. The dynamical behavior of the system is analyzed using the 0–1 test, attractor coexistence, multiple bifurcations, two-parameter Lyapunov exponent, and complexity. It is found that the new four-dimensional chaotic system has the properties of multi-stability, transient chaos and offset enhancement. The circuit of this chaotic system was designed and simulated, and the digital circuit was implemented using field programmable gate array. The consistency between the simulation and implementation results proves the existence and feasibility of the system. Finally, based on the adaptive synchronization control algorithm, the system is applied to secure communication synchronization and the analysis confirms the superiority of the adaptive synchronization strategy, while enhancing the system's ability to cope with external variations and demonstrating that it has a wide range of applications in various fields. [ABSTRACT FROM AUTHOR]

Human studies often rely on wearable lifelogging cameras that capture videos of individuals and their surroundings to aid in visual confirmation or recollection of daily activities like eating, drinking, and smoking. However, this may include private or sensitive information that may cause some users to refrain from using such monitoring devices. Also, short battery lifetime and large form factors reduce applicability for long-term capture of human activity. Solving this triad of interconnected problems is challenging due to wearable embedded systems' energy, memory, and computing constraints. Inspired by this critical use case and the unique design problem, we developed NIR-sighted, an architecture for wearable video cameras that navigates this design space via three key ideas: (i) reduce storage and enhance privacy by discarding masked pixels and frames, (ii) enable programmers to generate effective masks with low computational overhead, and (iii) enable the use of small MCUs by moving masking and compression off-chip. Combined together in an end-to-end system, NIR-sighted's masking capabilities and off-chip compression hardware shrinks systems, stores less data, and enables programmer-defined obfuscation to yield privacy enhancement. The user's privacy is enhanced significantly as nowhere in the pipeline is any part of the image stored before it is obfuscated. We design a wearable camera called NIR-sightedCam based on this architecture; it is compact and can record IR and grayscale video at 16 and 20+ fps, respectively, for 26 hours nonstop (59 hours with IR disabled) at a fraction of comparable platforms power draw. NIR-sightedCam includes a low-power Field Programmable Gate Array that implements our mJPEG compress/obfuscate hardware, Blindspot. We additionally show the potential for privacy-enhancing function and clinical utility via an in-lab eating study, validated by a nutritionist. [ABSTRACT FROM AUTHOR]

The technique of sampling rate conversion is frequently employed in various fields. A discrete time-varying filter, as well as a sample skip or sample duplicate operation, are required for the most general instance of an irrational and time-variable conversion factor. A wide band of signals is employed in a communication system, especially in specific situations where data must be transferred directly. A broadband sample rate converter with changeable filter parameters is necessary in such cases. Sample rate conversion is a communication system technology that accepts a band-limited high sample rate modulated signal and uses filtering to retrieve the original message signal. In this work, an energy-efficient implementation of a reconfigurable field programmable gate arrays (FPGA) architecture for a sample rate converter is proposed. In applications such as multi-rate signal processing and the construction of channelized receivers, sample rate conversion is used. In this work, a new FPGA based design is proposed to perform multiple sample rate conversion for various data transmission protocols such as Wi-Fi, ZigBee and Bluetooth. A lowpass filter with a 2.45 GHz filter with the minimum number of taps is used to avoid the aliasing effect. Xilinx synthesis tools are used to estimate hardware resource utilization and speed analyses. XC6VCX240t-2FF484 FPGA achieves 15% hardware resource occupancy at a maximum clock speed of 133 MHz. [ABSTRACT FROM AUTHOR]

A Field Programmable Gate Array (FPGA) is a semiconductor device based around a Configurable Logic Blocks (CLB) matrix connected by programmable interconnects. FPGA has numerous applications in biomedical signal processing due to its flexible programming and low power consumption. An Electrocardiogram (ECG) is a medical test used to determine heart rates, cardiac activity, and classify arrhythmias. All pass filters have Low Pass Filter (LPF), High Pass Filter (HPF), Band Stop Filter (BSF), and Band Pass Filter (BPF) to produce the exact amplitude in peak detection. However, the separate coefficient for individual filters increases the area in traditional all-pass filters. To overcome this issue, a Reconfigurable All-Pass Filter (RAPF) which considers a single coefficient for all filters and minimizes memory usage, consuming less area and power is employed. The LPF coefficient is utilized to perform the LPF operation, and then the two's complement of this LPF coefficient is computed to produce the HPF coefficient. Next, the two's complement is fed into the Hilbert Transform (HT) to produce the BSF coefficient and determine BSF operations. A RAPF is designed to perform these operations effectively. The RAPF performance is determined using Register, Look Up Table (LUT), Global Buffer (BUFG), Digital Signal Processing (DSP), Power, and Flip Flop (FF). RAPF consumes lesser power of 34 mW for Artix 7 XC7A200TFBG676-2 FPGA device, as opposed to the existing technique, Single Node Reservoir Computing (SNRC) using cumulative mean filter. [ABSTRACT FROM AUTHOR]

Biometric security has been developed in recent years with the emergence of cancellable biometric concepts. The idea of the cancellable biometric traits is concerned with creating encrypted or distorted traits of the original ones to protect them from hacking techniques. So, encrypted or distorted biometric traits are stored in databases instead of the original ones. This can be accomplished through non-invertible transforms or encryption schemes. In this paper, a cancellable face recognition algorithm is introduced based on face image encryption through a fractional-order multi-scroll chaotic system. The fundamental concept is to create random keys that will be XORed with the three components of color face images (red, green, and blue) to obtain encrypted face images. These random keys are generated from the Least Significant Bits of all state variables of a proposed fractional-order multi-scroll chaotic system. Lastly, the encrypted color components of face images are combined to produce a single cancellable trait for each color face image. The results of encryption with the proposed system are full-encrypted face images that are suitable for cancellable biometric applications. The strength of the proposed system is that it is extremely sensitive to the user's selected initial conditions. The numerical simulation of the proposed chaotic system is done with MATLAB. Phase and bifurcation diagrams are used to analyze the dynamic performance of the proposed fractional-order multi-scroll chaotic system. Furthermore, we realized the hardware circuit of the proposed chaotic system on the PSpice simulator. The proposed chaotic system can be implemented on Field Programmable Gate Arrays (FPGAs). To model our generator, we can use Verilog Hardware Description Language HDL, Xilinx ISE 14.7 and Xilinx FPGA Artix-7 XC7A100T based on Grunwald-Letnikov algorithms for mathematical analysis. The numerical simulation, the circuit simulation and the hardware experimental results confirm each other. Cancellable face recognition based on the proposed fractional-order chaotic system has been implemented on FERET, LFW, and ORL datasets, and the results are compared with those of other schemes. Some evaluation metrics containing Equal Error Rate (EER), and Area under the Receiver Operating Characteristic (AROC) curve are used to assess the cancellable biometric system. The numerical results of these metrics show EER levels close to zero and AROC values of 100%. In addition, the encryption scheme is highly efficient. [ABSTRACT FROM AUTHOR]

The integrated "perception‐memory" system is receiving increasing attention due to its crucial applications in humanoid robots, as well as in the simulation of the human retina and brain. Here, a Field Programmable Gate Array (FPGA) platform‐boosted system that enables the sensing, recognition, and memory for human‐computer interaction is reported by the combination of ultra‐thin Ag/Al/Paster‐based electronic tattoos (AAP) and Tantalum Oxide/Indium Gallium Zinc Oxide (Ta2O5/IGZO)‐based memristors. Notably, the AAP demonstrates exceptional capabilities in accommodating the strain caused by skin deformation, thanks to its unique structural design, which ensures a secure fit to the skin and enables the prolonged monitoring of physiological signals. By utilizing Ta2O5/IGZO as the functional layer, a high switching ratio is conferred to the memristor, and an integrated system for sensing, distinguishing, storing, and controlling the machine hand of multiple human physiological signals is constructed together with the AAP. Further, the proposed system implements emergency calls and smart homes using facial electromyogram signals and utilizing logical entailment to realize the control of the music interface. This innovative "perception‐memory" integrated system not only serves the disabled, enhancing human‐computer interaction but also provides an alternative avenue to enhance the quality of life and autonomy of individuals with disabilities. [ABSTRACT FROM AUTHOR]

Hearing loss sufferers might struggle in noisy environments. A new hearing aid system with noise-reducing filters can improve communication even in a noisy environment. However, current filters drain battery life, have matching errors, and are computationally expensive. Additionally, traditional filter banks have limitations. This paper proposes a novel Wolf-based Fractional Delay Variable Bandwidth Filter (W-FDVBF) to address these issues. The W-FDVBF aims to suppress background noise while optimizing factors like power consumption and computational complexity for a better user experience. Wolf optimization function helps to adjust filter parameters for robust noise reduction, leading to lower power usage, reduced matching errors, and less computational burden. The performance of the designed filter bank is tested in MATLAB and Xilinx software with the Field Programmable Gate Array (FPGA) accelerator. Finally, the obtained results are compared with other existing approaches and have gained better outcomes by attaining less power and matching error. The model achieved a 1.76 matching error and 1.4W power consumption, which is lower than other methods. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) technology is one of the nanotechnologies which attracted a great deal of consideration because of features like the speed of the circuit, low-power utilization and small size. In digital electronics, the comparator plays a vital role, due to its vast area of applications like state machine design, digital testing and fault tolerance, digital control systems, etc. This paper proposes a 4-bit/8-bit/16-bit comparator in QCA technology using the XOR Gate. The proposed method is an efficient method, which has two stages: finding whether the inputs are equal or not in stage 1 and less than or greater than in stage 2 using an XOR gate. The proposed comparator circuits have less area and cost with less delay as compared to the previous works. The proposed energy calculations are carried out with the QCA DesignerE tool, and it is observed that the proposed structures are energy efficient. In addition, the proposed comparators are simulated and synthesized with Vivado design suite 2021.1 and implemented on the Virtex UltraScale VCU129-PP FPGA board. [ABSTRACT FROM AUTHOR]

In the cigarette manufacturing industry, machine vision and artificial intelligence algorithms have been employed to improve production efficiency by detecting product defects. However, achieving both high accuracy and real-time defect detection for cigarettes with complex patterns remains a challenge. To address these issues, this study proposes a model based on RESNET18, combined with a feature enhancement algorithm, to improve detection accuracy. Additionally, a method is designed to deploy the model on a field-programmable gate array (FPGA) with high parallel processing capabilities to achieve high-speed detection. Experimental results demonstrate that the proposed detection model achieves a detection accuracy of 95.88% on a cigarette filter defect dataset with an end-to-end detection speed of only 9.38 ms. [ABSTRACT FROM AUTHOR]

The eigen-decomposition of a covariance matrix is a key step in the Direction of Arrival (DOA) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance. Addressing the high complexity and resource consumption of the traditional parallel Jacobi algorithm implemented on FPGA, this study proposes an improved FPGA-based parallel Jacobi algorithm for eigen-decomposition. By analyzing the relationship between angle calculation and rotation during the Jacobi algorithm decomposition process, leveraging parallelism in the data processing, and based on the concepts of time-division multiplexing and parallel partition processing, this approach effectively reduces FPGA resource consumption. The improved parallel Jacobi algorithm is then applied to the classic DOA estimation algorithm, the MUSIC algorithm, and implemented on Xilinx's Zynq FPGA. Experimental results demonstrate that this parallel approach can reduce resource consumption by approximately 75% compared to the traditional method but introduces little additional time consumption. The proposed method in this paper will solve the problem of great hardware consumption of eigen-decomposition based on FPGA in DOA applications. [ABSTRACT FROM AUTHOR]

This work presents the development of an embedded platform using Field Programmable Gate Arrays (FPGAs) for real-time simulation of dynamic systems in industrial plants. The platform, Real-Time Simulator for Dynamic Systems in FPGA (RTSDS-FPGA), is designed for industrial and academic applications. In industrial contexts, the RTSDS-FPGA facilitates the optimization and tuning of embedded control algorithms, while in academia, it supports research on new embedded solutions in automation and control. It is also an educational tool for undergraduate and postgraduate students developing embedded control system projects. Additionally, the simulator accelerates the simulation of slow dynamic systems, significantly reducing overall simulation time. Experimental results demonstrate the platform's capability to perform real-time simulations effectively, validating its accuracy and performance through comparative analyses with established software tools such as Matlab/Simulink. [ABSTRACT FROM AUTHOR]

Summary: The growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data, make it more important to keep secret keys safe and secure. A few major issues of secret keys, like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and nondestruction of keys can compromise the whole security system severely. In this work, we propose a field programmable gate array (FPGA)‐based trusted platform module (TPM) framework for operating system companies and OS users, utilizing blockchain to address NIST‐recommended secret key management issues. The security processor used in OS user machines is partitioned into three areas such that processor area, confidential area, and crypto area. The isolated secret key memory in confidential area, along with a private blockchain (BC) can log the life cycle of secret keys of TPM standard. We have also implemented a special custom bus interconnect, which receives custom crypto instructions from Processing Element (PE). During the execution of crypto instructions, the architecture ensures that secret keys are present in confidential area and crypto area but never in the processor area. The movements of secret keys between confidential area, and crypto area are recorded cryptographically after the proper authentication process controlled by the proposed hardware‐based private BC framework. To the best of our knowledge, this work is the first attempt to implement a blockchain‐based framework between OS company and OS users to address NIST recommended secret key management issues of TPM standard hardware environment. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is nominal. The proposed architecture is implemented with Xilinx Vivado$$ Vivado $$ EDA tool using Artix7$$ Artix\kern0.3em 7 $$ FPGA board. [ABSTRACT FROM AUTHOR]

This paper presents a spatiotemporal encoding metasurface design to independently achieve the good radiation and the low scattering performances in the same frequency band. The proposed metasurface unit cell is composed of a square patch and two orthogonally placed I-shaped strips. By switching the operating states of the PIN diode inserted into each I-shaped strip between ON state and OFF state, a phase difference of 180° can be obtained in the band of 7.6–7.95 GHz for two orthogonally polarized incident waves. When a coaxial probe is introduced at the diagonal line of the square patch, the dual-polarized radiation capability is achieved within the frequency range of 7.6–7.95 GHz. With the proposed metasurface unit cell, the manipulation of the radiating wave and the scattering wave has no influence on each other. By controlling the PIN operating states by the field programmable gate array in real time, the power of the scattering wave is transferred to some higher order harmonics, thus realizing radar cross section (RCS) reduction. With optimized spatial and temporal encoding layouts, the proposed metasurface realizes the RCS reduction over 10 dB within the range of 7.3–8 GHz, with the maximum RCS reduction of 35.6 dB, while maintaining good radiation capability. [ABSTRACT FROM AUTHOR]

The deblocking filter (DF) and the sample adaptive offset (SAO) filter, which aids in enhancing the subjective quality of the image, make up the in-loop filter of the high-efficiency video coding (HEVC) encoder and decoder. The in-loop filter significantly increases the computational load on the HEVC encoder. It is challenging to design an in-loop filter on hardware that can handle intensive computations while using the least amount of on-chip memory, taking external memory traffic and dependencies simultaneously delivering high throughput to support Ultra HD video applications. The proposed design employs the following strategies to address these issues. This work proposes an address generation technique for pipelined horizontal and vertical filtering in DF, that avoids a transpose buffer which otherwise is required. This enables easy pipelining and parallelization thus improving throughput while reducing the on-chip memory utilization. A simplified SAO filter with parallel-pipelined processing is included in the design. These features enable the design to support ultra-HD 7680 $ \times $ × 4320 @ 40 fps video applications. The proposed hardware architecture has a total gate count of 7.73 K LUTs and 2.8 K slice registers, and it is implemented on a 28 nm field programmable gate array (FPGA) platform. [ABSTRACT FROM AUTHOR]

The high sampling rate in modern digital systems generates a large scale of data. To address the computational burden, this paper proposes a threshold activation-based simplified Lv's transform (SLVT) algorithm to analyze the transient multi-component linear frequency modulation signals. Only the signal arrival can trigger the signal analysis. This mechanism alleviates the computation pressure because of the sparsity of signals. The threshold activation mechanism enables transient signal detection and sampling rate adjustment, thereby enhancing the efficiency and effectiveness of the analytical process. The simplified Lv's transform (LVT) removes redundant computations on stretch weighting and the Discrete Fourier Transform (DFT) in Lv's transform. SLVT uses the efficient Bluestein chirp-z algorithm to implement the stretch keystone transform. The comparison results show that SLVT reduces the computational complexity of the original LVT by at least 30.8%. This algorithm exhibits superior performance compared to other advanced signal processing methods, such as discrete chirp Fourier transform, fractional Fourier transform, and Radon Wigner transform algorithms, in terms of parameter extraction accuracy, computational complexity, and execution time. Moreover, the implementation of a field programmable gate array accelerates SLVT computing by a factor of 116 in comparison to the CPU (Central Processing Unit) platform. [ABSTRACT FROM AUTHOR]

This paper investigates state estimation methods for dynamical systems when model evaluations are performed on resource-constrained embedded systems with finite precision compute elements. Minimum mean square estimation algorithms are reformulated to incorporate finite-precision numerical errors in states, inputs, and measurements. Quantized versions of least squares batch estimation, sequential Kalman, and square-root filtering algorithms are proposed for fixed-point implementations. Numerical simulations are used to demonstrate performance improvements over standard filter formulations. Steady-state covariance analysis is employed to capture the performance trade-offs with numerical precision, providing insights into the best possible filter accuracy achievable for a given numerical representation. A low-latency fixed-point acceleration state estimation architecture for optomechanical sensing applications is realized on Field Programmable Gate Array System on Chip (FPGA-SoC) hardware. The hardware implementation results of the estimator are compared with double-precision MATLAB implementation, and the performance metrics are reported. Simulations and the experimental results underscore the significance of modeling quantization errors into state estimation pipelines for fixed-point embedded implementations. [ABSTRACT FROM AUTHOR]

The logic structures implemented in Field Programmable Gate Arrays (FPGAs) are often critical and their correct operation is vital. FPGA devices are often used in areas where there is increased ionising radiation (space, medical diagnostics, aviation or nuclear power). There is therefore a need for mechanisms to correct radiation-induced errors. A common approach is the redundant implementation of particularly critical parts of the logic structure. By triplicating selected fragments, it is possible not only to detect potential errors but also to correct them. Such an approach is called triple modular redundancy (TMR), and its essence lies in the use of specialised voting circuits called voters, which allow the erroneous results of individual subcircuits to be eliminated by voting. The triplicate circuit under consideration, together with the voter, constitutes the mitigation structure. It becomes necessary to develop a test environment to assess the correct operation of these circuits. Also key is the efficiency of the implementation of these structures, which can be related to the occupation of logical resources or the power consumption of a given implementation. This paper demonstrates the essence of implementing a test environment to test the correctness of the mitigation of logic structures using TMR voters. An error injector mechanism using the Pseudo-Random Bit Sequence (PRBS) register is proposed, which introduces an element of randomness into the testing process. The aim of this research is to determine the implementation efficiency of the proposed test environment. In the experimental part, the implementation costs of the proposed solution were examined. The results indicate that between 66 and 109 LUT blocks were required to implement the error injector, corresponding to a relatively small increase in dynamic power consumption: by 22% for combinational circuits and by 37% for sequential circuits. [ABSTRACT FROM AUTHOR]

This article introduces a paradigm shift in radar technology with field programmable gate array (FPGA)-driven Phase estimation using floating point arithmetic (FPA). Leveraging FPGA's parallel processing and the precision of FPA, this work promises enhanced accuracy and efficiency. The proposed system's key performance metrics include the following: number of slices: 20,941, number of look-up tables (LUTs): 22,371, number of digital signal processing (DSP) blocks: 2, delay: 112.9 ns, and power consumption: 7.2 mw. A comparative analysis showcases advantages in area utilization, LUT, and DSP blocks despite a trade-off with delay. The presented methodology and results demonstrate the feasibility of real-time phase estimation at GHz rates, positioning this approach as transformative for next-gen radar systems. [ABSTRACT FROM AUTHOR]

The current study uses Field-Programmable Gate Array (FPGA) hardware to advance smart home technology through a self-learning system. The proposed intelligent three-hidden layer system outperformed prior systems with 99.21% accuracy using real-world data from the MavPad dataset. The research shows that FPGA solutions can do difficult computations in seconds. The study also examines the difficulties of maximizing performance with limited resources when incorporating deep learning technologies into FPGAs. Despite these challenges, the research shows that FPGA-based solutions improve home technology. It promotes the integration of sophisticated learning algorithms into ordinary electronics to boost their intelligence. [ABSTRACT FROM AUTHOR]

Abstract The utilisation of continuous random waveforms for radar, that is, noise radar, has been extensively studied as a candidate for low probability of intercept operation. However, compared with the more traditional pulse‐Doppler radar, noise radar systems are significantly more complicated to implement, which is likely why few systems exist. If noise radar systems are to see the light of day, system design, implementation, limitations etc., must be investigated. Therefore, the authors examine and detail the implementation of a real‐time noise radar system on a field programmable gate array. The system is capable of operating with 100% duty cycle, 200 MHz bandwidth, and 268 ms integration time while processing a range of about 8.5 km. Additionally, the system can perform real‐time moving target compensation to reduce cell migration. System performance is primarily limited by the memory bandwidth of the off‐chip dynamic random access memory.

Metasurface technology has attracted widespread attention, owing to its remarkable capability to control electromagnetic properties. In this paper, we design a reconfigurable reflective metasurface array operating at 5 GHz for beam generation and scanning based on coding metasurface. Field programmable gate array (FPGA) is equipped for switching the states of PIN (positive-intrinsic-negative) diodes loaded on the metasurface in real-time, resulting in a 180° phase difference. To obtain multi-beam radiation and high-accuracy beam steering, the coding sequence to produce the target radiation pattern is calculated by an algorithm program. We design the fitness function of a genetic algorithm (GA) to optimize the sequence corresponding to the target directions. The simulation result shows that with the accuracy of 1°, the proposed metasurface is capable of generating multi-beam and scanning two-dimensional beams within the 50° range. Further, we fabricate and measure a prototype sample of 15 × 15 elements, which is verified feasible by comparing the measured result and the simulation. This work demonstrates the great potential of applying this reflective metasurface to wireless communication or radar. [ABSTRACT FROM AUTHOR]

Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment. [ABSTRACT FROM AUTHOR]

Atomic-scale imaging using scanning probe microscopy is a pivotal method for investigating the morphology and physico-chemical properties of nanostructured surfaces. Time resolution represents a significant limitation of this technique, as typical image acquisition times are on the order of several seconds or even a few minutes, while dynamic processes—such as surface restructuring or particle sintering, to be observed upon external stimuli such as changes in gas atmosphere or electrochemical potential—often occur within timescales shorter than a second. In this article, we present a fully redesigned field programmable gate array (FPGA)-based instrument that can be integrated into most commercially available standard scanning probe microscopes. This instrument not only significantly accelerates the acquisition of atomic-scale images by orders of magnitude but also enables the tracking of moving features such as adatoms, vacancies, or clusters across the surface ("atom tracking") due to the parallel execution of sophisticated control and acquisition algorithms and the fast exchange of data with an external processor. Each of these measurement modes requires a complex series of operations within the FPGA that are explained in detail. [ABSTRACT FROM AUTHOR]

This document provides summaries of the winners of the 15th Microscopy Today Innovation Awards competition. The winners include CrystalView Microscope, Volutome, CICERO, Lightning Arctic, and Tempo. These innovations improve polarization accuracy, provide 3D imaging, make high-end imaging accessible, offer cooling and heating capabilities, and minimize electron dose while equalizing the signal-to-noise ratio. The document also highlights five other technological innovations, including LightSpeed Mode, AEcroscopy, Unity, HexAuFoil cryoEM specimen supports, and the Thermo Scientific Meridian EX Fault Isolation System. These innovations have applications in various scientific fields and offer improvements in imaging speed, data quality, and defect analysis. [Extracted from the article]

With the extensive proliferation of scanning probe microscopy (SPM)-related technologies, there is a growing demand for a fully customizable SPM controller. In response, we have developed an SPM controller that allows users to incorporate additional functions using LabVIEW, a graphical programming language. This controller incorporates fundamental features such as one-dimensional and two-dimensional scanning, feedback control, and slope compensation. In addition, it includes capabilities to restrict the speed of probe movement and safeguard the probe. Our system consists of a host personal computer (PC) running the Windows operating system and a National Instruments Reconfigurable Input/Output board equipped with a field programmable gate array (FPGA). The FPGA supports real-time deterministic processing, including feedback and probe protection functions, operating asynchronously from the host PC through data exchange via direct memory access first-in-first-out. The system features a graphical user interface on the Windows OS, supplemented by a character-based user interface that utilizes command strings in JavaScript object notation format. Furthermore, we provide wrappers for these commands using the Python programming language. We anticipate that our fully customizable bare born package of LabVIEW-based controller will prove beneficial for researchers utilizing SPM and those managing instruments requiring scanning and feedback control. [ABSTRACT FROM AUTHOR]

Precision agriculture (PA) technologies combined with remote sensors, GPS, and GIS are transforming the agricultural industry while promoting sustainable farming practices with the ability to optimize resource utilization and minimize environmental impact. However, their implementation faces challenges such as high computational costs, complexity, low image resolution, and limited GPS accuracy. These issues hinder timely delivery of prescription maps and impede farmers' ability to make effective, on-the-spot decisions regarding farm management, especially in stress-sensitive crops. Therefore, this study proposes field programmable gate array (FPGA)-based hardware solutions and real-time kinematic GPS (RTK-GPS) to develop a real-time crop-monitoring system that can address the limitations of current PA technologies. Our proposed system uses high-accuracy RTK and real-time FPGA-based image-processing (RFIP) devices for data collection, geotagging real-time field data via Python and a camera. The acquired images are processed to extract metadata then visualized as a heat map on Google Maps, indicating green area intensity based on romaine lettuce leafage. The RFIP system showed a strong correlation (R2 = 0.9566) with a reference system and performed well in field tests, providing a Lin's concordance correlation coefficient (CCC) of 0.8292. This study demonstrates the potential of the developed system to address current PA limitations by providing real-time, accurate data for immediate decision making. In the future, this proposed system will be integrated with autonomous farm equipment to further enhance sustainable farming practices, including real-time crop health monitoring, yield assessment, and crop disease detection. [ABSTRACT FROM AUTHOR]

Although deep reinforcement learning (DRL) has gained increasing popularity in numerical studies of active flow control, practical implementations of this technique in experiments remain challenging, particularly for fast air flows. In this study, we proposed a field programmable gate array (FPGA)-based DRL framework for high-speed experimental active flow control. By splitting the training and execution process of artificial neural network and implementing them effectively in central processing unit (CPU) and FPGA, experimental DRL control with an interaction frequency up to 10–100 kHz can be realized, which is two orders higher than that of the traditional CPU-based DRL framework. Such a new framework is tested in the classical problem of airfoil leading flow separation control at Rec = 2.13 × 105, with a plasma actuator and a hotwire serving as the flow disturber and the state sensor, respectively. As a result, experimental DRL control is rather attractive in terms of the time cost, able to find a converged closed-loop control strategy in only one run of 5 min, eliminating the tedious parameter tuning process in open-loop control (time cost: dozens of minutes to hours). Moreover, the magnitude of lift increment in the case of optimal DRL control is 3.2% higher than that of the best open-loop periodical control strategy. [ABSTRACT FROM AUTHOR]

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process–Voltage–Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field. [ABSTRACT FROM AUTHOR]

The increasing number of sensors and Internet of Things (IoT) devices have made the Denial of Service (DoS) attacks in IoT networks a significant security threat. The inherent characteristics of IoT networks such as the large number of end nodes, the heterogeneous nature of IoT networks, resource limitations in routers, and the multiplicity of application areas in daily life, make the investigation of attacks in these networks a major and important research problem. This paper presents a new approach for detecting and mitigating DoS attacks in IoT networks. The proposed approach is implemented on an Field Programmable Gate Array (FPGA)-based platform and tested for performance against different types of DoS attacks. The approach can respond quickly to attacks specific to IoT networks and can be easily implemented on hardware with low resource requirements. [ABSTRACT FROM AUTHOR]

The automated guided vehicle (AGV) is currently used in a wide range of industries. The control system is the core of the AGV, responsible for task assignment, localization, path planning, motion planning, vehicle management, etc. In previous AGV implementations, personal computer, embedded computer, digital signal processor for computing, and programmable logic controller, micro control unit, field programmable gate array for control have been combined to form the whole control system. These solutions can solve common control problems, but they are complex to implement. To simplify the implementation complexity, the following work is presented in this study: (1) a new real-time operating system (RTOS), called Student RTOS, is developed. The RTOS includes memory management, task management, message queue, semaphore, synchronization, and timer, etc.; (2) a control system based on the newly designed RTOS is presented on a single processor; (3) the RTOS and the control system are tested on a newly designed AGV. From the actual test results, the newly designed RTOS and control system can meet the requirements of real-time, functionality, etc., and can effectively replace the original control system composed of multiple device combinations. In addition to running on the ARM Cortex-A processor used in the AGV control system, the RTOS also runs on the ARM Cortex-M and the STM8S (8-bit) processors for more low-end applications. [ABSTRACT FROM AUTHOR]

The number of Internet-of-Things (IoT) devices has been increasing rapidly every year. Most of these devices have access to important personal data such as health, daily activities, location, and finance. However, these devices have security problems since they have limited processing power and memory to implement complex security measures. Therefore, they possess weak authentication mechanisms and a lack of encryption. Additionally, there are no widely accepted standards for IoT security. Device Identifier Composition Engine (DICE) was proposed as a standard that enables adding a security layer to low-cost microcontrollers with minimal silicon overhead. However, previous studies show that DICE-based attestation is vulnerable to some remote attacks. In this study, we present a novel method called DICEguard to address the security problems of DICE. One of the key innovations of DICEguard is its incorporation of periodic memory forensics (PMF) technique, leveraging a hardware-based hash engine to detect and mitigate potential security breaches resulting from firmware vulnerabilities. DICEguard enhances the overall resilience of IoT devices against attacks by swiftly detecting alterations indicative of malicious activity through periodic calculation and comparison of firmware digests. Furthermore, DICEguard introduces a one-time programmable (OTP) memory component to safeguard critical security parameters, such as public keys used for signature verification, against tampering by adversaries. This ensures the integrity of essential security measures even in the face of sophisticated attacks. We implemented the enhanced DICE architecture using the open-source RISC-V platform Ibex and the mbedTLS library for cryptographic operations. We performed the hash operations required by DICE in a hardware-based manner on a commercial Field Programmable Gate Array (FPGA) platform rather than firmware, which is more vulnerable to attacks. Our test results show that with negligible area overhead to a standard microcontroller system, the proposed method can detect the simulated attacks. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive stability analysis of the boundary‐based hybrid control (BBHC) algorithm designed for boost converter. The stability assessment is carried out utilizing multiple Lyapunov functions, addressing both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) operation. The boost converter is modeled as a hybrid automaton to capture its dynamic behavior accurately. Through rigorous Lyapunov stability analysis, this study demonstrates the effectiveness of the BBHC algorithm in ensuring stable operation of the boost converter across various operating modes. Additionally, the proposed control algorithm's validation is conducted using the FPGA‐in‐the‐loop (FIL) technique, highlighting its efficiency and robustness in real‐world applications. This research contributes valuable insights into the design and implementation of stable control strategies for boost converter, emphasizing the practical utility of the BBHC algorithm with FIL for enhanced performance and reliability in power electronics systems. [ABSTRACT FROM AUTHOR]

Autonomous robots operate on batteries, rendering power efficiency essential. The substantial computational demands of object detection present a significant burden to the low-power cores employed in these robots. Therefore, we propose a grid-based density-based spatial clustering of applications with a noise (DBSCAN) clustering accelerator for light detection and ranging (LiDAR)'s point cloud to accelerate computational speed and alleviate the operational burden on low-power cores. The proposed method for DBSCAN clustering leverages the characteristics of LiDAR. LiDAR has fixed positions where light is emitted, and the number of points measured per frame is also fixed. These characteristics make it possible to impose grid-based DBSCAN on clustering a LiDAR's point cloud, mapping the positions and indices where light is emitted to a 2D grid. The designed accelerator with the proposed method lowers the time complexity from O (n 2) to O (n) . The designed accelerator was implemented on a field programmable gate array (FPGA) and verified by comparing clustering results, speeds, and power consumption across various devices. The implemented accelerator speeded up clustering speeds by 9.54 and 51.57 times compared to the i7-12700 and Raspberry Pi 4, respectively, and recorded a 99% reduction in power consumption compared to the Raspberry Pi 4. Comparisons of clustering results also confirmed that the proposed algorithm performed clustering with high visual similarity. Therefore, the proposed accelerator with a low-power core successfully accelerated speed, reduced power consumption, and effectively conducted clustering. [ABSTRACT FROM AUTHOR]

Artificial intelligence-based optimization algorithm was used to compute the switching angle values. In order to run the inverter with the lowest possible Total Harmonic Distortion (THD) value, it is suggested in this study to use an algorithm such as the Practical Swarm Algorithm (PSA). The multilevel inverter and optimization algorithm were created and simulated in this study using a MATLAB software. A frequency spectrum analysis was also conducted and found to be consistent with the theoretical analysis of the system. To provide practical results, the FPGA generates PWM signals that are appropriate for the inverter switches. On the Spartan-3E Starter set, the suggested control schemes were developed and put it into practice. Xilinx-ISE 12.1i design software and VHDL hardware description language were used to create the FPGA software. The suggested approaches have a number of benefits over conventional digital PWM techniques, including straightforward hardware implementation, minimum scaling of digital circuits, easy digital design, reconfigurable, and flexibility in adaptability. The outcomes of the experiment and the simulation agreed rather well. [ABSTRACT FROM AUTHOR]

In order to meet the requirements of antenna for high bearing capacity, high positioning accuracy and speed stability of the test turntable, a test turntable with simple operation is designed. First of all, the structure of the turntable is introduced. The turntable adopts the form of gear transmission and multi-turn absolute encoder angle measurement. The mechanical simulation analysis of the turntable table is carried out, and the static performance and modal characteristics of the turntable are analyzed. Then, the servo control system of the turntable is introduced. The multi-turn absolute encoder is used as the detection element of the actual position of the turntable. The target position is sent to the controller by the upper computer through the serial port. The controller uses the field programmable logic gate array (FPGA) as the core, and the encoder, controller and control object constitute the position loop; In the software design, the fuzzy PID algorithm is used to replace the traditional PID algorithm. Finally, the turntable accuracy test platform is built, and the autocollimator and polyhedral prism are used to obtain the angle measurement error. The test results show that the control accuracy is better than ±0.01°, the system position accuracy is better than 2.5', and the turntable positioning accuracy and rotational speed stability have been effectively improved. [ABSTRACT FROM AUTHOR]

Molecular Dynamics (MD) simulation for computing Interatomic Potential (IAP) is a very important High-Performance Computing (HPC) application. MD simulation on particles of experimental relevance takes huge computation time, despite using an expensive high-end server. Heterogeneous computing, a combination of the Field Programmable Gate Array (FPGA) and a computer, is proposed as a solution to compute MD simulation efficiently. In such heterogeneous computation, communication between FPGA and Computer is necessary. One such MD simulation, explained in the paper, is the (Artificial Neural Network) ANN-based IAP computation of gold (Au147& Au309) nanoparticles. MD simulation calculates the forces between atoms and the total energy of the chemical system. This work proposes the novel design and implementation of an ANN IAP-based MD simulation for Au147& Au309using communication protocols, such as Universal Asynchronous Receiver-Transmitter (UART) and Ethernet, for communication between the FPGA and the host computer. To improve the latency of MD simulation through heterogeneous computing, Universal Asynchronous Receiver-Transmitter (UART) and Ethernet communication protocols were explored to conduct MD simulation of 50,000 cycles. In this study, computation times of 17.54 and 18.70 h were achieved with UART and Ethernet, respectively, compared to the conventional server time of 29 h for Au147nanoparticles. The results pave the way for the development of a Lab-on-a-chip application. [ABSTRACT FROM AUTHOR]

One of the most common mitigations against network-borne security threats is the deployment of firewalls, i.e., systems that can observe traffic and apply rules to let it through if it is benign or drop packets that are recognized as malicious. Cheap and open-source (a feature that is greatly appreciated in the security world) software solutions are available but may be too slow for high-rate channels. Hardware appliances are efficient but opaque and they are often very expensive. In this paper, an open-hardware approach is proposed for the design of a firewall, implemented on off-the-shelf components such as an FPGA (the Xilinx KC705 development board), and it is tested using controlled Ethernet traffic created with a packet generator as well as with real internet traffic. The proposed system can filter packets based on a set of rules that can use the whitelist or blacklist approach. It generates a set of statistics, such as the number of received/transmitted packets and the amount of received/transmitted data, which can be used to detect potential anomalies in the network traffic. The firewall has been experimentally validated in the case of a network data throughput of 1 Gb/s, and preliminary simulations have shown that the system can be upgraded with minor modifications to work at 10 Gb/s. Test results have shown that the proposed firewall features a latency of 627 ns and a maximum data throughput of 0.982 Gb/s. [ABSTRACT FROM AUTHOR]

Machine learning (ML) models have demonstrated discriminative and representative learning capabilities over a wide range of applications, even at the cost of high-computational complexity. Due to their parallel processing capabilities, reconfigurability, and low-power consumption, systems on chip based on a field programmable gate array (SoC/FPGA) have been used to face this challenge. Nevertheless, SoC/FPGA devices are resource-constrained, which implies the need for optimal use of technology for the computation and storage operations involved in ML-based inference. Consequently, mapping a deep neural network (DNN) architecture to a SoC/FPGA requires compression strategies to obtain a hardware design with a good compromise between effectiveness, memory footprint, and inference time. This letter presents an efficient end-to-end workflow for deploying DNNs on an SoC/FPGA by integrating hyperparameter tuning through Bayesian optimization (BO) with an ensemble of compression techniques. [ABSTRACT FROM AUTHOR]

The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of $\approx $ ${10}^{-{15}}$ or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus. [ABSTRACT FROM AUTHOR]

This research centers on the application of the discrete-time Taylor–Fourier transform (DTTFT) algorithmic implementation for phasor estimation on a field-programmable gate array board. The system employs a finite impulse response structure of a digital Taylor–Fourier filter to extract amplitude and phase information. The hardware description utilizes a multiply accumulator architecture with only forty embedded 9-bit multiplier elements, achieving an 18-bit input–output resolution. Performance assessment involves signal analysis through FPGA-in-the-loop simulation in MATLAB/Simulink. Findings demonstrate that the DTTFT-based phasor estimator can be effectively characterized using VHDL code and implemented on an Intel D2-115 board. [ABSTRACT FROM AUTHOR]

In this letter, the problem of optimization of multirate filterbanks is addressed. The factors that define the efficiency of these multirate systems are investigated and the implementations of structures in stages are analyzed. The latter, together with the polyphase implementations of the filters, allows obtaining optimal filterbanks in the use of resources for the FPGAs. [ABSTRACT FROM AUTHOR]

Deep learning has brought great development to radar emitter identification technology. In addition, specific emitter identification (SEI), as a branch of radar emitter identification, has also benefited from it. However, the complexity of most deep learning algorithms makes it difficult to adapt to the requirements of the low power consumption and high-performance processing of SEI on embedded devices, so this article proposes solutions from the aspects of software and hardware. From the software side, we design a Transformer variant network, lightweight convolutional Transformer (LW-CT) that supports parameter sharing. Then, we cascade convolutional neural networks (CNNs) and the LW-CT to construct a one-dimensional-CNN-Transformer(1D-CNN-Transformer) lightweight neural network model that can capture the long-range dependencies of radar emitter signals and extract signal spatial domain features meanwhile. In terms of hardware, we design a low-power neural network accelerator based on an FPGA to complete the real-time recognition of radar emitter signals. The accelerator not only designs high-efficiency computing engines for the network, but also devises a reconfigurable buffer called "Ping-pong CBUF" and two-level pipeline architecture for the convolution layer for alleviating the bottleneck caused by the off-chip storage access bandwidth. Experimental results show that the algorithm can achieve a high recognition performance of SEI with a low calculation overhead. In addition, the hardware acceleration platform not only perfectly meets the requirements of the radar emitter recognition system for low power consumption and high-performance processing, but also outperforms the accelerators in other papers in terms of the energy efficiency ratio of Transformer layer processing. [ABSTRACT FROM AUTHOR]