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Image processing is the most effective method for enhancement and segmentation of tuberculosis bacilli in sputum smear samples. Improper straining can result in poor screening results such as over-staining, under-staining, and blurred images. The goal is to find an image enhancement and segmentation technique that will prepare the image for feature extraction. There are still some shortcomings with existing method when it is implemented on Ziehl Neelsen images. In normal images, TB bacilli can be identified easily, but in blur and images with dark background, TB bacilli are sometimes hidden behind the sputum cells. Hence, the basic method of contrast enhancement is not enough to improve the contrast of TB bacilli as the object of interest within the image. In this study, the combination of local and partial contrast enhancement is proposed as the best method for image enhancement. Image segmentation can be accomplished using Otsu thresholding technique. Otsu's method is presented as most suitable image processing techniques in this paper. The goal of the Otsu Threshold is to find a threshold value that distinguishes the object of interest from the background. Experiment shows that the combination of local and partial contrast enhancement followed by Otsu’s method achieve an average segmentation accuracy of 98.93% when applied on 50 images of sputum smear.

The increasing need for automated networking platforms like the Internet of Things, as well as network services like cloud computing, big data applications, wireless networks, mobile Internet, and virtualization, has driven existing networks to their limitations. Software-defined network (SDN) is a new modern programmable network architectural technology that allows network administrators to control the entire network consistently and logically centralized in software-based controllers and network devices become just simple packet forwarding devices. The controller that is the network's brain, is mostly based on the OpenFlow protocol and has distinct characteristics that vary depending on the programming language. Its function is to control network traffic and increase network resource efficiency. Therefore, selecting the right controllers and monitoring their performance to increase resource usage and enhance network performance metrics is required. For network performance metrics analysis, the study proposes an implementation of SDN architecture utilizing an open-source OpenDaylight (ODL) distributed SDN controller. The proposed work evaluates the deployment of distributed SDN controller performance on three distinct customized network topologies based on SDN architecture for node-to-node performance metrics such as delay, throughput, packet loss, and bandwidth use. The experiments are conducted using the Mininet emulation tool. Wireshark is used to collect and analyse packets in real-time. The results obtained from the comparison of networks are presented to provide useful guidelines for SDN research and deployment initiatives.

Among the top 10 leading causes of mortality, tuberculosis (TB) is a chronic lung illness caused by a bacterial infection. Due to its efficiency and performance, using deep learning technology with FPGA as an accelerator has become a standard application in this work. However, considering the vast amount of data collected for medical diagnosis, the average inference speed is inadequate. In this scenario, the FPGA speeds the deep learning inference process enabling the real-time deployment of TB classification with low latency. This paper summarizes the findings of model deployment across various computing devices in inferencing deep learning technology with FPGA. The study includes model performance evaluation, throughput, and latency comparison with different batch sizes to the extent of expected delay for real-world deployment. The result concludes that FPGA is the most suitable to act as a deep learning inference accelerator with a high throughput-to-latency ratio and fast parallel inference. The FPGA inferencing demonstrated an increment of 21.8% in throughput while maintaining a 31% lower latency than GPU inferencing and 6x more energy efficiency. The proposed inferencing also delivered over 90% accuracy and selectivity to detect and localize the TB.

The high nutritional composition of microalgae that includes lipids is considered as one of the promising alternative lipid sources for animal feeds enrichment. Since microalgae have higher photosynthetic efficiencies than terrestrial plants, highly adaptable to environmental changes, and do not compete with conventional agriculture for resources, the inclusion of lipid sources from microalgae in feed could help the sustainability of livestock production systems. This study has reported the indigenous microalgae strains from Pahang lakes and determined lipid-rich strains that have the potential for alternative lipid sources. Pure isolated strains were identified using an 18S rDNA marker. The microalgae strain biomass was determined for 15 days. Meanwhile, the screening for high-rich lipid contents in microalgae strains was carried out using Nile Red fluorescent dye. A total of 11 strains were successfully isolated that consist of 8 different species (Carteria radiosa, Spongiosaccinopsis terrestris, Desmodesmus sp., Desmodesmus abundans, Dendodesmus brasiliensis, Chlamydomonas reinhardtii, Mychonastes timauensis, and Mychonastes ovahimbae). Results showed that PHG C01, PHG C02, and PHG F03 have the highest biomass production among all strains. Meanwhile, for lipid production, PHG B01 and PHG F03 showed the highest results. Thus, PHG B01 and PHG F03 strains were chosen as potential candidates to be used as an alternative lipid source in animal feed feedstock.

An electro-encephalography (EEG) brain-computer interface (BCI) can provide the brain and external environment with separate information sharing and control networks. EEG impulses, though, come from many electrodes, which produce different characteristics, and how the electrodes and features to enhance classification efficiency have been chosen has become an urgent concern. This paper explores the deep convolutional neural network architecture (CNN) hyper-parameters with separating temporal and spatial filters without any pre-processing or artificial extraction processes. It selects the raw EEG signal of electrode pairs over the cortical area as hybrid samples. Our proposed deep-learning model outperforms other neural network models previously applied to this dataset in training time (∼40%) and accuracy (∼6%). Besides, considerations such as optimum order for EEG channels do not limit our model, and it is patient-invariant. The impact of network architecture on decoder output and training time is further discussed.

In Malaysia, English language is the secondary language for most of the people and they usually rely on the education system to learn the language especially in learning how to read and pronounce the words correctly. As a multiracial country, Malaysians have many dialects according to the different states, which can affect the children’s pronunciation of the language. Consequently, their own style of dialect causes the children to struggle in developing the right pronunciation during the early years of school. The children will be exposed to the proper language at school but limited to the weekdays and school hours. Therefore, the technology of computerized applications has a high potential to help young kids in reading with the correct pronunciation. This paper presents the development of a mobile application with speech implementation based on Flutter framework for early reader assistant. The project is evaluated based on the subjective satisfaction towards the application in terms of overall system and functionality of the application, ease of login into the application and the difficulty of the words provided in the application. Based on the study, an average mean score of 3.36 is obtained in which most of the users feel that the application can deliver its function and purpose to the users. In conclusion, the mobile application should be able to aid the users in improving their reading skills and pronunciation.

A compact meandered dual-bands monopole antenna for the application of a wireless local area network (WLAN) is proposed. This antenna has two operating frequency bands which are 2.4 GHz and 5.2 GHz and denoted as lower and upper operating bands respectively. In the antenna design, a meandered arms structure has been proposed to obtain a compact size monopole antenna with an overall dimension of 30 mm x 21 mm. Furthermore, the dual-bands operating frequency is achieved with the contribution of two meandered arms structure as well as a partial ground plane proposed in the antenna design. The copper layer traces with the thickness of 0.035 mm has been used as the radiating patch and the partial ground plane has been printed at the back side of the FR-4 substrate with the permittivity, ε_r of 4.5 and the thickness of 1.6 mm. The proposed antenna has a simple design, small size, easy to fabricate and low cost. The measured and simulated results were compared to analyse the performance of the designed antenna. From the simulation, the operating frequencies achieved are at 2.44 GHz and 5.23 GHz, while from the measurement at 2.50 GHz and 4.44 GHz. Other antenna parameter such as radiation pattern and gain has also been evaluated and analysed.

Home Automation System is becoming more popular day by day due to its numerous benefits. This project proposes an idea in the design of low cost home automation system by using the Internet of Things (IoT) and voice recognition. The layout of the home divided into four areas and each area has own function and system. The Raspberry Pi 3 (RPi) Model B+ used as the main controller for the processing and transmitting the input data. IoT provided huge storage for data collection from sensors and home appliances. An Android application is developed to monitor the home environment and remotely control the home devices by using the button or voice. The speaker-independent recognition system by using Google Voice to Text on Android embedded in this project for physically challenged people to control the electrical appliances without moving. All the data will be stored in Firebase and can be retrieved at any time by the application and the RPi board. There is a side view of a prototype model with two floors and divided into four home areas. This Low-Cost Home Automation System using IoT and Voice Recognition is successfully achieved the project’s objective.

RGB colour model is a basic colour model and complements together to produce full colour range but it is unable to produce sufficient information for digital image analysis. However, HSL is capable to provide other useful information such as colour in degree, saturation of the colour and brightness of colour. In this work, RGB to HSL mathematical conversion algorithm is implemented on FPGA chip. Parallelism and pipelining capabilities of FPGA helps to speed up conversion performance. The RGB to HSL equation is implemented by using two architectures which are parallel and 7-stages pipeline architectures. The designed parallel and pipeline converters have one clock and seven clock cycle of data latency respectively. The parallel and pipeline architectures for RGB to HSL converter have been achieved rate of accuracy by hardware verification up to 99% and 98% and possessed maximum operating frequency merit of 50 MHz and 120 MHz respectively.

Based on Moore’s prediction, the future integrated systems will contain billions of transistors with hundreds of IP core to undergo complex multimedia delivery and networks services. In order to continue the relevancy of Moore’s law, Network-on-Chip (NoC) architectures have been proposed. The bus structure in System-on-Chip (SoC) is swapped by a network with routers and wires. Routers in NoC are responsible to route packets based on the routing algorithms. For various system, there are a lot of different algorithms to suit with each system requirement. Routing algorithm is further divided into two which include oblivious routing algorithm and adaptive routing algorithm. This paper presents a review of different types of well-known router architecture in NoC. The routers are classified by respect to the adaptive routing algorithms with a view of the performance characteristics depending on the application requirements in NoC. The outline and features of several router architectures are reviewed and analyzed.

This paper discusses about the modeling of frequency coded serial communication for the application of Eurobalise on hardware-based field programmable gate array (FPGA). The transceiver consists of FPGA and the ultra-high frequency (UHF) band amplitude shift keying (ASK) module. In the convention interface of the ASK transceiver module with the digital controller, noise has introduce into the channel. The noise in the output of ASK receiver has distorted the transmitted data causing the throughput of the wireless channel to be decreased. When the ASK module interfaces with the FPGA device, the noise from the output of the ASK receiver causing the receiving FPGA retarded. The purpose of the frequency coded serial data is to provide continuous specific frequency pulse train to the ASK transmitter. The original serial bit stream is then modulated in the pulse train with different frequency corresponding to the bit’s logic level. This technique has made the output of the ASK receiver to produce a very clean signal with extremely less noise. Hence, the receiver’s FPGA able to capture all the transmitted data accurately across traditional disciplinary boundaries, including computer hardware, algorithms, electronics interfacing and application domain.

In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range of traffic requirements from various FPGA application design instances. Simulation results show performance augmentation of 25% on average over an equal-size standard router, or achieve iso-performance using 50% less virtual channel buffer size.

As the complexity of ASIC/SoC design is increasing along with the number of logic gates, a prototyping process in the verification stage is facing a challenge when the ASIC/SoC design cannot fit into a single FPGA. A solution to prototyping multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA. There are various implementation tools and platform available in the market which automates an FPGA-based prototype phase such as Cadence Protium Rapid Prototyping Platform, Synopsys and S2C. In this paper, Synopsys protocompiler tool will be used to perform the prototyping process of the large 4 core CPU based circuit into the HAPS-80 FPGA platform. This paper will be focusing on the partition requirement needed to successfully prototype the large SoC circuit into the multi-FPGA. The presence of cut clocks in a circuit after partition stage will resulting to the failure in routing stage due to the congestion error. In this paper, two techniques are used, which is automatic clock replication by the Synopsys Protocompiler tool and our proposed technique which is Manual Clock Distribution technique to solve the presence of the cut clock, so that the circuit is able to meet the partition requirement to complete the prototyping process into multi-FPGA. Obtained result from the proposed technique showing that prototyping the large SoC circuit into the multi-FPGA platform has met the specification by eliminating 100% presence of cut clock.

A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.

One of the greatest challenges with cutting edge technology in System-on-Chip (SoC) is capability of processing core especially for complex and larger network size interconnections. Additionally, it is important to consider the effectiveness of routing algorithm in the overall performance of Network-on-Chip (NoC). Hence, the design and implementation of networks-on-chip should be considering aspects of simplicity in design, bandwidth usage, delay and power consumption. In essence, adaptive technique is a potential routing algorithm for better performance in network-on-chip (NoC) in which have properties such as prevention of livelock, deadlock, and starvation. This paper employed survey to investigate the impact of deterministic routing algorithm that has degrade overall performance and deadlock happen due to the fixed direction to the destination. An adaptive routing algorithm straighten out the problem of deadlock from deterministic routing algorithm by providing routing flexibility.

There are several factors that may result to wrist injuries such as athlete injuries and stroke. Most of the patients are unable to undergo rehabilitation at healthcare providers due to cost and logistic constraint. To solve this problem, this project proposes a home-based wrist rehabilitation system. The goal is to create a wrist rehabilitation device that incorporates an interactive computer game so that patients can use it at home without assistance. The main structure of the device is developed using 3D printer. The device is connected to a computer, where the device provides exercises for the wrist, as the user completes a computer game which requires moving a ball to four target positions. Data from an InvenSense MPU-6050 accelerometer is used to measure wrist movements. The accelerometer values are read and used to control a mouse cursor for the computer game. The pattern of wrist movements can be recorded periodically and displayed back as sample run for analysis purposes. In this paper, the usefulness of the proposed system is demonstrated through preliminary experiment of a subject using the device to complete a wrist exercise task based on the developed computer game. The result shows the usefulness of the proposed system.

Application Specific Instruction-set Processor (ASIP) has a general-purpose architecture that can be modified and used in a variety of applications. However, this increases the power and memory utilization and affects the functionality and efficiency of ASIP. This paper is defining the flexibility of ASIP for Turbo decoding in term of its functionality and architecture for specific applications such as DVB-RCS, 3GPP. The proposed architecture has a dedicated SIMD (Single Instruction Set Multiple Data), coupled with distributed memory based ASIP. It has been concluded in this paper that ASIP facilitates parallelism at different levels, thereby, increasing the efficiency, power consumption, and processing time.

The most important issues in the field of speech recognition and representative of the speech is a feature extraction. Feature extraction based Mel Frequency Cepstral Coefficient (MFCC) is one the most important features required among various kinds of speech application. In this paper, FPGA-based for speech features extraction MFCC algorithm is proposed. The complexities of computational as well as the requirement of memory usage are characterized, analyzed, and improved. Look-up table (LUT) scheme is used to deal with the elementary function value in the MFCC algorithm and fixed-point arithmetic is implemented to reduce the cost under accuracy study. The final feature extraction design is implemented effectively into the FPGA-Xilinx Virtex2 XC2V6000 FF1157-4 chip.

Wireless Sensor Networks (WSN) consists of sensor nodes for monitoring and reporting sensible changes on a field to a specific server. One of the applications of WSN is large area monitoring, where sensor nodes are placed in far fields with limited power sources. Due to the adhered reason, the energy consumption of sensor nodes is considered as one of the major challenge in WSN. Many factor in WSN contributes to energy consumption such as Medium Access Control protocol (MAC), the network topology, and routing protocol. With the variety of factors that affects the energy consumption in WSN; the challenge of optimizing WSN networks toward a low energy consumption is becoming a hard problem. In the literature many efforts are paid for designing, implementing, and improving protocols in terms of power consumption. However, few efforts are paid for optimizing the existing protocols and other network parameters toward a green technology. This paper focuses in WSN infrastructure and protocols optimization by introducing the Ichi Taguchi (Taguchi) optimization method. Taguchi method is used to predict the best design parameters to achieve optimal performance parameters. Moreover, Taguchi method is used to optimize the energy consumed by sensor nodes against network protocols and network topology design parameters. A simulation experiments are curried out on the discrete event simulator OMNET++ for the purposes of this research paper. The obtained results show the impact of the network protocols toward the energy consumption. Furthermore, a proposed network topology and protocols set is introduced, and compared against the existing once.

An embedded system application involves a diverse set of skills that extend across traditional disciplinary boundaries, including computer hardware, software, algorithms, interfacing and application domain. Field Programmable Gate Arrays (FPGAs) which offer flexibility in design like software, but with performance speeds closer to Application Specific Integrated Circuits (ASICs) are used as an embedded-based system in this project. The character recognition project using artificial neural network (ANN) approach is implemented on Altera Cyclone II 2C35 FPGA device and the results shown very promising.

The advances in Wavelength Division Multiplexing (WDM) technology have tremendously increased the bandwidth of a single fiber optic, for local and metropolitan area network (LAN and MAN). This paper presents and discusses analysis on packet length for multiple optical channel, which coupled Ethernet with WDM to decrease the average queuing delay and increases the normalized throughput. The performances of three channels with several range of packet length were evaluated by employing discrete event simulator. It has been proved that longer packets gives better performance on throughput, however it does increased the average queuing delay. Packet length in range of 4096-8192 bits per packets gave similar result of throughput with normal packet length for Ethernet (512-12144 bits per packets).