64 results on '"Fangxu Lv"'
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2. Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
3. Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization.
4. An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM.
5. A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.
6. Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.
7. A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.
8. An Adaptive Equalization Algorithm for High Speed SerDes.
9. An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.
10. A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology.
11. A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology.
12. A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.
13. A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology.
14. Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators.
15. A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.
16. A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
17. Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
18. An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.
19. A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.
20. A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.
21. A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS.
22. A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.
23. A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.
24. A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.
25. A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
26. Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network.
27. A Low BER DB-PAM4 Adaptive Equalizer For Large Channel Loss In Wireline Receiver
28. Adaptive Equalizer for 112 Gb/s DB-PAM4 SerDes
29. An Adaptive Equalizer for 56 Gb/s Duo-Binary SerDes
30. A 28Gb/s NRZ and 56Gb/s PAM4 SerDes Dual-Mode Transmitters Based on 28nm CMOS
31. A Low BER Adaptive Sequence Detection Method for High-Speed NRZ Data Transmission
32. A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS
33. A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface
34. Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR
35. An Adaptive Equalizer for 56 Gb/s PAM4 SerDes
36. A High Phase Detection Density and Low Space Complexity Mueller-Muller Phase Detector for DB PAM-4 Wireline Receiver
37. A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
38. Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators
39. A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology
40. A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology
41. A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS
42. A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS
43. A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
44. Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits
45. A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS
46. A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology
47. A 10 GHz ring-VCO based injection-locked clock multiplier for 40 Gb/s SerDes application in 65 nm CMOS technology
48. A 1.25–12.5Gb/s 5.28mW/Gb/s multi-standard serial-link transceiver with 32dB of equalization in 40nm CMOS
49. A 28Gbps reference-less VCO based CDR with separate proportional path technology in 65nm CMOS
50. Design of 80-Gb/s PAM4 wireline receiver in 65-nm CMOS technology
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