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In this thesis four important physical and material aspects faced by MOSFET devices as dimensions move to the length scale of 10nm have been investigated: i) metal source/drain contacts with dopant segregation for reduced contact resistance and improved carrier injection; ii) variability of the Schottky-barrier height (SBH) in MOSFET contacts; iii) strained silicon as a high mobility channel material; iv) silicon nanowire (NW) MOSFETs in order to suppress short channel effects by a multi-gate architecture. Ultimately scaled devices require highly conductive contacts with abrupt junctions. However, due to Fermi-level pinning at the metal-semiconductor interface, the performance of SB-MOSFETs still falls behind that of conventional FETs. Nickel-silicidation induced dopant segregation is highly effective in improving carrier injection through SBs, resulting in higher Ion/Ioff -ratios and better sub-threshold swings. Arsenic dopant segregation has been studied in detail as a function of NiSi thickness, implantation energy and dose, as well as process conditions for the formation of NiSi. It is shown that dopant concentrations as high as the solid solubility and lateral dopant slopes of 1-2nm/dec at the NiSi/Si-contact interface can be obtained. Simulations of scaled ultra-thin-body SOI MOSFETs with dopant segregation demonstrated that these devices can be scaled down to channel lengths of L=10nm. Variability in the electrical characteristics of SB-MOSFETs without and with dopant segregation has been investigated by a new experimental method, that allows to measure the impact of various sources leading to variability. The inherent variability of the SBH has been identifed as the main source of variability and an increase in SBH variability due to dopant segregation by 0.01eV was found. The importance of SBH variability for the on-current, even for very low SBHs of 0.03eV, was demonstrated with simulations. High mobility channel materials are required, as the steady increase of carrier velocity with gate-length scaling reaches its limit. Several aspects of the fabrication of biaxial tensile strained SSOI substrates by strain transfer between a thin SiGe buffer and a Si cap layer have been investigated with emphasis on reducing the threading dislocation density to 1x10e6cm-2. Thin SiGe/Si-heterostructure lines featuring highly asymmetric strain were fabricated that show decreased resistivities for electrons and holes. Asymmetric strain relaxation relies on the limitation of the path length of threading dislocations by the stripe boundaries in thin SiGe/Si lines, leading to an asymmetrical dislocation network. The electrical properties of biaxial tensile strained (001) SSOI with a stress of 1.2GPa have been studied using Hall-bar MOSFETs. SSOI devices showed improved on-currents, mobilities and transconductances over unstrained parallel processed devices. The mobility in n-type SSOI had a peak value of 1250 cm2/Vs at low vertical electric field, an enhancement by a factor of 1.7 compared to unstrained Si. The impact of biaxial strain on the electron affinity was determined by measuring threshold voltage shifts between strained and unstrained devices. The effective electron mass in 60nm biaxial tensile strained (001) SSOI and unstrained SOI was determined to be meff = 0.20m0 from Shubnikov-de Haas oscillations in the longitudinal resistance. This proves that biaxial tensile stress of 1.2GPa does not warp the Delta2 constant energy surfaces of the Si conduction band for in-plane directions, in agreement with band structure calculations. The mobility increase in biaxial tensile strained SSOI is, therefore, caused by the occupation of the Delta2-valleys with low effective electron mass mt in transport direction and reduced scattering due to a smaller k-space volume. To avoid short channel effects in ultimately scaled FETs multi-gate geometries have to be used. A fully CMOS compatible fabrication process for Si NW-FETs has been developed and devices with trapezoidal cross-sections of about 40x40nm2 were fabricated, featuring excellent electrical characteristics. Current flow on different crystal planes in multi-gate devices has been used to take advantage of the anisotropy of conductivity in Si in order to match the on-currents of n- and p-type MOSFETs with the same dimensions. Improved electron mobility due to strain and excellent electrostatics due to a multi-gate architecture were combined in a uniaxial tensile strained NW-FET. Size-dependent lateral strain relaxation of nanostructures was used to transform biaxial tensile strain into uniaxial tensile strain along the NW. Uniaxial tensile strained NW n-FETs show a factor x 2.3 enhanced mobility and improvements in on-current and transconductance by a factor of x 2.5 and x 2.1, respectively. Circular suspended NWs with diameters down to