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In this chapter, we will learn the basics of flip chip packaging, including bump pattern selection, design, and assembly process. Flip chip rules and guidelines provided in this chapter are necessary for design of common flip chip packages as well as advanced packages. Reader is encouraged to master the flip chip design strategy and rules provided in this chapter.

Due to higher input/output (I/O) count and power delivery problem in deep submicrometer (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance application-specific integrated circuit and microprocessor designs. However, it is hard to tell which technique can provide better design cost edge in usually concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-I/O flip-chip design. It is based on an I/O buffer modeling and an I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have achieved better area and I/O wirelength in area-IO flip-chip configuration (especially for pad-limit designs), compared with peripheral bonding configuration in packaging consideration.

Due to the infeasible pre-assignment of IO connections in a flip-chip design, all the published RDL routers cannot guarantee 100% routability for the pre-assigned IO connections. In this paper, based on two swapping processes for pin reassignment, the unroutable conditions in a flip-chip design can be eliminated. Furthermore, by using the assignment of routability-driven transfer and boundary pins, a given set of pre-assigned IO connections between the wire-bonding pads and the bump balls can be completely routed to minimize the total wirelength with 100% routability in a flip-chip design.

Analytical and numerical results for dynamic temperature distribution in the semiconductor die operating in pulse mode are presented. A new type of flip-chip design is considered.

We study the problem of block and I/O buffer placement in flip-chip design. The goal of the problem is to minimize simultaneously the total path delay and the total skew of all input/output signals. We present two simple, yet effective, algorithms for the problem. Both algorithms place blocks to minimize the total path delay, and place I/O buffers to minimize the total skew. As compared to an existing method (Peng, C.-Y., 2003), the experimental results show that both algorithms are able to get better placement solutions with improvement rates of up to 65% and 77.5%, respectively, and run much faster.