Search

In this research work, a novel full adder (FA) circuit is designed based on a hybrid full-swing logic with 20 transistors. The 20-transistor hybrid full-swing adder (HFSA) circuit is designed and measured based on a 12-transistor XOR–XNOR circuit, which can efficiently use chip area and power dissipation. We developed a novel 12-transistor XOR–XNOR circuit that provides glitch-free full-swing outputs. This circuit integrates 2-to-1 multiplexers, pass transistor logic, and inverters. Due to its minimum power consumption and maximum area efficiency, it is a critical component of hybrid full-swing adder circuits. This research aims to measure the efficiency and practicality of novel and eleven existing methods by considering several factors, including performance and measuring key characteristics. As a result, our novel XOR–XNOR circuit offers superior performance compared to its peers—it has a smaller chip area of 7.35 µm2, an average power of 2.44 µW, and a propagation delay (25.88 and 24.87) ps, respectively. The proposed full adder has a smaller chip area of 14.157 µm2, an average power consumption of 3.582 µW, and a propagation delay of 72.66 ps. It emphasizes large-scale structures, including 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit full adders, as cascade designs utilizing a novel ripple carry adder. We also used the ADEXL design suite to analyze process corners, voltages, and temperatures, which is essential for ensuring circuit accuracy and reliability through multipoint simulations and Monte Carlo analysis. All circuits can be designed and measured in the ADEXL design suite using Cadence Virtuoso software in GPDK 45nm technology. This research shows that HFSA circuits are suitable gates for electronic component assembly. Centralized high-speed processing systems can benefit from HFSA circuits as an alternative to traditional FA circuits. [ABSTRACT FROM AUTHOR]

Ultra-low energy systems can be realized by utilizing multiple supply voltages which is feasible using voltage level converters. This paper proposes a high-speed and energy-efficient level converter (LC) which addresses the major limitations of state-of-the-art Wilson current mirror based LC. The proposed LC employing output-controlled virtually supplied inverter, controlled PMOS device and a pass transistor to enhance its speed performance. It is implemented in 180 nm CMOS technology using Cadence (virtuoso) tool and simulated through Spectre circuit simulator. The simulation results confirm that the LC can convert sub-threshold input voltage (180 mV) to nominal output voltage (1.8 V) which shows the ability to convert wider input range. The proposed LC demonstrates the delay of 3.79 ns, energy per transition of 839 fJ and static power consumption of 521 pW for the target conversion of 0.4 V to 1.8 V at signal frequency of 1 MHz. [ABSTRACT FROM AUTHOR]

A high current matching over full-swing and low-glitch charge pump (CP) circuit is proposed. The current of the CP is split into two identical branches having one-half the original current. The two branches are connected in source-coupled structure, and a two-stage amplifier is used to regulate the common-source voltage for the minimum current mismatch. The proposed CP is designed in TSMC 0.18 µm CMOS technology with a power supply of 1.8 V. SpectreRF based simulation results show the mismatch between the current source and the current sink is less than 0.1% while the current is 40 µA and output swing is 1.32 V ranging from 0.2 V to 1.52 V. Moreover, the transient output current presents nearly no glitches. The simulation results verify the usage of the CP in PLLs with the maximum tuning range from the voltage-controlled oscillator, as well as the low power supply applications. [ABSTRACT FROM AUTHOR]

Abstract: We present the control mechanism for interfacial charges in an organic field-effect transistor (OFET) by the introduction of a surface polarized layer (SPL), interfaced with a p-type organic semiconductor (p-OS), which generates a transverse dipolar field. The concept of such SPL enables to develop a high noise-margin full-swing inverter of the p-OS, pentacene, on a single substrate. The transverse dipolar field of the SPL of a fluorinated polymer, placed between the p-OS and a gate insulator, plays an essential role in the accumulation of holes at the interface due to the surface dipoles of the fluorinated polymer. Owing to the interfacial holes, the drain current of the p-type OFET becomes to saturate at zero gate voltage and its magnitude lies between the on-current and off-current of a conventional OFET with no SPL. This allows directly the high noise-margin and the full-swing capability of an organic inverter based on the p-OS material. [Copyright &y& Elsevier]

Abstract: A full-swing pentacene organic thin-film transistor (OTFT) inverter, which is composed of an enhancement-mode driver and a depletion-mode load, is proposed and confirmed at the discrete device level. The depletion-mode OTFT can be easily converted to the enhancement-mode by adding a thin PMMA layer between insulator and pentacene to the depletion-mode fabrication sequence. It is demonstrated that the proposed inverter shows a full-swing characteristic, large inverting gain and high noise margin with only two OTFTs. [Copyright &y& Elsevier]