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In this work, we demonstrate a novel In0.52Al0.48As based top-illuminated avalanche photodiode (APD), designed to circumvent the problem of serious bandwidth degradation under high gain (>100) and high power operation and significantly enhance the dynamic range in the established frequency modulated continuous wave (FMCW) lidar system. In our APD design, the carriers transiting through the dual multiplication (M-)layers are subjected to a stepped-up electric field profile, so they can be energized by the first step and propagate to the second step to trigger the avalanche processes. Such a cascade avalanche process leads to an ultra-high gain bandwidth product (460 GHz) with a 1 A/W responsivity at unit gain. Compared to the high-performance and commercial p-i-n PD and photo-receiver (PD + trans-impedance amplifier (TIA)) installed in the same lidar test bed, our demonstrated APD receiver (without TIA) has a larger S/N ratio under high operation gain (33 A/W) with less optical local-oscillator (LO) power required (0.25 vs. 0.5 mW), while exhibiting a wider dynamic range in each pixel. These advantages in turn lead to the construction of a better quality of 3-D lidar image by using the demonstrated APD.

This article presents a frequency interleaved technique (FIT) that can be applied to add resonant peaks in the response of distributed amplifier (DA) for loss compensation and then a frequency-interleaved distributed amplifier (FIDA) that can achieve a high-gain and wide-bandwidth frequency response by summing multiple overlapping distinct-band frequency responses through a distributed configuration. A detailed discussion was introduced to verify the FIDA and a DA was implemented using the FIT. The reported 65-nm CMOS FIDA chip occupies an area of 0.9 x 0.95 mm² and achieves a 17.2 dB small-signal power gain, 2-68 GHz -3-dB bandwidth, gain bandwidth product (GBW) of 478 GHz, and gain ripple of less than 2 dB, while consuming 120 mW under 1.2 V.

Low-dimensional photodetectors, in particular those in photoconductive mode, often have extraordinarily high photogain. However, high gain always comes along with a slow frequency response. The gain-bandwidth product (GBP) is a figure of merit to evaluate the performance of a photodetector. Whether the high-gain photoconductors can outperform standard PIN photodiodes in terms of GBP remains an open question. In this article, we derived the analytical transient photoresponses of nanowire photoconductors which were validated with the simulations and experiments. Surprisingly, the fall transients do not follow a simple time-dependent exponential function except for some special cases. Given the analytical photogains that were established previously, we derived the theoretical GBP of high-gain nanowire photoconductors. Analysis of the analytical GBP indicates that nanoscale photoconductors, although having extremely high gain, will never outperform typical PIN photodiodes in terms of GBP.

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

The present investigation is focused on the analog/RF performance of ferroelectric (FE) based substrate metal oxide semiconductor field effect transistor (MOSFET) for digital application as an inverter. Short channel effect (SCEs) reduced significantly with improvement in switching ratio (Ion/Ioff). The simulation shows the immunity towards the parameters like transconductance (gm), transconductance generation factor (TGF), early voltage (VEA) and the intrinsic gain (AV) which allows the device to look into digital application. Also, the RF performance parameters come out to be superior for the proposed device structure, as the gain frequency product (GFP) and gain bandwidth product (GBP) enhanced by 100 and 10 folds, respectively. Further, RF investigation shows the enhanced results as attributed with peak values for transconductance frequency product (TFP) and gain transconductance frequency product (GTFP). The transient analysis shows an improvement in the noise margin (NM) for FE-MOSFET structure. Thus, the proposed architecture can be an attractive alternative for the digital application.

This paper examines the effects of temperature variation on Hetero Gate Oxide Dual Work Function Step Channel Tunnel Field-Effect Transistor (HGO-DW-SCTFET). For different temperatures, the proposed device performs better in comparison with conventional Step Channel Tunnel Field-Effect Transistor (SCTFET). This study includes a temperature-based analysis on DC and Analog parameters like drain current, threshold voltage (Vth), Sub-threshold Slope (SS), ION–IOFF ratio, trans-conductance, gate drain capacitance (Cgd), cut off frequency (fT), Trans-conductance-frequency product (TFP), Trans-conductance generation factor (TGF), Gain Bandwidth Product (GBP), Transit Time (TT) to analyze its performance at various temperatures and various models named BT-BT, SRH, and TAT, along with the linearity analysis, and the reliability of the device. The variation in DC and Analog parameters shows that the proposed device can be used for the applications of high temperature. To examine the performance of the device, a wide range of temperatures of 250K to 400K has been taken in the TCAD simulator.

Emerging applications in D-band (110–170GHz) demand amplifiers with high gain-bandwidth (GBW) products. In this frequency range, the cascode stage offers superior available gain, thanks to the high output impedance, but the design of the output matching network entails a GBW tradeoff. The issue is deeply investigated in this work. Simple, closed-form equations for gain and bandwidth as a function of the load reflection coefficient are derived, leading to the following design insights: 1) for maximum gain and bandwidth, the output matching network should be implemented with positive (magnetic) reactances; 2) with lossy reactances, an optimal load reflection coefficient exists to maximize the power gain, ${\Gamma '_{L-{\mathrm{ opt}}}}$ ; and 3) by selecting ${\Gamma '_{L} , the bandwidth increases quickly with a marginal gain penalty, finally enhancing the GBW product. Leveraging the results of the analysis, single-stage and multistage stagger-tuned amplifiers are implemented in SiGe BiCMOS technology. Two- and three-stage amplifiers demonstrate more than 60GHz bandwidth with 20 and 28dB gain, respectively, corresponding to 700GHz and 1.7 THz GBW. Normalizing gain and bandwidth to the number of stages and technology $f_{\max }$ , the resulting figure of merit is remarkably higher than previously reported silicon amplifiers in the same band.

A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The design...

In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

In this work, a new structure of Schottky tunneling MOSFET has been designed and simulated. The proposed device structure uses floating gates and dual material main gates to counter short channel effects and to improve RF/Analog figures of merit for low power design applications. The use of floating gates modulates the Schottky barrier width, hence improves the ON state and RF/Analog figures of merit performance of the proposed device in comparison to a conventional device. A significantly high ION( $1.231\times 10^{-4}\text{A}/\mu \text{m}$ ) and ION/IOFF ratio ( $2.52\times 10^{5}$ ) is achieved in the proposed ST-MOSFET in comparison to conventional ST-MOSFET having $\text{I}_{\mathrm {ON {}}}(1\times 10^{-7}\text{A}/\mu \text{m}$ ) and ION/IOFF ratio ( $1\times 10^{2}$ ). It has been observed that there is more than 100 times improvement in cutoff frequency ( $f_{\mathrm {T}}$ ), transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), gain bandwidth product (GBP) and max oscillation frequency ( $f_{\mathrm {max}}$ ) in comparison to conventional ST-MOSFET. In addition, there are reductions of 98% and 33.33% in switching ON and OFF delays respectively in the proposed device-based inverter circuit in comparison to conventional ST-MOSFET based inverter circuit. Furthermore, the proposed ST-MOSFET device does not require any highly doped regions, hence does not have any doping related issues.

This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

A high-performance CMOS, fully balanced second-generation current conveyor (FBCCII) is proposed to exclusively use CCII circuits in integrated circuit applications. In the proposed circuit, a current folding technique is applied to a fully balanced version of transconductance amplifier. The proposed FBCCII consumes 84 $$\upmu $$ W of power and has an open-loop gain of 47.83 dB with 62.9 $$^\circ $$ of phase margin. The simulated input referred noise is 155 nV/ $$\sqrt{\text {Hz}}$$ @ 1 KHz and has a unity gain bandwidth of 39.8 MHz. A common mode feedback (CMFB) circuit is also proposed to improve the dynamic range of the proposed FBCCII circuit by 50 $$\%$$ as compared to the circuit with-out CMFB. The CMFB consumes 170 $$\upmu $$ W of power and has a bandwidth of 60 MHz. The proposed circuit is simulated using standard 180 nm CMOS process operating at $$\pm \,0.5$$ V supply voltage. To verify the effectiveness of the approach, a fully differential variable gain amplifier with tunable gain from 0 to 30 dB is designed. Also, a bandpass filter with quality factor = 4 and bandwidth of 10 MHz is designed using the proposed FBCCII. A novel low-pass filter (LPF) using the proposed FBCCII is designed for bio-medical applications. The proposed LPF is a second-order filter with the cut-off frequency of 55 Hz and 121 nV/ $$\sqrt{\text {Hz}}$$ of input-referred noise. The LPF is designed at a supply voltage of $$\pm \, 0.5$$ V, and the spurious free dynamic range of proposed LPF is 85 dB. The figure of merit of the LPF is 7.3 fJ. The layout area of the proposed FBCCII design is 6889 $$\upmu $$ m $${^2}$$ ( $$83\,\upmu \text {m} \times 83\,\upmu \text {m}$$ ).

We consider the integrated circuit design and the measurement results of test crystals for the 12-bit sigma-delta analog-to-digital converter (ADC) based on 180 nm silicon-on-insulator (SOI) technology from X-FAB. The ADC processes input signals in the frequency range up to 100 kHz in the temperature range of –40…+175 °C with the supply voltage equal to 3.3 V and the modulator clock frequency equal to 10 MHz. The circuit consists of the 5-th order switched-capacitor low-pass pre-filter to limit the input signal spectrum, the cascade connection of the second order sigma-delta modulators, and the digital decimation filter to reduce the clock frequency by 48 times. The main blocks of cutoff filter and modulator are assembled according to the balanced scheme on integrators based on operational transconductance amplifiers with the unity gain bandwidth of 63 MHz. The dynamic element matching circuit is used to expand the dynamic range of converter. It reduces the level of nonlinear distortions in digital-to-analog converters in the feedback circuits of modulator. The value of the SINAD parameter is not worse than 68 dB for converting the signal with the differential amplitude equal to 500 mV at the frequency of 100 kHz.

A new Ge/SiGe heterojunction double-gate tunnel field effect transistor (DGT) model with hetero dielectric gate and Gaussian doping drain region is investigated for the first time. The introduction of heterojunction with hetero dielectric will reduce band-to-band tunneling (BTBT) leakage current while maintaining high mobility to enhance drain current and transconductance characteristics of the device significantly. Along with that, the combined effect of analytical drain doping profile (Gaussian) and hetero dielectric suppresses the ambipolar behavior. Different DC characteristics of the device like energy band analysis, electric field, drain current and BTBT generation rate are analyzed for the proposed structure. RF figure of merit for the HD-HJDGT-GD is express by analyzing its transconductance (gm), cut off frequency (fT), maximum oscillation frequency (fmax), gain bandwidth product (GBP) and transconductance frequency product (TFP). The outcome of the model under study is compared with conventional DGT. It is apparent from the analysis that the recommended model has better DC and RF performance, which makes this device worth studying to be used in high-frequency applications. TCAD simulation is performed by using Sentaurus 2D device simulator from Synopsys.

This paper presents a wideband and highly linear transimpedance amplifier (TIA) with a high-speed, current-efficient transconductance amplifier and multi-order filtering. The proposed TIA employs a Rauch biquad structure and incorporates an operational transconductance amplifier with an improved feedforward frequency compensation in a nested configuration. The Rauch biquad TIA architecture improves the out-of-band (OOB) selectivity, achieving a high OOB IIP3 of the TIA. The proposed feedforward compensation scheme is effective only at high frequencies and thus further enhances the gain bandwidth product of the transconductance amplifier. The current re-use technique improves the power efficiency of the feedforward stage. The prototype circuit was designed in the TSMC 65nm CMOS technology. The TIA achieves a bandwidth of 80 MHz and an OOB IIP3 of 26.8 dBm with a power consumption of 14.2 mW from a supply of 1.8 V while occupying a core area of 0.037 mm2.

A novel raised source and recessed drain dopingless tunneling FET (RSRD-DL-TFET) is proposed in this paper. By using TCAD simulation, the DC electrical characteristics, energy-band diagrams, carrier concentrations and band-to-band tunneling generation rate of RSRD-DL-TFET are analyzed, as compared with planar dopingless tunneling FET (PDL-TFET). Besides, analog/RF and transient performances for both devices are also investigated, including transconductance, parasitic gate capacitance, cut-off frequency, gain bandwidth product and fall propagation delay. Benefiting from the design of raised source and recessed drain, the proposed device not only creates the line tunneling in the source region, but also reduces the ambipolar tunneling distance at drain/channel interface. As a result, the proposed RSRD-DL-TFET could provide higher on-current, steeper subthreshold swing, lower ambipolar current, higher cut-off frequency and better transient performance than PDL-TFET.

Emerging layered semiconductors present multiple advantages for optoelectronic technologies including high carrier mobilities, strong light-matter interactions, and tunable optical absorption and emission. Here, metal-semiconductor-metal avalanche photodiodes (APDs) are fabricated from Bi2O2Se crystals, which consist of electrostatically bound [Bi2O2]2+ and [Se]2− layers. The resulting APDs possess an intrinsic carrier multiplication factor up to 400 at 7 K with a responsivity gain exceeding 3,000 A/W and bandwidth of ~ 400 kHz at a visible wavelength of 515.6 nm, ultimately resulting in a gain bandwidth product exceeding 1 GHz. Due to exceptionally low dark currents, Bi2O2Se APDs also yield high detectivities up to 4.6 × 1014 Jones. A systematic analysis of the photocurrent temperature and bias dependence reveals that the carrier multiplication process in Bi2O2Se APDs is consistent with a reverse biased Schottky diode model with a barrier height of ~ 44 meV, in contrast to the charge trapping extrinsic gain mechanism that dominates most layered semiconductor phototransistors. In this manner, layered Bi2O2Se APDs provide a unique platform that can be exploited in a diverse range of high-performance photodetector applications.

This paper presents a quantum analytical modeling of UTBB SOIMOSFET as lateral dual gate for the first time. In this paper, a 2-dimensional analytical modeling of electric field distribution, threshold voltage (Vth), surface potential and drain current (ID) have been developed and then including Quantum mechanical effects (QMEs)in it. The proposed model provides an expression for Vth shift due to QMEs, which can be used for compact modeling as a quantum correction term. The results of quantum analytical modeling have been verified with the results achieved from numerical TCAD device simulator. Different analog/ radio frequency (RF) performance parameters like transconductance (gm), output resistance (RO), transconductance generation factor (TGF), intrinsic gain (gm*RO), cut-off frequency (fT), gain bandwidth product (GBW), maximum frequency of oscillation (fmax) etc. has been investigated. The effect of negative voltage on the control gate on RF/analog performance parameters has been studied. Result reveals that the potential of UTTB SOI MOSFET with lateral dual gate becomes a choice for analog and mixed signal SOC applications.

This paper reports an unique approach to suppress ambipolarity and enhance drive current in tunnel field effect transistor (TFET) by incorporating vertically extending drain in double gate Si1−xGex source TFET. This structure has dual source extending laterally on both sides of the channel with vertically extended drain over the T-shaped channel (VD-DG-Si1−xGexS-TFET). Our study is based on calibrated exhaustive 2-D TCAD simulations. It advocates that the device performance is not only retained but significantly enhanced even by deploying only double gate instead of quadruple gate with Si1−xGex sources. Further the drive current can be significantly increased by optimizing the mole fraction (x) in Si1−xGex source. Our study reveals that the average subthreshold slope (SSavg) is 23.98 m V/dec (point SS (SSpoint) is 12.7 m V/dec with sub-60 m V/dec point SS for 107 orders of current change), drive current (ION) is 2.73× 10− 4 A/um and 46% improvement in transconductance as compared to the earlier reported drain engineered quardruple gate TFET. Further the device sensitivity analysis with respect to gate oxide dielectric constant, gate metal work-function, temperature and germanium mole fraction variation is also analyzed here. Moreover, in terms of device analog behaviour, the cut off frequency (ft) is reported as 38.93 GHz and 140% increment in gain bandwidth product (GWB) as compared to its quardruple gate alternative. This study proves the potentials of considered device structure as a promising candidate for ultra low power analog/RF and digital logic applications.

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have large gain bandwidth product (GBP) and low excess noise due to the low impact ionization coefficient ratio of silicon. Optical receivers using APDs are able to achieve high-speed and energy efficient optical transceiver systems. We demonstrate a waveguide Si-Ge APD with low breakdown voltage of −10 V, achieving 60 Gb/s PAM4 successfully. A compact APD circuit model was constructed to allow photonic devices and transceiver circuitry co-design. The APD receiver has achieved −16 dBm sensitivity at 50 Gb/s PAM4 with a bit error rate (BER) of 2.4 $\times \,10^{-4}$ . The sensitivity of APD receivers changes with the multiplication gain. In our analysis, compared to a PIN PD receiver the APD receiver operating at optimum gain can obtain $\sim$ 8 dB more sensitivity for NRZ signaling at $ 50 Gb/s and 3–4 dB more sensitivity for PAM4 signaling at 50–100 Gb/s. Also, the APD receiver operating at optimum gain can reduce power consumption by $\sim\!\text{10}\%$ at PAM4 data rates of 50 Gb/s and $\sim\!\text{15}\%$ at 100 Gb/s in a silicon carrier-depletion microring modulator based WDM photonic link.

Design and simulation of an improved recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The new idea is based on minor changes in the conventional structure. Our improved amplifier is capable to enhance DC gain and unity gain bandwidth (UGBW) in the same −3dB frequency as for RFC structure. Moreover, fast-settling time, input-referred noise, total harmonic distortion (THD) and performances of power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) are also improved. Simulation results in 90 nm CMOS process indicate that the proposed amplifier has about 2 times the unity gain bandwidth (360 versus 175 MHz) and also has twice gain boosting (68.6 versus 62.5 dB) in the same −3 dB frequency and capacitor load of 10 pF @1.2 V power supply. The results also demonstrate a good figure of merit (FOM), and low sensitivity of temperature and power supply variations for the proposed amplifier.

This study introduces the design of a practical three-stage operational amplifier (op-amp) using nested Miller compensation, particularly for piezoelectric actuators. Driving a piezoelectric actuator represents a challenge in amplifier design due to its large capacitive nature. A stable piezo driver needs to be free of oscillations and phase lag. Direct feedback compensation using a conventional Miller capacitor is an effective method as long as the capacitance of the load is considerably close to the value of the Miller capacitor. However, using a large capacitor causes a decrease in the slew rate and gain bandwidth. To avoid this, our design focused on the utilization of nested Miller compensation technique. A prototype of the design working at 100V peak to peak voltage (Vpp) is implemented using commercial off-the-shelf (COTS) components. The measurements show the successful driving capability and step-response of the op-amp design. In the design, Widlar current source is also utilized for thermal stability and short circuit protection. According to simulation results, the proposed op-amp has a slew rate of 0.5 V/μs, an open loop gain of 90dB with 3MHz Gain Bandwidth Product (GBP) and phase margin of 77°, and a common mode rejection ratio (CMRR) of 62dB.

In this article, we propose an extended-source double-gate tunnel field-effect transistor (ESDG-TFET) to enhance the dc and analog/RF performance. The source of an ESDG-TFET is extended into channel to increase the line and point tunneling in the device at the source–channel junction. 2-D simulations in the TCAD tool (ATLAS) are carried out to analyze and investigate the performance of the proposed device. At optimized device structural parameters, the ESDG-TFET provides a low threshold voltage of 0.42 V, a low subthreshold swing of 12.24 mV/decade, and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of $2.57\times 10^{{12}}$ . Furthermore, the proposed device achieves a maximum transconductance of 238 $\mu \text{S}/\mu \text{m}$ , a cutoff frequency of 37.7 GHz, and a gain bandwidth product of 3.4 GHz.

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance ( g m ) cut-off frequency ( f T ) , gain bandwidth product and maximum oscillating frequency ( f max ) . Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

This letter presents a high-gain energy-efficient three-stage amplifier, which employs buffering-based pole relocation and dual-path structure. The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth (GBW) of the local feedback loop (LFL). Compared to the topologies using active-zero insertion, the 3rd pole is formed with a much smaller capacitance (parasitic capacitance), enabling it to be placed at a significantly higher frequency while consuming lower power. Moreover, the parasitic pole at the main path is bypassed by using an auxiliary path. Thus, the 3rd pole can be pushed to a higher frequency more easily than the topologies using an active zero. As a result, the GBW of the LFL in the proposed work is less limited. The proposed design improves the state-of-the-art FOM L by 36%, LC-FOM S by 26%, and LC-FOM L by 218%, while preserving robustness of the performance.

We examine the performance of a Josephson Parametric Amplifier (JPA) which uses an array of SNAILs (Superconducting Nonlinear Asymmetric Inductive eLements) as the source of nonlinearity and leverages the technique of impedance engineering (introducing a positive linear slope in the imaginary part of the input impedance seen by the SNAILs) to overcome a traditional gain-bandwidth product and increase the 1-dB compression point. We experimentally demonstrate an 18 dB gain over a 586 MHz band, along with a 1-dB compression point -101.9 dBm. All these characteristics are of great importance for the quantum devices measurements and in particular for the single-shot readout of a multi-qubit system. The signal-to-noise ratio after the application of the JPA was increased by 3 times. That led to the improvement of separation fidelity of single-shot dispersive measurements of a transmon qubit from 30.6% to 97.2%., В данной работе исследуется применение широкополосного джозефсоновского параметрического усилителя на основе сверхпроводящих нелинейных асимметричных индуктивных элементов SNAIL в качестве источника нелинейности и с использованием техники трансформации импеданса (введение частотной зависимости мнимой части входного импеданса) для увеличения gain-bandwidth product и мощности насыщения. Были экспериментально продемонстрированы коэффициент усиления 18 дБ в полосе 586 МГц и мощность насыщения -101.9 дБм. Эти характеристики очень важны для измерений квантовых устройств, и в частности для проективного считывания многокубитной системы. Благодаря использованию усилителя отношение сигнал-шум измерительной цепи было увеличено в три раза. Это привело к улучшению точности погрешности разделения состояний проективного дисперсионного считывания кубита-трансмона с 30.6% до 97.2%.

Obtaining a photomultiplication-type organic photodiode with a high gain–bandwidth product is challenging. We show that a newly designed regioregular polymer enables the formation of a highly oriented face-on structure with a low trap density, leading to a high EQE and a fast response time. As a result, a gain–bandwidth product of over 4 × 105 Hz is achieved.

This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamp) with Miller compensation, using a third stage that acts as output buffer to drive large loads. The TSMC 0.18μm PDK was used for the design, simulation and implementation in Cadence Virtuoso. The opamp exhibits 20μW power consumption with a 1-V rail-to-rail supply. Post layout simulation shows a unity gain bandwidth (UGBW) of 69.18 MHz $(A_{v}=\mathbf{49.63dB})$ with a phase margin (PM) larger than 86° and a Slew rate of $19.87\mu\mathrm{V}_\mathrm{s}$ ; making our design suitable for small and large signal applications.

The paper presents a dual low voltage chopper offset-stabilized operational amplifier with symmetrical RC notch filters, having a 1.6-5.5 V supply range, and being fabricated in a 0.25 µm CMOS process. The chopping frequency is 100 kHz. A new constant-gm technique is implemented within the input stage of main amp, improving most electrical performances. The amplifier has a typical offset voltage of 1 µV, a minimum PSRR of 128 dB, a minimum CMRR of 120 dB, a noise PSD of 42 nV/√Hz, 1.5 MHz unity gain bandwidth, and THD + noise of 0.001 % at 1 kHz, while consuming 70 µA per channel.

This study presents a systematic review of junctionless tunnel field effect transistor (JLTFET)–based homo- and hetero-based devices/circuits which have gained significant popularity in recent years for their performance. The divergent ranges of JLTFET-based structures are explored, and their DC/AC characteristics are discussed in detail. Basically JLTFET device exploits the advantages of both junctionless FET (JLFET) and tunnel FET (TFET) together to vanquish the major challenges that are faced by contemporary FETs. The hetero JLTFETs studied in this review uses lower band gap materials, silicon and SiXGeX-1 and high band gap material, AlGaAsat source and channel side, respectively. Also dual material gate structure in hetero JLTFET is explored for their performance improvement. Both homo and hetero structures exhibit better performance in terms of DC parameters, subthreshold slope (SS), ON-current, OFF-current and electron tunnelling rate, whereas AC parameters include unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), gain bandwidth product (GBW), transconductance generation factor (TGF) and delay. The silicon-on-nothing (SON) technology–based JLTFET is studied for the performance improvement by using different dielectric materials. With respect to circuit-related study, JLTFET uses SiGeN + pocket under the gate region which act as an inverter circuit with good transient and voltage transfer characteristics (VTC). For memory circuits like SRAM, JLTFET shows better performance in terms of hold static noise margin (SNM), read SNM and write SNM.

Owing to the transition metal dichalcogenides strong light-matter interaction and distinctive materials properties. But low carrier mobilities limited the performance of the device. Here we demonstrate an efficient plasmonic slot photodetector based on integrating MoTe2 in silicon photonics. Narrowing the source-drain distance to tens of nm enables high gain-bandwidth-product detectors.