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International audience; AlN nucleation layers are the basement of GaN-on-Si structures grown for light-emitting diodes, high frequency telecommunication and power switching systems. In this context, our work aims to understand the origin of propagation losses in GaN-on-Si High Electron Mobility Transistors at microwaves frequencies, which are critical for efficient devices and circuits. AlN/Si structures are grown by Metalorganic Vapor Phase Epitaxy. Acceptor dopant in-diffusion (Al and Ga) into the Si substrate is studied by Secondary Ion Mass Spectroscopy and is mainly located in the first 200 nm beneath the interface. In this region, an acceptor concentration of a few 1018cm-3 is estimated from Capacitance-Voltage (C-V) measurements while the volume hole concentration of several 1017 cm-3 is deduced from sheet resistance. Furthermore, the combination of scanning capacitance microscopy and scanning spreading resistance microscopy enables the 2D profiling of both the p-type conductive channel and the space charge region beneath the AlN/Si interface. We demonstrate that samples grown at lower temperature exhibit a p-doped conductive channel over a shallower depth which explains lower propagation losses in comparison with those synthesized at higher temperature. Our work highlights that this p-type channel can increase the propagation losses in the high-frequency devices but also that a memory effect associated with the previous sample growths with GaN can noticeably affect the physical properties in absence of proper reactor preparation. Hence, monitoring the acceptor dopant in-diffusion beneath the AlN/Si interface is crucial for achieving efficient GaN-on-Si microwave power devices.

International audience; Herein, the interest of cubic silicon carbide as a template for the growth of AlGaN/ GaN high electron mobility transistor (HEMT) heterostructures on silicon substrates for high-frequency operation is shown. On the one hand, 0.6-0.8 μm-thick 3C-SiC grown by chemical vapor deposition on intrinsic silicon substrate having initial resistivity superior to 5 kΩ cm enables the metalorganic vapor phase epitaxy of GaN buffer layers with propagation losses below 0.4 dB mm À1 at 40 GHz and 0.5 dB mm À1 at 67 GHz. On the other hand, an HEMT heterostructure is grown on 1.5 μm-thick 3C-SiC on 4 off-axis silicon substrate having an initial resistivity superior to 200 Ω cm that allows to keep a sufficiently resistive epilayer stack limiting the loss up to 0.78 dB mm À1 at 40 GHz. Device process developed on a piece of the 100 mm diameter wafer leads to the demonstration of DC transistor operation with low leakage currents. Compared with direct growth on silicon, these templates enable reduced radio frequency (RF) propagation losses that are very interesting for high-frequency transistors and circuits operation.

Plasma etching for sub 14nm technological nodes require a precise control of the etching of thin nanometer-sized layers, while controlling the lateral dimension of nanometer-scale structures. For spacers etching, the 3 mains challenges appear. The first is to obtain high selectivity of the spacer’s materials with respect to silicon or silicon germanium. The use of a chemistry with a stop layer on silicon is prohibited because of the dimensional constraints. The order of the layers to be etched is of 5nm to 6nm and the thickness of the reactive layer is of 3nm. The second challenge is the control of the damaged induced by the plasma on the silicon layer and their effects on the electrical performances. Moreover, an epitaxial growth is used differentiate the NMOS and PMOS zones. This technique is very sensitive to the surface state condition and the contamination. The silicon layer should be as intact as possible. The last challenge is the control of the hard mask consumption or the spacer height. It can lead to an epitaxial growth preventing the transistors realization.Preliminary studies have shown that the use of a bias pulsed plasma coupled with the adding of tetrachlorosilane SiCl4 allows to reduce the consumption and the damaged induced of the silicon layer. We will study the new process window obtained, as well as the impact of this new process on the electrical performances of the integrated circuits.A second part of the study will focus on a new approach for the spacers etching. It consists initially in modifying the layer that we want to remove by a light ion plasma in a conventional etching reactor. The modified layer is then remove selectively to the unmodified layer by a hydrofluoric acid. We performed FTIR, XPS et SIMS analyses to characterize the modified materials and to understand the etching mechanisms.Finally, we will evaluate the compatibility of these processes with the etching of a low-k material: SiCO., Les gravures par plasma pour les technologies sub 14nm nécessitent de bien contrôler la gravure de couches très minces de l’ordre du nanomètre, tout en contrôlant la dimension latérale des structures gravées au nanomètre près. Pour les gravures espaceurs, 3 nouveaux défis apparaissent. Le premier est d’obtenir une grande sélectivité des matériaux utilisés par rapport au silicium car l’utilisation de couches d’arrêt est proscrite du fait des contraintes dimensionnelles. Les couches à graver deviennent très fines de l’ordre de 5nm à 6nm, et l’épaisseur de la couche réactive est de 3 nm. Le second défi est le contrôle des dommages induits par le plasma sur la couche silicium leurs effets sur les performances du transistor. De plus pour différencier les zones NMOS et PMOS nous utilisons des croissances sur le silicium par épitaxie. Cette technique est très sensible à l’état de surface et à la contamination. Il faut donc laisser une couche de silicium le plus intact possible. Le dernier est le contrôle du retrait du masque dur et de la hauteur des espaceurs. Cela peut entraîner une épitaxie parasite empêchant la réalisation des transistors.Des études préliminaires ont montré l’intérêt d’utiliser des plasmas à bias pulsé couplé à un ajout de tétrachlorure de silicium afin de réduire la consommation et l’endommagement de la couche de silicium. Nous proposons d’évaluer la nouvelle fenêtre de procédé obtenue ainsi que l’impact de ce procédé sur les performances électriques des circuits-intégrés.Une seconde partie de l’étude sera consacré à l’étude d’une approche novatrice de la gravure des espaceurs. Elle consiste dans un premier temps à modifier la couche que nous voulons retirer par un plasma d’ions légers dans un réacteur de gravure conventionnel. Ce plasma implanté est ensuite retiré sélectivement au plasma non modifié par un bain d’acide fluorhydrique. Nous utiliserons des analyses FTIR, XPS et SIMS afin de caractériser les matériaux modifiés et de comprendre les mécanismes de gravure.Enfin nous évaluerons la compatibilité de ces procédés avec la gravure d’un matériau à basse permittivité : le SiCO.