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Cellular networks present high latencies,especially in the Radio Acccess Network (RAN). The new generation of cellular technology 5G, in addition to increasing transmission throughput, must offer low latency in mobile connectivity. The objective of this thesis is to propose mechanisms for reducing latency in the RAN. In this perspective, we set up a software-defined RAN experimentation platform based on the OpenAirInterface project and designed a tool for fine-grained measurement of RAN internal latencies called LatSeq. We show that the round-time trip latency typically reaches 30 ms in LTE divided between processing, queueing, retransmission and medium acquisition delays. We also measure a significant jitter on the uplink that affects the RAN latency but also the performance of TCP traffics,which are very common on the Internet. LatSeq highlights the role of the radio resource allocation mechanism in the jitter and latency of the uplink channel. We show how the partial knowledge of the transmission buffer length by the scheduling algorithm from Buffer Status Reports (BSRs) and Scheduling Requests (SRs) induces bursts of transmissions, significant jitter and under-utilization of the radio channel capacity. We then propose a new mechanism for estimating the terminal transmission buffer length which is compatible with 3GPP LTE and 5G standards. We demonstrate that this method makes it possible to reduce the latency of the uplink channel and even more the jitter experienced by packet flows; Les réseaux cellulaires présentent des latences importantes, en particulier au niveau du réseaux d’accès radio (RAN). La nouvelle génération de technologie cellulaire 5G, en plus d’augmenter les débits de transmission, doit offrir de faibles latences en connectivité mobile. L’objectif de cette thèse est de proposer des mécanismes de réduction de la latence dans le RAN. Dans cette perspective, nous avons mis en place une plateforme d’expérimentation software-defined RAN basée sur le projet OpenAirInterface et conçu un outil de mesure fine des latences internes au RAN appelé LatSeq. Nous montrons que la latence aller-retour atteint typiquement 30 ms en LTE répartie entre délais de traitement, de mis en file d’attente, de retransmissions et d’acquisition du medium. Nous avons aussi mesuré une gigue importante sur la voie remontante qui influe sur la latence du RAN mais aussi sur les performances des trafics TCP, très répandus sur Internet. LatSeq met en évidence le rôle du mécanisme d’allocation des ressources radio dans la gigue et la latence de la voie remontante. Nous montrons comment la connaissance imparfaite de la taille du buffer de transmission par l’algorithme d’ordonnancement à partir des rapports Buffer Status Reports (BSR) et des demandes d’accès (SR) induit une transmission par rafale, une gigue importante et une sous-utilisation de la capacité du canal radio. Nous proposons alors un nouveau mécanisme d’estimation de la taille du buffer de transmission des terminaux compatible avec les standards 3GPP LTE et 5G, et démontrons que cette méthode permet de réduire la latence de la voie remontante et la gigue subie par les flux de paquets.

Media production for professional broadcast (i.e., the process by which multiple audiovisual sources are mixed and processed, in real-time, to elaborate the audiovisual stream as it will be consumed by the final viewer) has currently been implemented with dedicated hardware equipment, based on the Serial Digital Interface (SDI), an interconnection technology carrying the legacy of analog video. Despite an ongoing industrial effort to replace SDI with IP-based interconnection --- as specified by the SMPTE 2022-6 and 2110 standards --- the delay-sensitive nature of media production still challenges its total transition to software running on commodity servers. This thesis solves different aspects of that problem.First a quantitative and qualitative study of the sources of jitter undergone by those streams upon software processing has been conducted. In addition to results specific to Linux x86_64 servers, that work has yielded a general jitter exploration methodology, applicable to any operating system and hardware commodity servers.Second, a generic platform enabling the implementation of custom high-accuracy instrumentation for hardware-based packet timestamping has been developed. Despite being FPGA-based, that platform allows network and broadcast operators with little hardware design skills to specify custom logic for line-rate packet processing and timestamping, by using the P4 language. In particular, such instrumentation can be used to qualify the jitter properties of media production streams.Third, a system to perform packet-pacing --- i.e., the transmission of a constant-rate packet stream with negligible jitter --- has been proposed. Despite exclusively relying on commodity hardware, the proposed system has been formally and experimentally proven to yield a jitter, conforming to the tight requirements of media production streams.Finally, a software framework easing the implementation of media-production applications has been developed. That framework relies on a separation between media processing and media transport. The transport layer handles high-performance packet processing with techniques such as zero-copy and kernel bypass networking., La production de média pour la diffusion audiovisuelle (i.e., le processus par lequel plusieurs sources audiovisuelles sont mélangées et traitées en temps réel pour élaborer le flux consommé par le téléspectateur) est généralement implémentée par du matériel dédié, basé sur la Serial Digital Interface (SDI), une technologie d'interconnection dérivé de la télévision analogique. Malgré l'effort industriel présent pour remplacer le SDI par de l'IP (ainsi que spécifié par les standards SMPTE 2022-6 et 2110) la sensibilité au délai de la production de média rend difficile une transition totale vers un traitement logiciel sur des serveurs générique. Cette thèse résout different aspects de ce problème.Premièrement, il a été conduit une étude quantitative et qualitative de la gigue subie par ces flux lors d'un traitement logiciel. Au delà de résultats obtenus pour des serveurs Linux x86_64, il a été dérivé une méthodologie générale, applicable à tout système d'exploitation et architecture matérielle, permettant d'étudier la gigue introduite.Deuxièmement, une plateforme générique a été proposé afin de permettre la réalisation de système d'instrumentation personnalisé, pour l'horodatage précis de packet réseaux. Bien qu'étant basée sur la technologie des FPGA, cette plateforme permet à tout opérateur réseau ou de diffusion audiovisuelle de spécifier une logique d'horodatage personnalisée en utilisant le langage P4. Cela permet en particulier la conception d'une instrumentation pour la qualification de flux média.Troisièmement, un système de lissage de traffic (packet-pacing) a été proposé, afin de permettre l'envoi de flux de paquets avec une gigue négligeable. Malgré un emploi exclusif de matériel générique, il a été prouvé formellement et expérimentalement que la gigue ainsi obtenue était suffisamment faible pour des flux média.Finalement, un cadre logiciel facilitant l'écriture d'applications de traitement média a été proposé. Ce cadre repose sur la séparation entre le traitement et le transport des flux média, la couche de transport s'occupant du traitement haute performance des paquets réseaux par l'emploi de techniques comme le zero-copy, ou le kernel-bypass.

Random numbers are essential for modern cryptographic systems. They are used as cryptographic keys, nonces, initialization vectors and random masks for protection against side channel attacks. In this thesis, we deal with random number generators in logic devices (Field Programmable Gate Arrays – FPGAs and Application Specific Integrated Circuits – ASICs). We present fundamental methods of generation of random numbers in logic devices. Then, we discuss different types of TRNGs using clock jitter as a source of randomness. We provide a rigorous evaluation of various AIS-20/31 compliant TRNG cores implemented in three different FPGA families : Intel Cyclone V, Xilinx Spartan-6 and Microsemi SmartFusion2. We then present the implementation of selected TRNG cores in custom ASIC and we evaluate them. Next, we study PLL-TRNG in depth in order to provide a secure design of this TRNG together with embedded tests. Finally, we study oscillator based TRNGs. We compare different randomness extraction methods as well as different oscillator types and the behavior of the clock jitter inside each of them. We also propose methods of embedded jitter measurement for online testing of oscillator based TRNGs.; Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour la protection contre les attaques par canaux cachés. Dans cette thèse, nous traitons des générateurs de nombres aléatoires dans les circuits logiques (FPGA et ASIC). Nous présentons les méthodes fondamentales de génération de nombres aléatoires dans des circuits logiques. Ensuite, nous discutons de différents types de TRNG en utilisant le jitter d’horloge comme source d’aléa. Nous faisons une évaluation rigoureuse de divers noyaux TRNG conformes à la norme AIS-20/31 et mis en œuvre dans trois familles de FPGA différentes: Intel Cyclone V, Xilinx Spartan-6 et Microsemi SmartFusion2. Puis, nous présentons l’implémentation des noyaux TRNG sélectionnés dans des ASIC et leur évaluation. Ensuite, nous étudions en profondeur PLL-TRNG afin de fournir une conception sécurisée de ce TRNG ainsi que des tests intégrés. Enfin, nous étudions les TRNG basés sur les oscillateurs. Nous comparons de différentes méthodes d'extraction d’aléa ainsi que de différents types d'oscillateurs et le comportement du jitter d'horloge à l'intérieur de chacun d'eux. Nous proposons également des méthodes de mesure du jitter intégrée pour le test en ligne des TRNG basés sur les oscillateurs.

As the world becomes more and more connected, the need for higher data throughput becomes increasingly urgent. This implied more creativity from circuit designers to come up with higher bandwidth circuits and faster pace clocks to drive them.However, the traditional microelectronics clock circuits fail short to fulfill the ever-increasing need for higher sampling frequencies because of their inherent noise. The latter renders the sampled data altogether unusable and therefore hinders the efforts towards higher streams of data.Integrated photonics, the optics alternative to microelectronics, may bring an end to this problem. Indeed, when it comes to pulsed lasers, a not that new technology, the optical pulses clocking features a very low noise compared to its microelectronics counterpart, i.e a jitter that is five folds lower than the best literature microelectronics clock.The main idea of this thesis is to design a sampling circuit that uses the laser pulses as a clock, but samples an electronic signal. This circuit design is mainly based on the use of a Germanium photoconductor, i.e, a Germanium resistor that changes its resistance according to the value of the optical signal it receives. This photoconductor plays then the role of a clocked switch and connects the RF input signal to the hold capacitor. When the switch receives a pulse of light, its resistance drops and the signal can be copied to the capacitor, and once the pulse of light is over, the Germanium photoconductor recovers its first resistance value and the input signal node is disconnected from the capacitor that holds the sampled signal.The aim of this thesis is to study the feasibility of such a design and whether or not it allows taking advantage of the very low jitter value of the laser. Within the thesis, we tried to implement the up said design and stumbled upon many challenges. First, the values of the off switch resistance were not high enough to disconnect the hold capacitor from the input node due to the low resistivity of the used Germanium (residual doping). The Germanium implies also that the switching from one resistance value to another is not instantaneous but rather as long as the photo-generated carriers exist, which lasts for at least a nanosecond. We resolved these problems using three methods: a novel geometry of Germanium photoconductors that allows for high Roff/Ron ratios (patented geometry), a counter-doping to increase the resistivity of the material and finally, a re-sampling circuit driven by a photonic clock based on the laser pulses. We also explored the possibility of making very steep-edged clocks with customizable pulse lengths based on the laser pulses.; Dans un monde de plus en plus connecté, il devient indispensable de trouver des moyens d’augmenter le débit d’informations qu’il est possible de véhiculer et de traiter. Ce besoin impose aux ingénieurs des contraintes plus serrées en termes de bande passante et de fréquence d’horloge des circuits qu’ils conçoivent.Or, les circuits d’horloge en microélectroniques sont limités par leur performance en termes de stabilité de la période d’horloge, i.e., en termes de « gigue d’horloge » ; cette limitation provient du bruit inhérent au circuit des horloges et rend donc le signal échantillonné inexploitable.Un moyen de se libérer de cette contrainte pourrait être de passer par la photonique intégrée. En effet, les horloges optiques, i.e les lasers pulsés, présentent des performances très intéressantes en termes de stabilité ou de gigue en comparaison avec les horloges en microélectroniques: les gigues des horloges optiques sont cinq fois plus faibles que la plus faible gigue d’horloge électronique citée dans la littérature.L’idée principale de cette thèse est de concevoir un circuit d’échantillonnage qui utilise les pulses du laser comme horloge et qui échantillonne un signal électronique. La brique de base du circuit en question est un photoconducteur en Germanium : une résistance en Germanium dont la résistivité varie selon la puissance du signal optique qu’elle reçoit du laser pulsé. Le photoconducteur dans ce cas précis jour le rôle d’un interrupteur piloté par le laser, et connecte l’entrée RF à la capacité d’échantillonnage. Quand l’interrupteur reçoit un pulse de lumière sa résistance chute et le signal RF peut être copié vers la capacité. Dès que le pulse de lumière s’arrête, le photoconducteur en Germanium retrouve sa résistance initiale et déconnecte ainsi l’entrée RF de la capacité qui contient le signal échantillonné.Cette thèse se propose d’étudier la faisabilité d’un tel circuit et la possibilité d’exploiter la performance des lasers en termes de stabilité de l’horloge dans l’échantillonnage d’un signal électrique.Dans le cadre de la thèse, nous avons essayé d’implémenter le circuit de base présenté auparavant et avons rencontré plusieurs défis. D’abord, les valeurs des résistances Off du photoconducteur n’étaient pas assez élevées pour permettre de déconnecter entièrement le signal RF de la capacité d’échantillonnage. Cela est dû à la présence d’un dopage résiduel lié au procédé de fabrication des photoconducteurs. L’utilisation du Germanium implique également que le passage de l’état On à l’état Off du photoconducteur n’est pas instantané, mais est fonction de la durée de vie des porteurs de charge créés suite à l’exposition aux pulses de lumière (de l’ordre de la nanoseconde).Nous avons contourné ces problèmes en utilisant trois méthodes : une nouvelle géométrie des photoconducteurs en Germanium qui permet de maximiser le rapport Roff/Ron (géométrie brevetée), un contre-dopage pour augmenter la résistivité du matériau et finalement un circuit électronique qui permet de re-échantillonner le signal en utilisant une horloge photonique basée sur les pulses du laser. Nous avons également exploré la possibilité de concevoir des horloges photoniques qui présentent une très faible valeur de gigue et dont la longueur du pulse peut être modifiée de manière indépendante de la longueur du pulse laser utilisé pour les générer.

Random numbers are essential for modern cryptographic systems. They are used as cryptographic keys, nonces, initialization vectors and random masks for protection against side channel attacks. In this thesis, we deal with random number generators in logic devices (Field Programmable Gate Arrays – FPGAs and Application Specific Integrated Circuits – ASICs). We present fundamental methods of generation of random numbers in logic devices. Then, we discuss different types of TRNGs using clock jitter as a source of randomness. We provide a rigorous evaluation of various AIS-20/31 compliant TRNG cores implemented in three different FPGA families : Intel Cyclone V, Xilinx Spartan-6 and Microsemi SmartFusion2. We then present the implementation of selected TRNG cores in custom ASIC and we evaluate them. Next, we study PLL-TRNG in depth in order to provide a secure design of this TRNG together with embedded tests. Finally, we study oscillator based TRNGs. We compare different randomness extraction methods as well as different oscillator types and the behavior of the clock jitter inside each of them. We also propose methods of embedded jitter measurement for online testing of oscillator based TRNGs., Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour la protection contre les attaques par canaux cachés. Dans cette thèse, nous traitons des générateurs de nombres aléatoires dans les circuits logiques (FPGA et ASIC). Nous présentons les méthodes fondamentales de génération de nombres aléatoires dans des circuits logiques. Ensuite, nous discutons de différents types de TRNG en utilisant le jitter d’horloge comme source d’aléa. Nous faisons une évaluation rigoureuse de divers noyaux TRNG conformes à la norme AIS-20/31 et mis en œuvre dans trois familles de FPGA différentes: Intel Cyclone V, Xilinx Spartan-6 et Microsemi SmartFusion2. Puis, nous présentons l’implémentation des noyaux TRNG sélectionnés dans des ASIC et leur évaluation. Ensuite, nous étudions en profondeur PLL-TRNG afin de fournir une conception sécurisée de ce TRNG ainsi que des tests intégrés. Enfin, nous étudions les TRNG basés sur les oscillateurs. Nous comparons de différentes méthodes d'extraction d’aléa ainsi que de différents types d'oscillateurs et le comportement du jitter d'horloge à l'intérieur de chacun d'eux. Nous proposons également des méthodes de mesure du jitter intégrée pour le test en ligne des TRNG basés sur les oscillateurs.

As the world becomes more and more connected, the need for higher data throughput becomes increasingly urgent. This implied more creativity from circuit designers to come up with higher bandwidth circuits and faster pace clocks to drive them.However, the traditional microelectronics clock circuits fail short to fulfill the ever-increasing need for higher sampling frequencies because of their inherent noise. The latter renders the sampled data altogether unusable and therefore hinders the efforts towards higher streams of data.Integrated photonics, the optics alternative to microelectronics, may bring an end to this problem. Indeed, when it comes to pulsed lasers, a not that new technology, the optical pulses clocking features a very low noise compared to its microelectronics counterpart, i.e a jitter that is five folds lower than the best literature microelectronics clock.The main idea of this thesis is to design a sampling circuit that uses the laser pulses as a clock, but samples an electronic signal. This circuit design is mainly based on the use of a Germanium photoconductor, i.e, a Germanium resistor that changes its resistance according to the value of the optical signal it receives. This photoconductor plays then the role of a clocked switch and connects the RF input signal to the hold capacitor. When the switch receives a pulse of light, its resistance drops and the signal can be copied to the capacitor, and once the pulse of light is over, the Germanium photoconductor recovers its first resistance value and the input signal node is disconnected from the capacitor that holds the sampled signal.The aim of this thesis is to study the feasibility of such a design and whether or not it allows taking advantage of the very low jitter value of the laser. Within the thesis, we tried to implement the up said design and stumbled upon many challenges. First, the values of the off switch resistance were not high enough to disconnect the hold capacitor from the input node due to the low resistivity of the used Germanium (residual doping). The Germanium implies also that the switching from one resistance value to another is not instantaneous but rather as long as the photo-generated carriers exist, which lasts for at least a nanosecond. We resolved these problems using three methods: a novel geometry of Germanium photoconductors that allows for high Roff/Ron ratios (patented geometry), a counter-doping to increase the resistivity of the material and finally, a re-sampling circuit driven by a photonic clock based on the laser pulses. We also explored the possibility of making very steep-edged clocks with customizable pulse lengths based on the laser pulses., Dans un monde de plus en plus connecté, il devient indispensable de trouver des moyens d’augmenter le débit d’informations qu’il est possible de véhiculer et de traiter. Ce besoin impose aux ingénieurs des contraintes plus serrées en termes de bande passante et de fréquence d’horloge des circuits qu’ils conçoivent.Or, les circuits d’horloge en microélectroniques sont limités par leur performance en termes de stabilité de la période d’horloge, i.e., en termes de « gigue d’horloge » ; cette limitation provient du bruit inhérent au circuit des horloges et rend donc le signal échantillonné inexploitable.Un moyen de se libérer de cette contrainte pourrait être de passer par la photonique intégrée. En effet, les horloges optiques, i.e les lasers pulsés, présentent des performances très intéressantes en termes de stabilité ou de gigue en comparaison avec les horloges en microélectroniques: les gigues des horloges optiques sont cinq fois plus faibles que la plus faible gigue d’horloge électronique citée dans la littérature.L’idée principale de cette thèse est de concevoir un circuit d’échantillonnage qui utilise les pulses du laser comme horloge et qui échantillonne un signal électronique. La brique de base du circuit en question est un photoconducteur en Germanium : une résistance en Germanium dont la résistivité varie selon la puissance du signal optique qu’elle reçoit du laser pulsé. Le photoconducteur dans ce cas précis jour le rôle d’un interrupteur piloté par le laser, et connecte l’entrée RF à la capacité d’échantillonnage. Quand l’interrupteur reçoit un pulse de lumière sa résistance chute et le signal RF peut être copié vers la capacité. Dès que le pulse de lumière s’arrête, le photoconducteur en Germanium retrouve sa résistance initiale et déconnecte ainsi l’entrée RF de la capacité qui contient le signal échantillonné.Cette thèse se propose d’étudier la faisabilité d’un tel circuit et la possibilité d’exploiter la performance des lasers en termes de stabilité de l’horloge dans l’échantillonnage d’un signal électrique.Dans le cadre de la thèse, nous avons essayé d’implémenter le circuit de base présenté auparavant et avons rencontré plusieurs défis. D’abord, les valeurs des résistances Off du photoconducteur n’étaient pas assez élevées pour permettre de déconnecter entièrement le signal RF de la capacité d’échantillonnage. Cela est dû à la présence d’un dopage résiduel lié au procédé de fabrication des photoconducteurs. L’utilisation du Germanium implique également que le passage de l’état On à l’état Off du photoconducteur n’est pas instantané, mais est fonction de la durée de vie des porteurs de charge créés suite à l’exposition aux pulses de lumière (de l’ordre de la nanoseconde).Nous avons contourné ces problèmes en utilisant trois méthodes : une nouvelle géométrie des photoconducteurs en Germanium qui permet de maximiser le rapport Roff/Ron (géométrie brevetée), un contre-dopage pour augmenter la résistivité du matériau et finalement un circuit électronique qui permet de re-échantillonner le signal en utilisant une horloge photonique basée sur les pulses du laser. Nous avons également exploré la possibilité de concevoir des horloges photoniques qui présentent une très faible valeur de gigue et dont la longueur du pulse peut être modifiée de manière indépendante de la longueur du pulse laser utilisé pour les générer.

The main Specification of the quality of service (QoS) is that the signaling must be capable of carrying out traffic characteristics such as bandwidth and QoS are needed. This paper presents the performance evaluation of QoS parameters such as gigue, latency, lost packets, end-to-end delay, MOS under Omnet 4.6++ for all types of Software Defined Networking (SDN) topologies “Hierarchical, star, ring, tree”, in order to determine the architecture most suitable for the latter, via the implementation and simulation of the OpenFlow protocol.

In Europe, the competition between the mobile operators is so strong that the profitability of the mobile network has decreased. The cost to implement, to operate and to upgrade the mobile network is increasing while the revenues generated by the latter are not sufficient. Therefore, the operators should find the way to reduce the CAPEX and the OPEX. To keep competitive, the operators have begun to think about a novel RAN architecture. This new architecture is called Centralized or Cloud Radio Access Network. The traditional antenna site consists of the Radio Remote Head (RRH) which performs the radio processing, and the Base Band Unit (BBU) which carries out the digital processing. The principle of C-RAN consists to move the BBU from antenna site towards the local secured belonging to an operator called Central Office (CO). The move of BBU from antenna site to CO leads to the appearance of a new network segment called fronthaul. During this thesis, the different solutions to the deployment of fronthaul are studied and also the effects and the impacts of jitter on the fronthaul interface.; De nos jours, la montée en débit observée dans les réseaux mobiles est une problématique. A long terme, la densification des réseaux radios mobiles s'avérera inefficace. En plus de cela cette densification entraînera une baisse de rentabilité des réseaux d'accès mobiles et augmentera la complexité au niveau de la gestion des fréquences mobile qui accroîtra inéluctablement le risque de la présence des interférences. Pour pallier ce manque de rentabilité et pour faciliter le déploiement de certaines techniques d'optimisation et d'amélioration de l'interface air comme le « Coordinated MultiPoint » (CoMP), les acteurs des télécommunications proposent une nouvelle architecture innovante désignée par les termes Mobile Cloud ou « Centralized or Cloud Radio Access Network » (C-RAN). Le C-RAN consiste à déporter l'entité de traitement des données numérisées appelée « Base Band Unit » (BBU) du site d'antenne vers un local plus sécurisé nommé « Central Oce (CO) ». L'entité de traitement radio dénommée « Remote Radio Head (RRH) »est toujours localisée sur le site d'antenne. Cette délocalisation crée un nouveau segment réseau appelé « fronthaul ». Le fronthaul est un segment réseau très gourmand en bande passante par conséquent la fibre est désignée comme le support idéal pour assurer la communication bidirectionnelle entre la RRH et la BBU. Dans notre thèse, nous avons étudié les solutions de déploiement du fronthaul. Etant donné que l'interface fronthaul utilise de grands débits pour la transmission de données numérisées, elle est soumise à un phénomène physique nommé gigue qui a tendance à dégrader les performances de transmission. Les effets et l'impact de la gigue sur l'interface fronthaul et sur l'interface air ont été aussi étudiés.

We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm2 and advanced 10 kA/cm2 processes and successfully tested at high speed.

We propose a glottal source estimation method robust to shimmer and jitter in the glottal flow. The proposed estimation method is based on a joint source-filter optimization technique. The glottal source is modeled by the Liljencrants-Fant (LF) model and the vocal-tract filter is modeled by an auto-regressive filter, which is common in the source-filter approach to speech production. The optimization estimates the parameters of the LF model, the amplitudes of the glottal flow in each pitch period, and the vocal-tract filter coefficients so that the speech production model best describes the observed speech samples. Experiments with synthetic and real speech data show that the proposed estimation method is robust to different phonation types with varying shimmer and jitter characteristics.

The performance analysis of the 32 × 32 crosspoint-queued switch is presented in this paper. Switches with small buffers in crosspoints have been evaluated in the late 1980s but mostly for uniform traffic. However, due to technological limitations of that time, it was impractical to implement large buffers together with switching fabric. The crosspoint-queued switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin, and frame-based round robin matching) are analyzed and compared. The results obtained for the crosspoint-queued switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round-robin-based algorithms become a better choice for implementation due to their simplicity, small hardware requirements, and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm.

This paper studies the jitter performance at the input of the transimpedance amplifier (TIA) in a communication system based on multimode optical fibers. A method is shown to analyze and effectively reduce data-dependent jitter by proper choice of the TIA input resistance and the use of multiple feedback techniques. A 40-Gbit/s TIA in 0.25-μm BiCMOS with fT of up to 180 GHz is presented to demonstrate the efficiency of the jitter analysis. It shows 6 kΩ (75.5 dBΩ) transimpedance gain, 37.6-GHz bandwidth, open eyes, and less than 0.6-ps root mean square jitter at 40 Gbit/s, as well as best-in-class power consumption and noise performance.

We propose a new high-speed reset waveform which uses a negatively biased voltage to the common electrode and an alternating ramp voltage to the scan electrode during the reset period and an erase address scheme. It showed a less than 800-ns time lag, a wide address margin over 40 V, and improved jitter characteristics among different color cells in a plasma display panel with a 50-in full-high-definition resolution. Its fast discharge characteristics were attributed to the formation of a higher wall voltage near the middle of the gap during the reset period and the consequent bigger electric field during the scan period which was confirmed by the 3-D emission observation and cell-voltage-domain analysis.

ns-2 is a well known network simulator, recently extended with improvements to its emulation facility. Real-time constraints and the boundary between real-world and simulated entities impose scalability and accuracy limitations, and distort the simulated network as perceived by the involved real-world applications. This paper presents results from a performance evaluation of the ns-2 emulation facility. By carrying out emulation experiments at different scales and in different scenarios, we identify scalability limitations and quantify the emulation accuracy. We find throughput limits using high- and low-end computers, and a significant throughput decrease when increasing the number of involved real-world applications. Furthermore, we show how the end-to-end delay increases with both the traffic load and the number of real-world applications. In experiments with many applications, we also uncover significant variations in throughput and end-to-end delay among flows. Finally, our jitter measurements indicate how kernel scheduling causing bursty traffic transmission is responsible for most jitter. This effect is most often relatively modest, yet somewhat variable for experiments including several applications. Based on analysis of our results, we propose a set of modifications of the system that improves the performance. Our implementation of one of these modifications are demonstrated to increase throughput significantly while reducing the variation among flows. Implementation and evaluation of the remaining modifications is reserved for future work.

A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-μm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm 2 .

An all-digital clock and data recovery (CDR) with a digital threshold decision updating technique for SFI-5 application is presented in this paper. The CDR updates its decision upon the phase error reaching a threshold value by examining the phase errors in the data bits within an examining window at the baud rate. High jitter tolerance performance is obtained and the phase acquisition can be achieved within one baud period. The proposed CDR is embodied with 900 transistors and the core CDR consumes 5 mW with 1.2 V supply at 2.5 Gb/s. Measured results verify the digital threshold decision technique and its low-complexity implementation for SFI-5 application.

By using the data timing control at transmitter (TX) side, the crosstalk-induced jitter (CIJ) is compensated in a 4 Gbps single-ended transmitter with 3-bit parallel data. CIJ is induced by the propagation velocity difference between the signal modes of parallel transmission lines. This velocity difference was compensated for by sending data early or late at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 mum CMOS process. The parallel transmission lines used in the measurements are 4-inch long, have the minimum-allowed spacing between transmission lines to maximize CIJ. CIJ was measured to be reduced by about 50% from 53 ps to 27 ps at 4 Gbps excluding the random jitter component of 72 ps added at the TX side. The scheme used in this work can be expanded to more than three transmission lines.

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 mm2 active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.

This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 mum CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7 ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

This paper discusses PID controller tuning for integrating processes with varying time-delays. Most of the existing tuning rules for the first-order lag plus integrator plus delay (FOLIPD) processes that we mainly focus on have the same general structure, and the properties of these rules are discussed in conjunction with varying time-delays. The analysis leads to novel tuning rules, where the maximum amplitude of an arbitrarily varying time-delay can be given as a parameter, which makes the use of the rules attractive in several applications. We will also extend the analysis to integrating processes with second-order lag and apply the design guidelines for a networked control application. In addition, we propose a novel tuning method that optimizes the closed-loop performance with respect to certain robustness constraints while also providing robustness to delay variance via jitter margin maximization. Further, we develop new PID controller tuning rules for a wide range of processes based on the proposed method. The new tuning rules are discussed in detail and compared with some of the recently published results. The work was originally motivated by the need for robust but simultaneously well-performing PID parameters in an agricultural machine case process. We also demonstrate the superiority of the proposed tuning rules in the case process.

A real-time control system design procedure consists of the controller design stage and the implementation stage. In the controller design stage, various digital control theories are used with assumptions, such as synchronous sampling, no sampling jitter and negligible feedback latency (latency from sensing to actuation). However, in the implementation stage, multiple control tasks are usually scheduled on a processor, which creates a finite sampling period, varying feedback latency and sampling jitter, and therefore the controller's performance is degraded. In this article, we investigate the relationship between control performance and timing parameters. In the course of this investigation, we found that the feedback latency is the dominant factor affecting control performance. In addition, we propose a rate monotonic (RM) scheduler with non-preemptible last section algorithm, which can reduce the feedback latency considerably. The proposed algorithm provides better control performance than a preemptive RM scheduler, in most cases. The effectiveness of the proposed algorithm is shown in illustrative examples.

The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 times 10.3125 Gb/s, and 10 times10.3125 Gb/s for Ethernet 40 G/100 G), 8 times fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification.

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 mum CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.

This paper introduces a hybridized version of two common topologies of LC-based clock buffers. The proposed design can minimize jitter by adaptively adjusting the ratio between these two topologies. The analysis shows that the setting for optimum jitter depends on the relative level between the input noise and the inherent noise of the clock buffer. The long-term and short-term jitters are both studied and supported by measurement. A frequency tuning technique based on a voltage-swing digitizer is also demonstrated. The test chip is fabricated in a 1P8M 1.2-V 0.13-mum digital CMOS process. The power consumption of the proposed LC-based clock buffer is 12 mW.

A 2.5GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83ps (rms) less than 0.7% of the output period. The total power dissipation is 21mW at 2.5GHz output frequency, and the core area is 0.08mm2.

A new method is proposed in this article to accomplish the fine tune unit of the digitally controlled oscillator of an all-digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilise the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off states as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element can achieve results as good as 1.7126 ps. The operating frequency of this presented ADPLL ranges from 308 to 587 MHz. As compared to prior arts, the power consumption per MHz is reduced over 15% and the jitter is as low as 5 ps, which is a significant improvement.

A wide-range delay-locked loop (DLL) with infinite phase shift and duty cycle control is presented. A voltage-controlled sawtooth delay line provides not only the delay control but also duty cycle control. The proposed DLL achieves infinite phase shift by using a single loop. Therefore, it has the benefits of good jitter and wide range compared with the conventional dual-loop DLL. The proposed DLL has been fabricated in a 0.18-mum CMOS process and the core area is 0.45 times 0.3 mm2. The measurement results show the proposed DLL operates from 50 MHz to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured peak-to-peak jitter is 11.1 ps and the power consumption is 6 mW.

In order to achieve high linear density recording, a narrow transition width or small transition parameter, a, is imperative. Reducing the grain size improves transition jitter and also reduces the transition width. The correlation between transition width and transition jitter was examined. The observed discrepancy from simple, analytical expressions introduces more realistic magnetization transitions with island magnetization reversals. It was found that island reversals increase the transition width, rather than the transition jitter, which must be suppressed to attain high linear density.

The influence of wall charge distribution on the time lag of address discharge in an AC plasma display panel is investigated using two different reset waveforms: one (typical reset) induces both face and surface discharges and the other (TR reset) induces face discharges only. The measured formative time lag and statistical time lag of address discharge for TR were 21–31 ns and 31–74 ns shorter than the one for the typical reset, respectively. The TR reset resulted in much less increase of statistical time lag than the typical reset when the reset-to-address time interval was increased, and ∼70 ns smaller deviation of the statistical time lag among different color cells. Calculations show that the TR reset forms a much smoother wall charge profile, which is less susceptible to cell parameter variations, than the typical reset. The observed differences in the time lags of address discharge between different scan lines and color cells are strongly correlated to the differences of the wall charge profile, indicating that a smooth wall charge profile formed by the reset using face discharges only reduces the time lag of address discharge and minimizes the susceptibility of address discharge to cell parameter variation.

This paper proposes and demonstrates a simulation model to systematically investigate jitter accumulations in cascaded all-optical 2R regenerators. The simulation results indicate that when the pattern dependence from the memory effect is minimized, the jitter accumulation depends critically on the degree of the regenerative nonlinearity. Studies of tradeoffs between the jitter from bandwidth limitation and the signal-to-noise-ratio degradation help identify the optimized regenerator bandwidth for various degrees of regenerative nonlinearity. The simulation then considers the pattern dependence from the memory effect and finds that it can severely degrade the cascadability of an optical 2R regenerator and can make it worse than that of a linear optical amplifier (optical 1R). The simulation results show good matches to the experimental results of an optical 2R regenerator based on a semiconductor optical amplifier based Mach-Zehnder interferometer. To overcome the jitter accumulation associated with the optical 2R regeneration, we experimentally demonstrate an optical 3R regenerator for optical nonreturn-to-zero signals with all-optical clock recovery. The experiments achieve more than 1000-hop cascadability for pseudorandom binary sequence 231-1 inputs with a 100-km recirculation loop using lab fiber. Field trial experiments then demonstrate a more than 1000-hop cascadability for a 3R spacing of 66 km and a 100-hop cascadability for a 3R spacing of 264 km.

A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.

International audience; La réponse fréquentielle de lasers DML est analysée afin d'évaluer la limitation de leur usage dans les transmissions optiques multi-niveaux tels que le duo-binaire.

Bit rates of high speed serial links (USB, SATA, PCI-express, etc.) have reached the multi-gigabits per second, and continue to increase. Two of the major electrical parameters used to characterize SerDes Integrated Circuit performance are the transmitted jitter at a given bit error rate (BER) and the receiver capacity to track jitter at a given BER.Modeling the phase noise of the different SerDes components, extracting the time jitter and decomposing it, would help designers to achieve desired Figure of Merit (FoM) for future SerDes versions. Generating white and colored noise synthetic jitter patterns would allow to better analyze the effect of jitter in a system for design verification.The phase locked loop (PLL) is one of the contributors of clock random and periodic jitter inside the system. This thesis presents a method for modeling the PLL with phase noise injection and estimating the time domain jitter. A time domain model including PLL loop nonlinearities is created in order to estimate jitter. A novel method for generating Gaussian distribution synthetic jitter patterns from colored noise profiles is also proposed.The Standard Organizations specify random and deterministic jitter budgets. In order to decompose the PLL output jitter (or the generated jitter from the proposed method), a new technique for jitter analysis and decomposition is proposed. Modeling simulation results correlate well with measurements and this technique will help designers to properly identify and quantify the sources of deterministic jitter and their impact on the SerDes system.We have developed a method, for specifying PLLs in terms of Phase Noise. This method works for any standard (USB, SATA, PCIe, …), and defines Phase noise profiles of the different parts of the PLL, in order to be sure that the standard requirements are satisfied in terms of Jitter., La vitesse des liens séries haut débit (USB, SATA, PCI-express, etc.) a atteint les multi-gigabits par seconde, et continue à augmenter. Deux des principaux paramètres électriques utilisés pour caractériser les performances des SerDes sont la gigue transmis à un niveau de taux d’erreur donné et la capacité du récepteur à suivre la gigue à un taux d’erreur donné.Modéliser le bruit de phase des différents components du SerDes, et extraire la gigue temporelle pour la décomposer, aideraient les ingénieurs en conception de circuits à atteindre les meilleurs résultats pour les futures versions des SerDes. Générer des patterns de gigue synthétiques de bruits blancs ou colorés permettrait de mieux analyser les effets de la gigue dans le système pendant la phase de vérification.La boucle d’asservissement de phase est un des contributeurs de la gigue d’horloge aléatoire et déterministe à l’intérieur du système. Cette thèse présente une méthode pour modéliser la boucle d’asservissement de phase avec injection du bruit de phase et estimation de la gigue temporelle. Un modèle dans le domaine temporel en incluant les effets de non-linéarité de la boucle a été créé pour estimer cette gigue. Une nouvelle méthode pour générer des patterns synthétiques de gigue avec une distribution Gaussienne à partir de profils de bruit de phase coloré a été proposée.Les standards spécifient des budgets séparés de gigue aléatoire et déterministe. Pour décomposer la gigue de la sortie de la boucle d’asservissement de phase (ou la gigue généré par la méthode présentée), une nouvelle technique pour analyser et décomposer la gigue a été proposée. Les résultats de modélisation corrèlent bien avec les mesures et cette technique aidera les ingénieurs de conception à identifier et quantifier proprement les sources de la gigue ainsi que leurs impacts dans les systèmes SerDes.Nous avons développé une méthode, pour spécifier la boucle d’asservissement de phase en termes de bruit de phase. Cette méthode est applicable à tout standard (USB, SATA, PCIe, …) et définit les profils de bruits de4phases pour les différentes parties de la boucle d’asservissement de phase, pour s’assurer que les requis des standards sont satisfaits en termes de gigue. Ces modèles nous ont également permis de générer les spécifications de la PLL, pour des standards différents.

In video applications, the storage requirement is considerably large and hence they require large amount of network resources for their transmission. For transmitting the videos through a physical channel, there are two types of channelization-constant bandwidth and variable bandwidth channelization. It has been reported that using variable bandwidth channelization the buffer storage requirement is less than that of constant bandwidth channelization. Therefore, using variable bandwidth channelization a stochastic model is proposed for estimating the buffer storage so that the continuous delivery of the video data can be provided to the users.

The long-term bit error rate (BER) performance of partial response maximum likelihood (PRML) system using an adaptive equalizer in a perpendicular magnetic recording (PMR) channel with thermal decay is studied. A thermal decay model based on the experimental data giving the amplitude change of reproducing waveforms with the elapsed time for CoPtCr-SiO 2 PMR medium is obtained. The BER performance of PR1ML channel for the 16/17(0,6/6) run-length-limited (RLL) code is evaluated by computer simulation using the model. The relationship between the ratio Rj of the jitter-like media noise power to the total noise power at the reading point and the required SNR to achieve a BER of 10 -4 is also obtained and the performance is compared with that of the conventional equalization. The results show that the significant improvement in SNR by utilizing the adaptive equalization is recognized over all Rj compared with the conventional equalization.

We propose a subspace-based maximum-likelihood approach for acquiring the timing of wavelet-based multirate transmission systems. The S-curve analysis shows that our approach can correctly acquire the initial timing of a symbol from anywhere within a symbol-time interval at a cost of increasing jitter variance.

This paper presents a design of a 72.7ps peak-to-peak (p2p) jitter, 80MHz, phase-locked loop (PLL) circuit for digital video broadcasting over terrestrial (DVB-T) receivers. A step-down voltage regulator is utilized to suppress the coupled supply noise. A zero offset charge pump is employed to eliminate the static phase offset caused by the charge offset when the PLL is in lock. The measurement results on silicon using the TSMC (Taiwan Semiconductor Manufacturing Company) [email protected] 2P4M CMOS process show that the proposed PLL achieves as low as 72.7ps p2p jitter on silicon when the output frequency is 80MHz and the power consumption is merely 10.5mW given a 3.3V power supply.

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

Highly stable single axial mode operation is obtained in a pulsed injection seeded oscillator with an adjustable pulse length from 20 ns to more than 50 ns, at a constant output energy. The adjustment principle is described experimentally and analysed theoretically. The peak to peak time jitter added to a slow time drift is of the order of 1 nanosecond for a 20 nanoseconds pulse length.