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Byline: Bob Gleason SURE, YOU'RE AN EXPERT SKIER--YOU JUST DON'T NEED TO PROVE IT EVERY RUN. AND IF IT'S A CHOICE BETWEEN PRECISION PERFORMANCE AND REASONABLE COMFORT, IT'LL BE THE […]

In today's global economy, much has been written on how important it is for U.S. manufacturers to improve productivity and increase profits. The compressed air system remains an excellent source [...]

The need for cleaner compressed air is apparent to anyone trying to increase the productivity of sensitive pneumatic applications. Today; the modern manufacturer has needs for high-speed spindles, air gauging, [...]

The article discusses the 2014 Guild of American Luthiers (GAL) Convention panel discussion featuring the ukulele building with participants Michael DaSilva, Jay Lichty, Bob Gleason and moderator Woodley White.

A personal narrative is presented which explores the author's experience of constructing a ukelele.

ANSWERS TO YOUR QUESTIONS ABOUT LOTUS PRODUCTS CONTEST RESULTS In the February contest, we asked users of Symphony and 1-2-3 to devise a formula to test a range of values […]

An illuminator and mask patterns were optimized (SMO) to minimize CD variation of a set of contact patterns selected from logic layouts and an array of SRAM cells. MEEF and defocus characteristics of the target patterns were modeled as functions of constraints on minimum mask features and spaces (MRC). This process was then repeated after linearly shrinking the input patterns by 10%. Common statistical measures of CD control worsen as MRC becomes more restrictive, but these are weak indicators compared to behavior at points in the image that exhibit high MEEF or low depth of focus. SMO solutions for minimum MEEF and maximum depth of focus are different, so some compromise is necessary. By including exposure time among the variables to be optimized, some control over local mask bias is made available to minimize MEEF and loss of litho quality due to MRC.

Clear-field photo-masks offer significant advantages over dark-field photo-masks for some important classes of target patterns, including small isolated features and dense arrays of contacts. This work compares lithographic performance of clear-field and dark-field images when mask patterns are optimized for respective mask tones. Since the purpose is to study optical behavior, computed images without resist models were compared. In order to explore performance limits, optimized masks were not constrained to limit their complexity. Calculated images were compared for clear-field and dark-field masks, with either opaque or 6% transmission, 180-degree phase-shifted absorbers. In each case, mask patterns were independently optimized to print the targets, which were a set of square and rectangular arrays of contact holes with various dimensions and pitches. The range of the target patterns extended to the limits of ArF resolution with water immersion. Because the intent was to compare inherent optical performance of positive and negative-tone imaging, the study did not use resist models that would combine materials properties or behaviors into the results, but simply applied a constant threshold to calculated intensities to obtain images. Contrast, MEEF, and deviation of images with defocus were the basis of optimizing the mask patterns, and were compared for the four combinations of mask tones and absorbers. Best contrast and MEEF were obtained with bright-field masks that had attenuated, phase-shifting absorbers. The amount of improvement depended on the size of the mask patterns relative to that of their corresponding targets, set here by varying the intensity threshold for the images during mask optimization. Differences in how the images of the four types of masks changed with defocus were statistically insignificant.

It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh[1][2] thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including: DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask. Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors responsible for their differences include composition of the cost function that is minimized, constraints applied during optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.

We present a comprehensive study of area scaling for 22nm-logic-node routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and double-patterning (DP) regimes. For each candidate route pitch (88-56nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel 'source/design optimization' technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.