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To overcome the Fermi-level pinning in III-V metal-oxide-semiconductor capacitors, attention is usually focused on the choice of dielectric and surface chemical treatments prior to oxide deposition. In this work, we examined the influence of the III-V material surface cleaning and the semiconductor growth technique on the electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP(100) substrates. By means of the capacitance-voltage measurements, we demonstrated that samples do not have the same total oxide charge density depending on the cleaning solution used [(NH4)2S or NH4OH] prior to oxide deposition. The determination of the interface trap density revealed that a Fermi-level pinning occurs for samples grown by metalorganic chemical vapor deposition but not for similar samples grown by molecular beam epitaxy. Deep level transient spectroscopy analysis explained the Fermi-level pinning by an additional signal for samples grown by metalorganic chemical vapor deposition, attributed to the tunneling effect of carriers trapped in oxide toward interface states. This work emphasizes that the choice of appropriate oxide and cleaning treatment is not enough to prevent a Fermi-level pinning in III-V metal-oxide-semiconductor capacitors. The semiconductor growth technique needs to be taken into account because it impacts the trapping properties of the oxide. [ABSTRACT FROM AUTHOR]

In this paper, we show that performances of Ge2Sb2Te5-based phase-change memory (PCM) cells can be improved by the insertion of a thin HfO2 interfacial layer between the phase-change material and the tungsten plug. Significant reduction of the RESET and SET currents and of the energy required to switch the PCM cells are demonstrated. In addition, compared with pure GST reference cells, the presence of the HfO2 layer leads to an enhanced endurance (>10^8~cycles) and an improved data-retention (ten years at 172^\circC). Using cross-sectional TEM-Energy Dispersive X-Ray (EDX) analyses and technology computer-aided design simulations, the decreases of the programming currents and energy are explained through the reduction of the PCM cell active area, due to the creation of conductive paths in the HfO2 layer during the initial forming procedure. Electrical measurements and modeling of the forming procedure indicate that the size of the conductive paths is controlled by the maximum current flowing through the PCM cells during the current overshoot of the forming procedure. [ABSTRACT FROM AUTHOR]

We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germaniumon-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/μm at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~ 5 × 105), even at Lg = 55 nm. [ABSTRACT FROM AUTHOR]

Functionalization of Ge surfaces with the aim of incorporating specific dopant atoms to form high-quality junctions is of particular importance for the development of solid-state devices. In this study, we report the shallow doping of Ge wafers with a monolayer doping strategy that is based on the controlled grafting of Sb precursors and the subsequent diffusion of Sb into the wafer upon annealing. We also highlight the key role of citric acid in passivating the surface before its reaction with the Sb precursors and the benefit of a protective SiO 2 overlayer that enables an efficient incorporation of Sb dopants with a concentration higher than 10 20 cm -3 . Microscopic four-point probe measurements and photoconductivity experiments show the full electrical activation of the Sb dopants, giving rise to the formation of an n++ Sb-doped layer and an enhanced local field-effect passivation at the surface of the Ge wafer.