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The design of a very compact four quadrant CMOS analog multiplier is presented. The circuit has a very simple design, consisting of only four transistors and ten resistors, enabling a very small silicon area consumption. Furthermore, the multiplier can work in both subthreshold and saturation region, allowing it to operate over a wide range of frequencies. Subthreshold biasing sets the multiplier into a low-frequency low-power mode, while saturation biasing sets the multiplier to a high-frequency high-power mode. These two modes can be implemented for a very low voltage power supply. Finally, the proposed multiplier uses a minimum amount of nodes, allowing it to operate at high frequencies. Simulations show a maximum operating frequency of 300 kHz @ C L = 30 pF , a THD of ≈1% for an input sine wave of 100 mV and DC = 800 mV, and a minimum power supply of ( V DD - V SS ) ≈ 0.5 V when operating in the sub threshold region. In order to validate theory and simulations, a prototype of the proposed multiplier was fabricated using ON SEMI 0.5 μ m technology, showing its feasibility.

In this work the design and implementation of a white-cane suitable for blind people is presented. The sensing method is based on the relation distance/vibration; the closer the object, the faster is the vibration magnitude. The magnitude of this vibration is passed by four micro DC motors into the fingers of the user, indicating the proximity to the object and its localization. The vibration on the index, middle, ring, and baby fingers are used to indicate the position to the left, front, front, and left, respectively. The proximity sensors are located on a 3-D printed phantom model glasses, enabling the capability of sensing the whole environment in a 360° fashion by means of only moving the head in any direction. Stress and deformation simulations of the proposed white-cane were performed in SolidWorks. Also, the overall power consumption of the instrumentation system is only 2.15 W/h, allowing a six hours of continuous use before battery recharge. Also, the whole white-cane weighs 0.54 kg.

Self-powered RF passive sensors have potential application in temperature measurements of patients with health problems. Herein, this work presents the design and implementation of a self-powered UHF passive tag prototype for biomedical temperature monitoring. The proposed battery-free sensor is composed of three basic building blocks: a high-frequency section, a micro-power management stage, and a temperature sensor. This passive temperature sensor uses an 860 MHz to 960 MHz RF carrier and a 1 W Effective Isotropic Radiated Power (EIRP) to harvest energy for its operation, showing a read range of 9.5 m with a 13.75 µW power consumption, and an overall power consumption efficiency of 10.92% was achieved. The proposed device can measure temperature variations between 0 °C and 60 °C with a sensitivity of 823.29 Hz/°C and a standard error of 13.67 Hz/°C over linear regression. Circuit functionality was validated by means of post-layout simulations, characterization, and measurements of the manufactured prototype. The chip prototype was fabricated using a 0.18 µm CMOS standard technology with a silicon area consumption of 1065 µm × 560 µm. The overall size of the self-powered passive tag is 8 cm × 2 cm, including both chip and antenna. The self-powered tag prototype could be employed for human body temperature monitoring.

This work presents and validates the design of a four-quadrant analog multiplier based on the bulk-driven technique. Using the source–gate as well as the bulk–source voltages of a PMOS transistor as input ports, the multiplication task can be achieved. The AC signals are injected into the bulk terminals by means of a very-low-frequency programmable high-pass RC network which also serves to set its proper DC operation point. Although two RC networks are required, this multiplication cell is composed of only seven PMOS transistors and two coupling capacitors which makes it a very compact circuit. Furthermore, no preprocessed signals like the sum of $$\pm \,v_x \pm \,v_y$$ are required at the input ports. The implemented circuit shows a bandwidth of 50 MHz for an output capacitance of 40 pF and a THD lower than 1 $$\%$$ for gate/bulk input amplitudes below 0.2 Vp. The power consumption of the multiplication core is 660 $$\upmu $$ W and 2.6 mW including output buffers. In order to simulate and fabricate this circuit, an ON Semi 0.50 $$\upmu $$ m CMOS standard technology is used, showing a silicon area consumption of $$280\,\upmu \hbox {m} \times 400\,\upmu $$ m including output buffers. The proposed multiplier is suitable for biomedical, AM modulation, base-band modulation and analog computation.

This work presents the design of a new frequency doubler by a simple inductorless active network, without the exigency of additional quadrature signals. The frequency doubling function of the proposed circuit relies on the analog cosine mapping operation. The mapping circuit is possible in voltage mode as the circuit is based on two face-to-face CMOS inverters switched by the same differential input signal. The circuit is designed, with a simple set of functions, according to the nonlinear circuit’s nature. It was designed in a CMOS 0.18- $$\upmu $$ m process with a doubling frequency up to $$8~\text{ GHz }$$ . The experimental results of the prototype on the mentioned frequency range show the frequency doubling operation with a phase noise figure of $$-\,130~\text{ dBc/Hz }$$ @ $$10~\text{ KHz }$$ offset from the carrier.

This work presents the design of a current mode instrumentation amplifier (CMIA) based on the flipped voltage follower (FVF), used as a double current sense mechanism. Unlike current state of the art, the proposed CMIA senses the sourced and sank current of the voltage follower buffer inside the Op-Amp inputs. The FVF low-impedance input node allows to monitor the sink current provided by the low-impedance drain node of the active load in the voltage follower buffer. Proposed CMIA uses Split-Length compensated op-amps at the inputs, and Nulling-Resistor compensation technique is used at the output Op-Amp. The proposed CMIA is able to provide continuous programmable gains from 16 to 56 dB by adjusting $$R_2/R_1$$R2/R1 resistor ratios from 6.3 to 630 respectively. A gain-bandwidth product of 1.23 MHz and a common mode rejection ratio (CMRR) of 96 dB is obtained. A ?3 dB CMRR cutoff frequency of 115 Hz is observed in all gain cases. An overall CMIA power consumption of 315.5 µW is measured; 95 µA at ±1.65 V. The proposed CMIA was simulated and fabricated using 0.50 µm ON-Semiconductor CMOS standard technology.

In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “ x ” input signal is applied in voltage mode while the “ y ” input signal and “ o ” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “ y ” and “ o ” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a 50 Ω ‖ 30 pF load, presents a 1.5 % THD at 100 MHz, and consumes 7.5 mV using a ± 1 V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 μ m CMOS standard fabrication process; a silicon area consumption of 520 μ m × 70 μ m was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.

This work presents a Cap-less Low-Drop Out (LDO) Voltage Regulator that uses a Bootstrap Flipped-Voltage Follower (B-FVF) as the input stage of its active compensation network. Previous works use active compensation networks whose frequency response shows a high-pass behavior that depends on their compensation capacitor Cf. The dominant pole is related to the value of Cf. By using the B-FVF, this Cf-pole dependency is broken; only the gain of the compensation loop lies on Cf, while the high-pass pole is referred to the B-FVF input node capacitance. This advantage allows the integration of a smaller Cf, a 10X reduction compared with the state-of-the-art, and easier placement of the high-pass pole to higher frequencies than the LDO open-loop Gain Bandwidth (GBW). The proposed LDO presents a quiescent current consumption of 95 μA at a 1.8 V input voltage, delivering a 0mA–50mA load current at a 1.6 V output voltage. A load and line transient responses of 133 mV and 165 mV were measured by using a Cf of only 0.3 pF and a load capacitor CL of 100 pF. In order to validate the proposed LDO, simulations and measurements were performed in 0.18 μm CMOS Standard technology. The silicon area consumption is 0.133 mm2.

Ultra low-power electronic design is the backbone methodology tool in sensor integration architectures, sensor networking, biomedical applications and wearable electronics. These implementations demand multiple supply voltage domains with different current level requirements that vary from a few microamperes to hundred of miliamperes, such task is done by voltage regulators. This work studies the lower limits of DC-DC power conversion in Buck Converters as well as its feasibility to be embedded as ultra low-power voltage regulator supply; such feasibility criteria is based on inductor and capacitor CMOS technological parameters. Also, the design of a 1.65V/250mA Buck Converter in 0.50µm standard CMOS technology is presented. The designed Buck Converter presents a 41.33% efficiency using an input voltage of 3.3V; input power consumption is 1.023W while delivered power is 0.417W.

This work presents a 910MHz/2.4GHz dual-band dipole antenna for Power Harvesting and/or Sensor Network applications whose main advantage lies on its easily tunable bands. Tunability is achieved via the low and high frequency dipole separation Wgap. This separation is used to increase or decrease the S11 magnitude of the required bands. Such tunability can be used to harvest energy in environments where the electric field strength of one carrier band is dominant over the other one, or in the case when both carriers have similar electric field strength. If the environment is crowed by 820MHz-1.02GHz carries Wgap is adjusted to 1mm in order to harvest/sense only the selected band; if the environment is full of 2.24GHz - 2.52 GHz carriers Wgap is set to 7mm. When Wgap is selected to 4mm both bands can be harvested/sensed. The proposed antenna works for UHF-RFID, GSM-840MHz, 3G-UMTS, Wi-Fi and Bluetooth standards. Simulations are carried out in Advanced Design System (ADS) Momentum using commercial FR4 printed circuit board specification.

Some of the flaws in the interconnection wires of digital integrated circuits can be caused by fabrication defects or wear as the effect of electromigration effect. Interconnection wires add parasitic effects such as resistances and capacitances which contribute to the propagation delay of a logic gate signal to another. For long length wires the Elmore delay model for RC networks ladder, allows to estimate the propagation delay of a wire ideally without faults, and give a vision of the repercussions in the output signal between two connected inverters with a faulty wire at different points. Therefore, is presented a study of propagation delay in interconnection wire for a TSMC 0.18μm technology.

Theft and exchange of newborns have rise its numbers becoming this topic a big issue that must be face up by hospitals. Closed Circuit Television (CCTV) surveillance is one of the most used solutions. However, CCTV needs human operator and a highly implementation cost. Ultra High Frequency Radio IDentification (UHF RFID) brings an easy and cheap solution to this problematic because of automatic real time control and monitoring of passive elements called tags. This work presents the design of two UHF RFID meander line antennas for newborn hospital monitoring applications. The first antenna is implemented on printed circuit board (PCB) obtaining a read range of 8.25m, a read range improvement of 2.25m is observed compared with commercially available passive systems. The second antenna is fabricated on Rogers Duroid 5880 flexible substrate allowing adhesion to any surface shape, a read range of 6m is obtained. Comercially available system used as reference is composed by a reader CSL 461 and passive tag Confidex Carrier. In order to illustrate this improvement, a monitoring system layout prototype is proposed. during its stay in maternity room. The identification, security and monitoring is a vital task and must be done with the most carefully methods. In order to prevent any mistake related with the new born, hospitals tie up a label in the newborn's arm or ankle with the mother's personal information, birthday and sex, (3). An exactly copy of the first label is also tied up to the mother's arm. A UHF RFID system can easily overcome these issues, moreover it can bring a set of new applications that may help hospitals to offer a more controlled and secured service for the newborn and relatives. It is planned to use a commercial RFID reader and its components, implementing the system and performing readings of commercial tags, later performing readings with antennas, which are designed using chip coupling and thus compare the read rates and observe the behavior of the proposed tags. The first section explains how a basic RFID system and its operation is understood. The second section discusses the general procedures to identify newborns, specifically in Mexico. In the following section, the considerations and factors for implementing an RFID system are specified. Details about the design of the antennas is presented in section four, as well as the tag proposed according to their reading ranges and it's behavior in an area of 20 square meters.

This paper presents the design of a Voltage Regulation System for UHF Passive RFID Tags which consists of a Clamp Circuit and LDO Voltage Regulator. The Clamp's current consumption is 100nA and 1μA when the voltage reaches levels of 2.6V and 3.6V, respectively. LDO Voltage Regulator is capable of supplying a load current of 4.5 μA with only a current consumption of 900nA. The LDO Voltage Regulator has an overall efficiency of 73%, provides a load regulation of 25.53mV/μA and a settling time of 4μs. The design, simulation and layout are realized using 0.50 μm technology ON-SEMI two poly - three metal.

The energy harvesting breakthroughs have reached a point where has become posible to develop microelectronic systems, able to be supplied by the energy obtained from natural or prevalent sourced in the human environment. However, the energy amount that can be obtained from this sources is limited, hence, the energy harvesting power administration systems must be planned, so their energy consumption is low, without affecting their conversion efficiency and their start-up time. The usage of subthreshold design techniques makes it possible for circuits that involve an integrated system to operate using polarization currents that is in the nanoamperes order, therefore, they keep their performance and high integration capability. Among the problems that arise by using these design techniques is getting large transistors to be able to handle subthreshold current capacities, carrying as a consequence the increase of parasite capacitance, undermining the speed of response and the power consumption. Besides requiring the system being able to obtain a high conversion efficiency and a resistance to hostile operation conditions for its practical implementation. For the energy harvesting integrated systems development, it’s necessary for these to be able to deliver a continuous and stable current at its output to help the energy supply in modern microelectronic systems. At the same time, these blocks must be compatible with standard CMOS manufacturing processes, to guarantee their emigration capacity towards nanometric and sub-nanometric technologies. The presented system in this work it’s integrated by a rectifier circuit, a voltaje limiter, a current and voltage reference resistant to temperature variations, and a LDO voltage regulator. The system is capable of operate within a frequency range of 50Hz to 20KHz, a temperature range of 200°C, with a total power intake of 1.16μW and a 94.98% conversion efficiency. The simulations and layout were made using an ON Semiconductorᴿ 0.5μm standard CMOS technology, occupying a 756.2μm x 987.4μm area. Los avances alcanzados por el estudio de la recolección de energía han llegado al punto en el que es posible desarrollar de sistemas microelectrónicos que pueden ser alimentados por la energía extraída de fuentes naturales o prevalentes que se encuentran en el entorno humano. Sin embargo, la cantidad de energía que se puede obtener de estas fuentes es limitada, es por esto que los sistemas de administración de potencia para los recolectores de energía deben ser planeados para que su consumo sea bajo sin afectar de sobremanera su eficiencia de conversión y su tiempo de arranque. El empleo de técnicas de diseño en sub-umbral hace posible que los circuitos que componen a un sistema integrado operen utilizando corrientes de polarización que se encuentran en el orden de los nanoamperes, y a su vez, conservan su rendimiento y su alta capacidad de integración. Dentro de los problemas que surgen al usar estas técnicas de diseño se encuentra que se obtienen transistores de gran tamaño para poder manejar las capacidades de corriente en sub-umbral, trayendo a su vez como consecuencia que aumente las capacitancias parásitas resultando en un compromiso entre velocidad de respuesta y consumo de potencia. Además de que se requiere que el sistema sea capaz de obtener una alta eficiencia de conversión y una resistencia a condiciones de operación adversas para su aplicación práctica. Para el desarrollo de sistemas integrados de recolección de energía es necesario que estos sean capaces de entregar una corriente continua y estable a su salida para asistir al suministro de energía en los sistemas microelectrónicos modernos. A su vez, estos bloques deben ser compatibles con los procesos de fabricación CMOS estándares para garantizar su capacidad emigración hacia tecnologías nanoméricas y sub-nanométricas. El sistema presentado en este trabajo está compuesto por un circuito rectificador, un limitador de voltaje, una referencia de corriente y voltaje resistente a variaciones de temperatura y por último de un regulador de voltaje LDO. El sistema opera dentro de un rango de frecuencias de 50Hz a 20KHz, en un rango de temperatura de 200°C, con un consumo de potencia total 1.16μW y una eficiencia de conversión de 94.98%. Las simulaciones y el layout fueron realizados utilizando una tecnología de 0.5μm CMOS estándar de ON Semiconductorᴿ ocupando un área de 756.2μm x 987.4μm.