245 results on '"Gutmann, R.J."'
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2. Auger and radioactive recombination coefficients in 0.55-ev InGaAsSb
3. Photon recycling and recombination processes in 0.53 eV p-type InGaAsSb
4. Role of relative tilt on the structural properties of GaInSb epitaxial layers grown on (001) GaSb substrates
5. InGaAsSb thermophotovoltaic diode: physics evaluation
6. Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy
7. Evaluation of Thin Dielectric-Glue Wafer-Bonding for Three Dimensional Integrated Circuit-Applications
8. SiC and GaN bipolar power devices
9. Design considerations and experimental analysis for silicon carbide power rectifiers
10. Microwave photoconductivity decay characterization of high-purity 4H-SiC substrates
11. Antimonide based devices for thermophotovoltaic applications
12. P-type and N-type doping in GaSb and Ga{sub 0.8}In{sub 0.2}Sb layers grown by metalorganic vapor phase epitaxy
13. Silicon as the P-type dopant in GaSb and Ga{sub 0.8}In{sub 0.2}Sb grown by metalorganic vapor phase epitaxy
14. Tellurium doping of Ga{sub 0.8}In{sub 0.2}Sb layers grown by metalorganic vapor phase epitaxy
15. Ternary and quaternary antimonide devices for thermophotovoltaic applications
16. Effects of annealing on carrier lifetime in 4H-SiC
17. Adhesive wafer bonding
18. RF/microwave non-destructive measurements of electrical properties of semiconductor wafers for thermophotovoltaic applications
19. Modeling of InGaSb thermophotovoltaic cells and materials
20. Bulk growth of GaSb and Ga{sub 1{minus}x}In{sub x}Sb
21. Silicon as the P-type dopant in GaSb and Ga{sub 0.8}In{sub 0.2}Sb grown by metalorganic vapor phase epitaxy
22. Wafer-Level Via-First 3D Integration with Hybrid-Bonding of Cu/BCB Redistribution Layers
23. Wafer-Level 3D Integration Technology Platforms for ICs and MEMS
24. Memory performance prediction for high-performance microprocessors at deep submicrometer technologies
25. High Carrier Lifetime Bulk-Grown 4H-SiC Substrates for Power Applications
26. First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration
27. Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding
28. 930-V 170-m<tex>$Omega cdot hbox cm^2$</tex>Lateral Two-Zone RESURF MOSFETs in 4H-SiC With NO Annealing
29. Integrated Flip-Chip Flex-Circuit Packaging for Power Electronics Applications
30. Evaluation of Thin Dielectric-Glue Wafer-Bonding for Three Dimensional Integrated Circuit-Applications
31. Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy
32. Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration
33. Effect of annealing on gan-insulator interfaces characterized by metal-insulator-semiconductor capacitors
34. Slurries for Copper Damascene Patterning: Similarities and Differences
35. Developing the structure of a Cu CMP model
36. Dielectric GlueWafer Bonding For 3D ICs
37. Wafer Thinning for Monolithic 3D Integration
38. Bonding interfaces in wafer-level metal/adhesive bonded 3D integration.
39. lOkV 4H-SiC PiN Diodes Designed for Improved Switching Performance using Emitter Injection Control.
40. A 12-bit 65 MS/s pipeline A/D converter in 0.18 μm SiGe BiCMOS.
41. 1300-V 6H-SiC lateral MOSFETs with two RESURF zones
42. Hysteresis in transfer characteristics in 4H-SiC depletion/accumulation-mode MOSFETs
43. Grain Based Modeling of Stress Induced Copper Migration for 3D-IC Interwafer Vias.
44. Positive flatband voltage shift in MOS capacitors on n-type GaN
45. Die-on-wafer and wafer-level 3D integration for millimeter-wave smart antenna transceivers.
46. Degraded blocking performance of 4H-SiC rectifiers under high dV/dt conditions.
47. Evaluation of Thin Dielectric-Glue Wafer-Bonding for Three Dimensional Integrated Circuit-Applications.
48. Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy.
49. Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs.
50. High-voltage 4H-SiC PiN rectifiers with single-implant, multi-zone JTE termination.
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