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In the domain of process virtual machine (PVM) binary translation, the difference in address space layout between the guest program and the translated program requires the recalculation of jump instruction targets, resulting in suboptimal execution efficiency. This paper presents a novel method called SPC-Indexed Indirect Branch Hardware Cache Redirecting (SPCIC) technique. SPCIC utilizes specialized branch instruction to represent indirect branches from guest programs while frequently-used target addresses are cached in a customized hardware mapping table. When translating an indirect branch, SPCIC queries the jump target cache first to achieve a fast redirection unless the destination address is not cached. Besides, SPCIC merely falls back to the software-based remapping approach when the query fails, improving the translation efficiency to the greatest extent. SPCIC is implemented on the QEMU platform to accelerate the translation of ARM payloads into RISC-V. Experiments are carried on SPEC2006 to demonstrate the effectiveness of SPCIC for reducing the runtime overhead of indirect branch translation. The experimental results indicate up to 11% average improvement and 35% maximum improvement are obtained on the selected benchmark. [ABSTRACT FROM AUTHOR]

ABSTRACT In this paper, a high‐performance and area‐efficient hardware structure of the ChaCha20 stream cipher is presented. The most complex operation in the ChaCha20 stream cipher is addition modulo 232. The addition is used in the round function computations and the addition of the last round result and initial state. We use the proposed sparse parallel prefix adder for the implementation of addition modulo 232, which has a low critical path delay. In the proposed structure, to reduce area consumption, we use resource sharing with minimum hardware. To increase throughput and speed, the four registers are used with two main tasks including the storing intermediate results of the round function and the break critical path delay for the pipeline of the structure. Also, based on the used registers in the structure, the computations of the last clock cycle of the previous round function and the first clock cycle from the next round function are computed concurrently. Implementation results such as delay, computation time, area, and throughput of the proposed structure in 180 nm CMOS technology and FPGA implementation on the device Xilinx Virtex‐7 XC7VX485T are achieved. The achieved results show that the design has better hardware and timing properties compared with other works. [ABSTRACT FROM AUTHOR]

Lossless image compression techniques shrink the image size to improve the transmission efficiency and reduce the occupied storage space while ensuring the quality of the image is lossless. Among them, the LOCO‐I/JPEG‐LS algorithm benefits high lossless compression ratio and low computational complexity and thus is widely used for various real‐time applications. However, due to the problems of the context dependency in the LOCO‐I, the parallelism in the algorithm is greatly constrained, which significantly limits the throughput and the real‐time performance of hardware implementations. Existing designs achieve more parallelism by using a lot of hardware costs or straightforward chunking with losing compression ratio. In order to trade off the parallelism and the compression ratio, this paper proposes a chunk‐oriented error modeling scheme for LOCO‐I, which enables parallelism in both compression and decompression and achieves a better compression ratio in chunks. Based on the optimized algorithm, a high‐throughput flexible lossless compression and decompression architecture (HFCD) is proposed, which achieves higher pixel per clock (PPC) with less hardware cost. Additionally, HFCD introduces a parameter sharing mechanism to enable random access of image chunks to improve the flexibility for decompression. Experimental results show that, compared with state‐of‐the‐art works, HFCD achieves 3.02–13.50 times improvement for the PPC of compression. For decompression, benefiting from our optimizations, HFCD achieves 22.4 times speedup compared to the software solution. [ABSTRACT FROM AUTHOR]

The Covid-19 pandemic showed forcefully the fundamental importance broadband data communication and the internet has in our society. Optical communications forms the undisputable backbone of this critical infrastructure, and it is supported by an interdisciplinary research community striving to improve and develop it further. Since the first 'Roadmap of optical communications' was published in 2016, the field has seen significant progress in all areas, and time is ripe for an update of the research status. The optical communications area has become increasingly diverse, covering research in fundamental physics and materials science, high-speed electronics and photonics, signal processing and coding, and communication systems and networks. This roadmap describes state-of-the-art and future outlooks in the optical communications field. The article is divided into 20 sections on selected areas, each written by a leading expert in that area. The sections are thematically grouped into four parts with 4–6 sections each, covering, respectively, hardware, algorithms, networks and systems. Each section describes the current status, the future challenges, and development needed to meet said challenges in their area. As a whole, this roadmap provides a comprehensive and unprecedented overview of the contemporary optical communications research, and should be essential reading for researchers at any level active in this field. [ABSTRACT FROM AUTHOR]

A two-transformer active clamp forward flyback (ACFF) converter without output inductors is suitable for high output current applications such as low-voltage DC-DC converters (LDCs) in electrified vehicles. This paper presents the reverse power transmission operation of an ACFF converter used Synchronous Rectifier (SR). One of the target applications of the proposed converter is bidirectional LDCs used in electrified vehicles due to its high-power density and cost competitiveness. Operational principles with key voltage and current waveforms are provided, and a detailed analysis of each operating interval is provided, offering guidelines for component selection. Experimental results obtained from a 14 V–600 V hardware prototype verifies the feasibility of operation in practical LDCs. [ABSTRACT FROM AUTHOR]

In this overview article, we present the main features of the upgraded ID27 beamline which is fully optimised to match the exceptional characteristics of the new Extremely Bright Source (EBS) of the European Synchrotron Radiation Facility (ESRF). The ID27 beamline has been converted to a 120-m-long instrument and has undergone a major refurbishment of all its critical components including both hardware and software environments. We will successively introduce the ID27 undulator X-ray source, optical scheme and the main components of the experimental hutch. We will illustrate the potential of this new instrument through some selected research examples. [ABSTRACT FROM AUTHOR]

Practical testing of distance relays under power swing conditions is becoming all the more essential. This is in view of the increasing use of power electronic apparatus due to penetration of renewable sources and/or FACTS controllers now-a-days. To perform such practical tests, a hardware platform emulating power system swing occurrences, as caused by electromechanical oscillation of alternators, is necessary. As a first step it is required to model the phenomenon before its implementation. In this paper an analytical small-signal model of the low-frequency electromechanical oscillations in a grid-connected alternator is presented. Off-line simulation-based validation for a Single Machine Infinite Bus (SMIB) system is done. To emulate an open-loop alternator, a prototype of a controlled grid synchronised VSI with AC-side reactor is developed and practically tested. A control scheme is proposed and implemented to emulate the active power swing phenomenon. Effects of machine inertia and initial power angle on the swing characteristics are investigated. In-process estimation of apparent impedances, as seen from the distance relay terminals downstream towards the grid, is done. Principle of estimating the apparent impedance during power swing is presented with corresponding experimental results. Both real-time and off-line simulation results are in close agreement with the experimental results thus establishing the accuracy of the model and the precision of the experiments. [ABSTRACT FROM AUTHOR]

To address the challenges of efficient hardware design for error-tolerant applications, several techniques of applied approximate computing have been proposed. Pruning algorithms aim to approximate circuits with reduced design requirements at the cost of an acceptable degradation of their quality of result. In this letter, we present the effects of resynthesis, an iterative application of logic synthesis along with pruning algorithms, into a state-of-the-art approximate design flow, AxLS. Resynthesis strategy improves the approximation, achieving up to 70% area-power savings for the same error in the output, and reducing the number of iterations, and hence the time required to explore the design space in up to $30\times $ , to obtain an approximated design. [ABSTRACT FROM AUTHOR]

Emerging communication standards prioritize both the assurance of secure and reliable communications as well as the reduction of transmission delay and latency. Nevertheless, the task of achieving these objectives presents a complex and demanding challenge. Ensuring secure transmissions while simultaneously minimizing error rates requires the implementation of multistage information processing techniques that integrate coding and encryption methods, which may unfortunately lead to an undesired increase in transmission delay and latency. This letter presents an innovative crypto-coding framework capable of concurrently achieving essential encryption and coding within a single, streamlined process. By leveraging this approach, we aim to address the tradeoff between security, efficiency, and transmission delay, thus contributing to the advancement of secure and efficient communication standards. In this letter, we present a comprehensive evaluation of the proposed scheme, assessing its impact on final system error probability, encryption efficacy, and the complexity of hardware implementation. Our findings shed light on the potential benefits of this approach for future communication standards. [ABSTRACT FROM AUTHOR]

This letter focuses on the field-programmable gate array (FPGA) implementation of a Class A Middleton noise estimator, aiming to enhance its efficiency and performance. The inherent algorithm of the estimator undergoes strategic enhancements, leveraging median approximations. This endeavor leads to the development of a more streamlined and expeditious architecture. The research not only introduces the refined architecture but also conducts a comparative analysis of its attributes. The outcomes of this investigation show the benefits of algorithmic optimization, as the execution times achieved in hardware significantly surpass those attainable through software-based implementation. This underscores the practicality of the algorithmic refinement and also the notable advantages of the FPGA-based execution in terms of computational speed. [ABSTRACT FROM AUTHOR]

Modern chipmultiprocessors (CMPs) use third-party intellectual properties (IPs) to reduce design costs and meet deadlines. The cores in the CMP has their own private cache memories and all the cores share a common large sized last level cache (LLC). All the components of CMP, including cores and cache memories, are connected through a network-on-chip (NoC). Most of the NoC components have third-party IPs. Some of these IPs may be malicious and act as Hardware Trojan (HT). In this letter, we propose an HT-base attack that targets the LLC resizing techniques. The LLC resizing techniques are used to reduce the energy consumption of the LLC by shutting down unused parts of the LLC. The proposed attack can misuse the properties of these resizing techniques to reduce their energy saving up to 58%. The proposed attack can also reduce the system performance up to 18%. [ABSTRACT FROM AUTHOR]

Emergency alert systems (EASs) have been deployed in some countries in order to broadcast emergency alerts and warning messages to the public. In this letter, we describe an innovative electronic embedded solution, named Firetec switch, intended to be placed in the FM radio stations. This switch will be supported by a server placed at the authorized officials, with the capability to generate the audio alerting messages. One interesting challenge is to deliver the messages only to the local public, in the catastrophe neighborhood, by using FM radio stations. This letter focuses on the description of the Firetec switch hardware and software. [ABSTRACT FROM AUTHOR]

Machine learning (ML) models have demonstrated discriminative and representative learning capabilities over a wide range of applications, even at the cost of high-computational complexity. Due to their parallel processing capabilities, reconfigurability, and low-power consumption, systems on chip based on a field programmable gate array (SoC/FPGA) have been used to face this challenge. Nevertheless, SoC/FPGA devices are resource-constrained, which implies the need for optimal use of technology for the computation and storage operations involved in ML-based inference. Consequently, mapping a deep neural network (DNN) architecture to a SoC/FPGA requires compression strategies to obtain a hardware design with a good compromise between effectiveness, memory footprint, and inference time. This letter presents an efficient end-to-end workflow for deploying DNNs on an SoC/FPGA by integrating hyperparameter tuning through Bayesian optimization (BO) with an ensemble of compression techniques. [ABSTRACT FROM AUTHOR]

We extend the qubit-efficient encoding presented in (Tan et al. in Quantum 5:454, 2021) and apply it to instances of the financial transaction settlement problem constructed from data provided by a regulated financial exchange. Our methods are directly applicable to any QUBO problem with linear inequality constraints. Our extension of previously proposed methods consists of a simplification in varying the number of qubits used to encode correlations as well as a new class of variational circuits which incorporate symmetries thereby reducing sampling overhead, improving numerical stability and recovering the expression of the cost objective as a Hermitian observable. We also propose optimality-preserving methods to reduce variance in real-world data and substitute continuous slack variables. We benchmark our methods against standard QAOA for problems consisting of 16 transactions and obtain competitive results. Our newly proposed variational ansatz performs best overall. We demonstrate tackling problems with 128 transactions on real quantum hardware, exceeding previous results bounded by NISQ hardware by almost two orders of magnitude. [ABSTRACT FROM AUTHOR]

To address the challenges in establishing the state transfer matrix and the complexity of eigenvalue calculation in determining the multi-parameter stability boundaries of high-order nonlinear Vienna rectifiers, a novel numerical computation method is proposed in this paper. This method leverages a numerical stability criterion and a grid variable step search to efficiently calculate these stability boundaries. The small-signal model of the Vienna rectifier is derived by constructing the time-varying state transfer matrix using the periodic solution of the harmonic balance method. Eigenvalues are rapidly calculated via the periodic numerical solution of the state transfer matrix. The proposed parameter sensitivity-based grid variable step search method ensures a fast and accurate determination of stability boundaries. A hardware experimental setup is established to validate the stability boundaries of the Vienna rectifier under various parameter variations, including load, component, and control changes. The experimental results closely match the simulations, confirming the correctness and superiority of the proposed method. [ABSTRACT FROM AUTHOR]

We present VirtSecIO, a hypervisor-based platform for executing secure modules. VirtSecIO provides the modules with secure paths to peripheral devices, which can be shared between the modules and the operating system. Moreover, VirtSecIO is a thin hypervisor with a negligible performance overhead and a minimal attack surface. We demonstrate VirtSecIO's abilities by developing HyperWallet, a secure module that acts as a hardware crypto-wallet, without requiring any dedicated hardware. [ABSTRACT FROM AUTHOR]

Fixed‐width Booth multiplier (FWBM) plays a significant role in the arouse of approximate computing (AC) field. In this paper, a row‐based binary‐weighted compensator (RBC) for fixed‐width Booth multiplication is proposed. The derived binary‐weighted close‐form minimizes the conversion loss and hardware cost. With the proposed close‐form, the partial product array can be reduced dramatically. Consequently, the compact FWBM with the proposed RBC not only shortens the critical path to at least 24% but also minimizes the power dissipation to at least 44%. Moreover, the proposed RBC outperforms the state‐of‐art with a maximum merit improvement of 39%. By implementing the proposed RBC‐FWBM in the FIR filter, we manage to demonstrate the practicality of the proposed design with a significant reduction in power‐dissipation and delay while maintaining high accuracy. [ABSTRACT FROM AUTHOR]

We describe two operating modes for the same potentiostat, where the redox processes of hydroquinone in a hydrochloric acid medium are contrasted for cyclic voltammetry (CV) as functions of a digital/staircase scan and an analogue/linear scan. Although superficially there is not much to separate the two modes of operation as an end user, differences can be seen in the voltammograms while switching between the digital and analogue modes. The effects of quantization clearly have some impact on the measurements, with the outputs between the two modes being a function of the equivalent-circuit model of the electrochemical system under investigation. Increasing scan rates when using both modes produces higher peak redox currents, with the differences between the analogue and digital modes of operation being consistent as a function of the scan rate. Differences between the CV loops between the analogue and digital modes show key differences at certain points along the scans, which can be attributed to the nature of the electrolyte affecting the charging and discharging processes and consequently changing the peak currents of the redox processes. The faradaic processes were shown to be independent of the scan rates. Simulations of the equivalent-circuit behaviour show differences in the responses to different input signals, i.e., the step and ramp responses of the system. Both the voltage and current steps and ramp responses showed the time-domain behaviour of distinct elements of the equivalent electrochemical circuit model as an approximation of the applied digital and analogue CV input signals. Ultimately, it was concluded that similar parameters between the two modes of operation available with the potentiostat would lead to different output voltammograms and, despite advances in technology, digital systems can never fully emulate a true analogue system for electrochemical applications. These observations showcase the value of having hardware capable of true analogue characteristics over digital systems. [ABSTRACT FROM AUTHOR]

Most previous works in the field of nonlinear memristive chaotic systems mainly focus on non‐material memristor while seldom on material memristor. In this letter, the model and the corresponding parameter identification of the Knowm memristor is presented. The chaotic circuit based on the Knowm memristor is designed. Equilibrium points and stability of this Knowm‐memristor‐based chaotic system is analyzed. Nonlinear dynamic behavior is presented by the bifurcation diagram and Lyapunov exponents. Finally, the hardware circuit of this Knowm‐memristor‐based chaotic system is designed and the experimental results are presented for confirmation. [ABSTRACT FROM AUTHOR]

This paper investigates null control within the transmit–receive beampattern of Frequency Diverse Array-Multiple-Input and Multiple-Output (FDA-MIMO) systems, presenting a novel phase-only optimization approach for achieving null control in FDA-MIMO. We employ an alternating multiplier framework, which transforms the intricate and inherent constant modulus constraint and numerous amplitude constraints in optimization into more manageable projection problems. By employing a phase-only optimization strategy, the intricate hardware and computational burdens associated with null control in FDA-MIMO are effectively alleviated. The simulation results indicate that the algorithm proposed in this paper exhibits excellent null control ability while precisely maintaining constant modulus constraints, and it possesses an extremely high computational efficiency. [ABSTRACT FROM AUTHOR]

The general form of the Hamiltonian function serves as the foundation for the creation of a new four-dimensional chaotic system in this study. We discover that the external excitation parameter d , the internal parameter a , and all initial values have a transforming influence on the system property. Additionally, the corresponding fractional-order chaotic system in accordance with the constructed four-dimensional chaotic system is proposed. It is found that as the order q rises, the system transforms gradually from a dissipative system to a conservative system. Multiple coexisting attraction flows based on the Hamiltonian energy magnitude are present in this dual-property chaotic system. The complexity analysis shows that the system has a high level of complexity. NIST test indicates that the chaotic sequences produced by this dual-property chaotic system exhibit good pseudo-randomness. Finally, a Digital Signal Processing-based hardware platform confirms the physical realizability of the system. [ABSTRACT FROM AUTHOR]

Cloud computing, as the most widely applied and prominent domain of distributed systems, has brought numerous advantages to users, including high resource sharing efficiency, strong availability, and excellent scalability. However, the complexity of cloud computing environments also introduces various risks and challenges. In the current landscape with numerous cloud service providers and diverse hardware configurations in cloud environments, addressing challenges such as establishing trust chains, achieving general-purpose virtual remote attestation, and ensuring secure virtual machine migration becomes a crucial issue that traditional remote attestation architectures cannot adequately handle. Confronted with these issues in a heterogeneous multi-cloud environment, we present a targeted solution—a secure migration-enabled generic virtual remote attestation architecture based on improved TEE. We introduce a hardware trusted module to establish and bind with a Virtual Root of Trust (VRoT), addressing the challenge of trust chain establishment. Simultaneously, our architecture utilizes the VRoT within TEE to realize a general-purpose virtual remote attestation solution across heterogeneous hardware configurations. Furthermore, we design a controller deployed in the trusted domain to verify migration conditions, facilitate key exchange, and manage the migration process, ensuring the security and integrity of virtual machine migration. Lastly, we conduct rigorous experiments to measure the overhead and performance of our proposed remote attestation scheme and virtual machine secure migration process. The results unequivocally demonstrate that our architecture provides better generality and migration security with only marginal overhead compared to other traditional remote attestation solutions. [ABSTRACT FROM AUTHOR]

In this manuscript, a new control approach is counselled for DSTATCOM to resolve power quality (PQ) related issues. The Non-dual Adaptive Controller (NDAC) is employed with DSTATCOM to enhance the performance in terms of stability. The DSTATCOM is the constituent of voltage source inverter shunt DC-capacitor. A hysteresis block is employed for switching pulse triggering. The counselled scheme is a new method of shunt compensation and offers superior performance, for the lower frequency band in comparision with traditional strategies. Now-a-days we are dealing with huge nonlinear loads which draws non sinusoidal currents and also they generate large amount of harmonics. There are various advantages of using this new modified adaptive controllers over the tradition controllers. We are going to compare the performance of this new counselled controllers performance with the existing one in this literature. This new controller is initially simulated over MATLAB 2016 and then the efficacy of the counselled control approach (NDAC) is investigated using Laboratory prototype. Hardware setup is then authenticated through prototype with the help of dSPACE 1104. The execution reflects wide variation in the performances of both the controllers and also shows the supremacy of Non-dual adaptive controllers in terms of various aspects like harmonic current reduction, reduction in Total harmonic distortions during load dynamics. [ABSTRACT FROM AUTHOR]

Among the novel 3D visualization technologies of our era, light field displays provide the complete 3D visual experience without the need for any personal viewing device. Due to the lack of such constraint, these displays may be viewed by any number of observers simultaneously, and the corresponding use case contexts may also involve a virtually unlimited numbers of users; any number that the valid viewing area of the display may accommodate. While many instances of the utilization of this technology operate with static contents, camera animation may also be relevant. While the topic of light field camera animation has already been addressed on an initial level, there are still numerous research efforts to be carried out. In this paper, we elaborate on the lessons learned from implementing light field camera animation. The paper discusses the associated implications, limitations, potentials, and future research efforts. Each of these areas are approached from the perspectives of use cases, visual content, and quality assessment, as well as capture and display hardware. Our work highlights the existing research gaps in the investigated topic, the severe issues related to visualization sharpness, and the lack of appropriate datasets, as well as the constraints due to which novel contents may be captured by virtual cameras instead of real capture systems. [ABSTRACT FROM AUTHOR]

With the advent of networked systems in almost all current applications, security poses a great threat to the design industry. The participation of several people in different design abstract stages in the hierarchical design industry makes the design vulnerable to security threats. To address these security issues, this study used PUFs to create signatures on Intellectual Property (IP) to protect against malicious attacks. The proposed method exhibits significant resilience to ML-based attacks. [ABSTRACT FROM AUTHOR]

Quantum hardware has the potential to efficiently solve computationally difficult problems in physics and chemistry to reap enormous practical rewards. Analogue quantum simulation accomplishes this by using the dynamics of a controlled many-body system to mimic those of another system; such a method is feasible on near-term devices. We show that previous theoretical approaches to analogue quantum simulation suffer from fundamental barriers which prohibit scalable experimental implementation. By introducing a new mathematical framework and going beyond the usual toolbox of Hamiltonian complexity theory with an additional resource of engineered dissipation, we show that these barriers can be overcome. This provides a powerful new perspective for the rigorous study of analogue quantum simulators. Analogue quantum simulation has looser experimental requirements than its digital counterpart, but rigorous theoretical results on the capabilities of realisable experiments are scarce. Here, the authors fill this gap by proposing an alternative mathematical framework, and showing how to overcome barriers to scalable implementations using additional resources such as engineered dissipation. [ABSTRACT FROM AUTHOR]

Concerns over the carbon footprint resulting from the manufacturing, usage and disposal of hardware have been growing. The right-to-repair legislation was introduced to promote sustainable utilisation of hardware by encouraging stakeholders to prolong the lifetime of products, such as electronic devices. As there is little empirical evidence from a consumer perspective on exercising the right to repair, this study aims firstly to examine the factors that underpin consumers' intention to repair their hardware and secondly to investigate the perceived outcomes of repair practices. Based on 510 responses, the results showed that intention to repair is dependent on three groups of factors, namely the facilitators of pro-environmental behaviour, repair-related factors and beliefs about legislation. If consumers have a stronger intention to repair, they have a stronger feeling of emotional self-assurance, satisfaction with the repair decision and the technology manufacturer, an intention to engage with the manufacturer and a positive perception of a repaired device's performance. The findings contribute to the literature on sustainable behaviour and the right to repair, offering insight for policymakers and manufacturers about the strategies facilitating the wider adoption of repair practices. [ABSTRACT FROM AUTHOR]

While spin–orbit torque (SOT) devices are extensively investigated due to their potential for use in neural network computation, it remains challenging to explore the hardware for neural networks. In this paper, the field‐free memristive SOT switching of the CoPt single layer is used to propose a neuromorphic hardware circuit for detecting edges in images. Owing to its threefold symmetry of inversion, the polarity of SOT switching can be reversed by rotating the current by 60°. Moreover, the process of current‐induced SOT switching exhibits stable multi‐state magnetic switching behavior, and can be controllably tuned by using the pulse of the current. As the slope of the applied ramp pulse current increased, the wave of the anomalous Hall resistance changed from a curve with normally memristive property to trigonometric, and finally to cosine. The design of the hardware circuit for a single SOT device is subsequently formulated to detect the edges in images. The results of experiments verified the capability of this device to detect the edge lines in images with high accuracy, which confirms its potential for use in the hardware of neuromorphic computing platforms. The work here provides guidance for the application of SOT‐based devices to neuromorphic hardware. [ABSTRACT FROM AUTHOR]

Cache memory is controlled by hardware, resulting in significant hardware overhead and power consumption. This situation necessitated the use of scratchpad memory as an alternative. Specifically, for utilizing scratchpad memory in multi-core systems, a Local Memory Storage (LMStr) structure has been proposed. However, the LMStr structure must address fragmentation issues caused by the use of variable-sized data blocks. In this paper, we propose a new structure called 'Paging LMStr' that applies paging to solve this problem. We implement a system capable of simulating it in gem5 and evaluate its performance through a comprehensive testbench. The results demonstrate that the proposed structure improves the hit rate by 3.6% and reduces system ticks by approximately 10.68%, leading to a significant overall performance improvement compared to the existing structure. This indicates that Paging LMStr can effectively enhance memory management efficiency in multi-core systems, providing a viable solution to the challenges posed by traditional cache memory systems. [ABSTRACT FROM AUTHOR]

Bulk feeders that can automatically feed materials are one of the most commonly used vibration devices in the electronics industry. This study uses voice coil motors to design and implement a dual-axis bulk feeder and a quad-axis bulk feeder, allowing them to handle many kinds of materials. The implemented feeders can improve some of the problems in traditional bulk feeders, such as only one direction of movement, can only handle one kind of material, the contact time between the material and the platform is too long, and the feeder is not suitable to process materials with particular shapes. Two or four voice coil motors are placed under the platform of the implemented feeder. The vibration of the platform is controlled by the up-and-down movements of the voice coil motors, so that the bulk materials on the platform can be moved to the desired direction according to the feeding requirements. This study proposes a control method to control voice coil motors. For example, using different combinations of up-and-down movements of these four voice coil motors, the quad-axis voice coil feeder can move the material in eight horizontal directions, such as up, down, right, left, up right, up left, down right, and down left, as well as vertically flip. Since the frequency and amplitude of each vibration of the voice coil motor can be easily and instantly adjusted through the program, the implemented feeder can handle other types of materials without modifying the hardware of the device. Finally, some experimental results illustrate that the implemented dual-axis and quad-axis voice coil feeders can indeed effectively handle various bulk materials. [ABSTRACT FROM AUTHOR]

In artificial intelligence, the large role is played by machine learning (ML) in a variety of applications. This article aims at providing a comprehensive survey on summarizing recent trends and advances in hardware accelerator design for machine learning based on various hardware platforms like ASIC, FPGA and GPU. In this article, we look at different architectures that allow NN executions in respect of computational units, network topologies, dataflow optimization and accelerators based on new technologies. The important features of the various strategies for enhancing acceleration performance are highlighted. The numerous current difficulties like fair comparison, as well as potential subjects and obstacles in this field has been examined. This study intends to provide readers with a fast overview of neural network compression and acceleration, a clear evaluation of different methods, and the confidence to get started in the right path. [ABSTRACT FROM AUTHOR]

Background: Sequence alignment lies at the heart of genome sequence annotation. While the BLAST suite of alignment tools has long held an important role in alignment-based sequence database search, greater sensitivity is achieved through the use of profile hidden Markov models (pHMMs). Here, we describe an FPGA hardware accelerator, called HAVAC, that targets a key bottleneck step (SSV) in the analysis pipeline of the popular pHMM alignment tool, HMMER. Results: The HAVAC kernel calculates the SSV matrix at 1739 GCUPS on a ∼ $3000 Xilinx Alveo U50 FPGA accelerator card, ∼ 227× faster than the optimized SSV implementation in nhmmer. Accounting for PCI-e data transfer data processing, HAVAC is 65× faster than nhmmer's SSV with one thread and 35× faster than nhmmer with four threads, and uses ∼ 31% the energy of a traditional high end Intel CPU. Conclusions: HAVAC demonstrates the potential offered by FPGA hardware accelerators to produce dramatic speed gains in sequence annotation and related bioinformatics applications. Because these computations are performed on a co-processor, the host CPU remains free to simultaneously compute other aspects of the analysis pipeline. [ABSTRACT FROM AUTHOR]

AbstractStroboscopic nutation has proved to be invaluable for pulse width calibration (P. S. C. Wu and G. Otting, Rapid pulse length determination in high-resolution NMR, J. Magn. Reson. 2005, 176, 115–119), though it is not without its issues. Herein it is proposed that a correction factor be applied to correct for the inaccuracy of the method which is dependent on the NMR system including the probe, observed nucleus, sample type set (solvent, concentration, ionic strength, etc.), temperature, etc. Poor performance of the stroboscopic nutation experiment was also found to be a harbinger of a serious hardware problem. [ABSTRACT FROM AUTHOR]

Brain–Computer Interfaces (BCIs) have shown remarkable potential in human neuroscience and medicine. Yet, their application with animals, in particular canines, remains largely unexplored. This paper delves into the background, systems overview, implementation details, potential features, prospective use-cases and challenges of canine BCIs. While the focus is on EEG-based BCIs, other modalities such as fNIRS are also discussed. Despite significant challenges, such as hardware design and data inference, I argue that canine BCIs hold potential to significantly push forward our understanding of canine cognition, and facilitate a higher bandwidth of human-canine communication, collaboration, and flourishing. [ABSTRACT FROM AUTHOR]

Simulation-based Fault Injection (FI) is crucial for validating system behaviour in safety-critical applications, such as the automotive industry. The ISO 26262 standard's Part 11 extension provides failure modes for digital components, driving the development of new fault models to assess software-implemented mechanisms against random hardware failures (RHF). This paper proposes a Fault Injection framework, QEFIRA, and shows its ability to achieve the failure modes proposed by Part 11 of the ISO 26262 standard and estimate relevant metrics for safety mechanisms. QEFIRA uses QEMU to inject permanent and transient faults during runtime, whilst logging the system state and providing automatic post-execution analysis. Complemented with a confusion matrix, it allows us to gather standard compliant metrics to characterise and evaluate different designs in the early stages of development. Comparatively to the native QEMU implementation, the tool only shows a slowdown of 1.4 × for real-time microcontroller-based applications. [ABSTRACT FROM AUTHOR]

AI systems have an increasing sprawling impact in many application areas. Embedded systems built on AI have strong conflictual implementation constraints, including high computation speed, low power consumption, high energy efficiency, strong robustness and low cost. Neural Networks (NNs) used by these systems are intrinsically partially tolerant to computation disturbances. As a consequence, they are an interesting target for approximate computing seeking reduced resources, lower power consumption and faster computation. Also, the large number of computations required by a single inference makes hardware acceleration almost unavoidable to globally meet the design constraints. The reported study, based on an integer version of LeNet, shows the possible gains when coupling approximation and hardware acceleration. The main conclusions can be leveraged when considering other types of NNs. The first one is that several approximation types that look very similar can exhibit very different trade-offs between accuracy loss and hardware optimizations, so the selected approximation has to be carefully chosen. Also, a strong approximation leading to the best hardware can also lead to the best accuracy. This is the case here when selecting the ApxFA5 adder approximation defined in the literature. Finally, combining hardware acceleration and approximate operators in a coherent manner also increases the global gains. [ABSTRACT FROM AUTHOR]

Unauthenticated device access to a network presents substantial security risks. To address the challenges of access and identification for a vast number of devices with diverse functions in the era of the Internet of things (IoT), we propose an IoT device identification method based on hardware and software fingerprint features. This approach aims to achieve comprehensive "hardware–software–user" authentication. First, by extracting multimodal hardware fingerprint elements, we achieve identity authentication at the device hardware level. The time-domain and frequency-domain features of the device's transient signals are extracted and further learned by a feature learning network to generate device-related time-domain and frequency-domain feature representations. These feature representations are fused using a splicing operation, and the fused features are input into the classifier to identify the device's hardware attribute information. Next, based on the interaction traffic, behavioral information modeling and sequence information modeling are performed to extract the behavioral fingerprint elements of the device, achieving authentication at the software level. Experimental results demonstrate that the method proposed in this paper exhibits a high detection efficacy, achieving 99% accuracy in both software and hardware level identification. [ABSTRACT FROM AUTHOR]

The unmanned aerial vehicle (UAV) is considered a promising auxiliary relay for enhancing network coverage due to its easy deployment, agility, and maneuverability. In order to overcome the obstruction of towering buildings and the limitation of relaying energy, this paper proposes a half-duplex decode-and-forward UAV-assisted relaying network based on simultaneous wireless information and power transfer scheme. The power splitting (PS) is implemented at the UAV relay to address the challenge of energy limitation by separating information and energy from the radio frequency signal. We also study the impact of hardware impairments on transmitters, which can actually degrade communication performance. We derive both an exact expression and asymptotic analysis for the outage probability (OP) with energy harvesting and hardware impairments. In addition, we formulate an optimization form to find the optimal PS ratio and minimize the outage probability. Due to the nonconvex nature of this optimization problem, we perform a series of transformations to reformulate it into a convex optimization form. Experimental simulations validate our theoretical results. Specifically, optimal altitude for UAV is about 300 m and relatively constant in different conditions. The OP of our work is nearly 0.33 smaller than that of AF relaying in a given situation. Moreover, we provide practical guidance for the design and deployment of the UAV-assisted communication by exploring the effects of UAV's altitude, hardware impairments level, and power splitting ratio on the outage probability. [ABSTRACT FROM AUTHOR]

Neural network pruning is a popular approach to reducing the computational complexity of deep neural networks. In recent years, as growing evidence shows that conventional network pruning methods employ inappropriate proxy metrics, and as new types of hardware become increasingly available, hardware-aware network pruning that incorporates hardware characteristics in the loop of network pruning has gained growing attention. Both network accuracy and hardware efficiency (latency, memory consumption, etc.) are critical objectives to the success of network pruning, but the conflict between the multiple objectives makes it impossible to find a single optimal solution. Previous studies mostly convert the hardware-aware network pruning to optimization problems with a single objective. In this paper, we propose to solve the hardware-aware network pruning problem with Multi-Objective Evolutionary Algorithms (MOEAs). Specifically, we formulate the problem as a multi-objective optimization problem, and propose a novel memetic MOEA, namely HAMP, that combines an efficient portfoliobased selection and a surrogate-assisted local search, to solve it. Empirical studies demonstrate the potential of MOEAs in providing simultaneously a set of alternative solutions and the superiority of HAMP compared to the state-of-the-art hardware-aware network pruning method. [ABSTRACT FROM AUTHOR]

Nanospray desorption electrospray ionization (nano‐DESI) is an ambient ionization mass spectrometry imaging (MSI) approach that enables spatial mapping of biological and environmental samples with high spatial resolution and throughput. Because nano‐DESI has not yet been commercialized, researchers develop their own sources and interface them with different commercial mass spectrometers. Previously, several protocols focusing on the fabrication of nano‐DESI probes have been reported. In this tutorial, we discuss different hardware requirements for coupling the nano‐DESI source to commercial mass spectrometers, such as the safety interlock, inlet extension, and contact closure. In addition, we describe the structure of our custom software for controlling the nano‐DESI MSI platform and provide detailed instructions for its usage. With this tutorial, interested researchers should be able to implement nano‐DESI experiments in their labs. [ABSTRACT FROM AUTHOR]

The Telecom Infra Project Open Optical & Packet Transport (TIP OOPT) carries out activities aimed at decoupling hardware and software and accelerating innovation in optical and IP networks. This article focuses on the TIP Phoenix Project, in which operators are working together to present common use cases and specifications to encourage the entry of new vendors and reduce costs. The background of the project, efforts to date, and contribution of the NTT Group are explained. [ABSTRACT FROM AUTHOR]

Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms. [ABSTRACT FROM AUTHOR]

The multiple analytes produced during the operation of nuclear facilities are required to monitor the smooth operation of the plant in the environment of high temperature and radioactivity in real time. A chemiresisitive electronic nose was investigated and developed to analyze the multiple analytes generated in the nuclear reactor/allied facilities. An electronic nose consists of chemiresisitive sensor, array, housing, hardware, software, and pattern recognition algorithm. The sensor and array of different semiconductor metal oxides were prepared, processed, and developed to sense the multiple analytes. The hardware and data acquisition software (DAS) was designed and developed to acquire the dynamic responses from the array of four sensors. The hardware provides a low excitation voltage for measurement of the dynamic response of four sensors towards the improvement of the life of the sensor. The various experiments were conducted with multiple analytes at different temperatures to study the analysis of analytes. The performance of the hardware and DAS were tested and evaluated with the sensor array responses towards three analytes, viz., hydrogen (H2), formaldehyde (HCHO), and hydrazine (NH2NH2). Different features evaluated from the response traces were processed to teach the instrument using pattern recognition algorithms. The training and real-time testing of the sensor array realized the qualitative discrimination and quantitative estimation of the analytes. [ABSTRACT FROM AUTHOR]

Replacement policies have an important role in the functioning of the cache memory of processor cores. The implementation of a successful policy allows us to increase the performance of the processor core and the computer system as a whole. Replacement policies are most often evaluated by the percentage of cache hits during the cycles of the processor bus when accessing the cache memory. The policies that focus on replacing the Least Recently Used (LRU) or Least Frequently Used (LFU) elements, whether instructions or data, are relevant for use. It should be noted that in the paging cache buffer, the above replacement policies can also be used to replace address information. The pseudo LRU (PLRU) policy introduces replacing based on approximate information about the age of the elements in the cache memory. The hardware implementation of any replacement policy algorithm is the circuit. This hardware part of the processor core has certain characteristics: the latency of the search process for a candidate element for replacement, the gate complexity, and the reliability. The characteristics of the PLRUt and PLRUm replacement policies are synthesized and investigated. Both are the varieties of the PLRU replacement policy, which is close to the LRU policy in terms of the percentage of cache hits. In the current study, the hardware implementation of these policies is evaluated, and the possibility of adaptation to each of the policies in the processor core according to a selected priority characteristic is analyzed. The dependency of the rise in the delay and gate complexity in the case of an increase in the associativity of the cache memory is shown. The advantage of the hardware implementation of the PLRUt algorithm in comparison with the PLRUm algorithm for higher values of associativity is shown. [ABSTRACT FROM AUTHOR]