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Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose high performance systolic hardware architectures for 1BT based fixed block size (FBS) an,t variable block size (VBS) ME. The proposed ME hardware architectures perform full search ME for 4 Macroblocks in parallel and they are faster than the 1BT based ME hardware reported in the literature. They use less on-chip memory than the previous 1BT based ME hardware by using a novel data reuse scheme and memory organization. The proposed VBS ME hardware is the first 1BT based ME hardware implementing VBS ME. The proposed haraware architectures are implemented in Verilog HDL. The FBS ME and VBS ME hardware consume %34 and %49 of the slices in a Xilinx XC2VP30-7 FPGA, respectively. They can work at 113 MHz in the same FPGA and are capable of processing 49 1920x1080 full High Definition frames per second. Therefore, they can be used in consumer electronics products that require real-time video processing or compression. Index Term--Motion Estimation, Variable Block Size Motion Estimation, One-Bit Transform, Hardware Implementation. FPGA.

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a novel technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly without any PSNR and bitrate loss. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are equal, the prediction equations of H.264 intra prediction modes simplify significantly for this block. By exploiting the equality of the neighboring pixels, the proposed technique reduces the amount of computations performed by 4x4 luminance, 16x16 luminance, and 8x8 chrominance prediction modes up to 60%, 28%, and 68% respectively with a small comparison overhead. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex H FPGA using Xilinx XPower, and it reduced the power consumption of this hardware up to 18.6%. Index Terms--H.264, Intra Prediction, Low Power, Hardware Implementation, FPGA.

Motion estimation (ME) is the most computationally intensive part of a video coding system. Therefore it is very important to reduce its computational complexity. In this paper, a novel all-binary approach for reducing the computational complexity of sub-pixel accurate ME is proposed. An efficient hardware architecture for the proposed all-binary sub-pixel accurate motion estimation approach is also presented. The proposed hardware architecture has significantly low hardware complexity and therefore very low power consumption. It can process 720p video frames at 30 fps in a pipelined fashion together with the integer ME hardware. Therefore, it can be used in real-time low power video coding systems required by many mobile consumer electronics devices. Index Terms--Video Coding, One-bit transform, Sub-pixel motion estimation, Source pixel based linear arrays.

In this paper, we present an efficient H.264 intra frame coder system that achieves real-time performance for portable consumer electronics applications with low hardware cost. The system includes a low cost intra prediction hardware design that implements all intra prediction modes used in H.264 video coding standard based on a novel organization of the intra prediction equations. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code works at 71 MHz in a Xilinx Virtex II FPGA and it can code 35 CIF (352x288) frames per second. The system also includes software running on an Arm926EJS processor for implementing pre-processing and post-processing functions. The H.264 intra frame coder system is demonstrated to work correctly on an Arm Versatile Platform development board and it is verified to be compliant with H.264 standard. Index Terms--H.264, Video Coding, Intra Frame Coder, Intra Prediction, Hardware Implementation, FPGA.

In this paper, we present two efficient and low power H.264 deblocking filter (DBF) hardware implementations that can be used as part of an H.264 video encoder or decoder for portable applications. The first implementation (DBF_4x4) starts filtering the available edges as soon as a new 4x4 block is ready by using a novel edge filtering order to overlap the execution of DBF module with other modules in the H.264 encoder/decoder. Overlapping the execution of DBF hardware with the execution of the other modules in the H.264 encoder/decoder improves the performance of the H.264 encoder/decoder. The second implementation (DBF_16xl6) starts filtering the available edges after a new 16x16 macroblock is ready. Both DBF hardware architectures are implemented in Verilog HDL and both implementations are synthesized to 0.18 [micro]m UMC standard cell library. Both DBF implementations can work at 200 MHz and they can process 30 VGA (640X480) frames per second. DBF_4 x 4 and DBF_16 X 16 hardware implementations, excluding on-chip memories, are synthesized to 7.4 K and 5.3 K gates respectively. These gate counts are the lowest among the H.264 DBF hardware implementations presented in the literature. Our hardware implementations are more cost effective solutions for portable applications. DBF_16x16 has 36% less power consumption than DBF_4x4 on a Xilinx Virtex II FPGA on an Arm Versatile PB926EJ-S development board. Therefore, DBF 4X4 hardware can be used in an H.264 encoder or decoder for which the performance is more important, whereas DBF 16X16 hardware can be used in an H.264 encoder or decoder for which the power consumption is more [important.sup.1] Index Terms--H.264, Video Coding, Deblocking Filter, Hardware Implementation, FPGA, Low Power.