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This letter provides an overview of the metal-embedded chiplet assembly for microwave integrated circuits (MECAMICs) technology. MECAMIC is a 2.5-D wafer-level packaging approach that provides seamless heterogeneous integration capabilities of compound semiconductor transistors (e.g., GaN HEMTs) with passive components and interconnects using a backside metal embedding process. The chiplets are embedded in through-interposer cavities, and the backside metallization locks the chiplets into position while providing dc and RF ground for the high-frequency circuits. With this hybrid manufacturing approach, high-performance RF ICs can: 1) be designed using the best transistor technology for the function; 2) be fabricated in short cycle times through hybrid manufacturing; and 3) compete performancewise with monolithic circuits. We demonstrated an $X$ -band power amplifier circuit realized in MECAMIC with a saturated output power of 31 dB and a peak power added efficiency of 54%, which compared favorably to its monolithic GaN monolithic microwave integrated circuit (MMIC) counterpart. The MECAMIC process cycle time was $4.5\times $ faster than the monolithic process.

We report the development of high efficiency Ka-band (33 GHz – 36 GHz) MMIC amplifiers in a highly scaled 40nm HRL’s T4A GaN MMIC process. The reported two stage power amplifiers have peak power added efficiency (PAE) of 58.5% with associated gain of 11.9 dB and associated output power of 24.4 dBm measured at a frequency of 34 GHz in continuous wave (CW) mode. The exceptionally high efficiency of reported MMICs is a result of outstanding device characteristics of highly scaled GaN HEMTs.

This paper describes optically semi-transparent and flexible microstrip interconnects and patch antennas at millimeter wave frequencies. They are realized on a 5-mil thick transparent PET film by patterning honeycomb shape metal grids using a standard lithographic process. Dimensions of the employed metal grids were optimized for low insertion loss and >70% optical transmission at 77 GHz to enable integration into non-conventional surfaces for potential automotive radar applications. The fabricated microstrip lines demonstrate low-loss interconnects with

We report the first demonstration of: 1) wide-wavelength range, infrared transparent conductors (ITCs) made of silver nanowires (Ag NWs), and 2) ITC contact-integrated prototype, InAsSb mid-wavelength IR (MWIR) detectors. The Ag NW-based ITCs show optical transmittance ( $T_{\lambda}$ ) of ∼94% in the 0.9–2.5 μm wavelength range with a sheet resistance ( ${\rm R_{s}}$ ) of 19.1 Ω/□. $T_{\lambda}$ of the Ag NW-ITC decreases slowly with increasing wavelength, resulting in $T_{\lambda}$ ∼92%–87% at 2.5–8 μm (MWIR) and $T_{\lambda}$ ∼87%–82% at 8–15 μm (LWIR). The Ag NW-based ITC makes good ohmic contacts on InAsSb-based MWIR detectors with contact resistance of 85% at 4.25 μm and 150 K. The measured external QE remains at the same high level regardless of detector fill factor. These results indicate that Ag NW-ITCs may enable future pixel scaling for front-side illuminated, high-density-format focal plane arrays without compromising QE, responsivity, and detector performance.

We describe our recent results in developing and maturing small pixel (5μm pitch), high definition (HD) mid-wave infrared (MWIR) detector technology as well as focal-plane-array (FPA) hybrids, and prototype 2.4 Megapixel camera development operating at high temperature with low dark current and high operability. Advances in detector performance over the last several years have enabled III-V high operating temperature (T≥150K), unipolar detectors to emerge as an attractive alternative to HgCdTe detectors. The relative ease of processing the materials into large-format, small-pitch FPAs offers a cost-effective solution for tactical imaging applications in the MWIR band. In addition, small pixel detector technology enables a reduction in size of the system components, from the detector and ROIC chips to the focal length of the optics and lens size, resulting in an overall compactness of the sensor package, cooling and associated electronics. An MBE system has been used to grow antimony-based detector structures with 5.1μm cutoff with low total thickness variation (TTV) across a 3” wafer, in order to realize high interconnect yield for small-pitch FPAs. A unique indium bump scheme is proposed to realize 5μm pitch arrays with high connectivity yield. Several 1kx2k /5μm hybrids have been fabricated using Cyan’s CS3 ROICs with proper backend processing and finally packaged into a portable Dewar camera. The FPA radiometric result is showing low median dark current of 2.3x10 -5 A/cm 2 with > 99.9% operability, and >60% QE (without AR coating).

Barrier detectors based on III-V materials have recently been developed to realize substantial improvements in the performance of mid-wave infrared (MWIR) detectors, enabling FPA performance at high operating temperatures. The relative ease of processing the III-V materials into large-format, small-pitch FPAs offers a cost-effective solution for tactical imaging applications in the MWIR band as an attractive alternative to HgCdTe detectors. In addition, small pixel (5-10μm pitch) detector technology enables a reduction in size of the system components, from the detector and ROIC chips to the focal length of the optics and lens size, resulting in an overall compactness of the sensor package, cooling and associated electronics. To exploit the substantial cost advantages, scalability to larger format (2kx2k/10μm) and superior wafer quality of large-area GaAs substrates, we have fabricated antimony based III-V bulk detectors that were metamorphically grown by MBE on GaAs substrates. The electro-optical characterization of fabricated 2kx2k/10μm FPAs shows low median dark current (3 x 10-5 A/cm2 with λco = 5.11μm or 2.2 x 10-6 A/cm2 with λco = 4.6μm) at 150K, high NEdT operability (3x median value) >99.8% and >60% quantum efficiency (non-ARC). In addition, we report our initial result in developing small pixel (5μm pitch), high definition (HD) MWIR detector technology based on superlattice III-V absorbing layers grown by MBE on GaSb substrates. The FPA radiometric result is showing low median dark current (6.3 x 10-6 A/cm2 at 150K with λco = 5.0μm) with ~50% quantum efficiency (non-ARC), and low NEdT of 20mK (with averaging) at 150K. The detector and FPA test results that validate the viability of Sb-based bulk and superlattice high operating temperature MWIR FPA technology will be discussed during the presentation.

We report very wideband 100 MHz to 1 GHz active circulator with high power operation up to 30 dBm for the first time. In order to achieve broadband high power circulation and isolation, a new architecture is developed using low-loss RF choke concept and it is implemented on alumina substrate with mounted GaN HEMT devices along with other SMTs. The performed test shows minimum 15 to 20 dB isolation up to 30 dBm and 15 dB directivity up to 26 dBm across the band with 2.5~5 dB insertion loss for 15 dB of minimum directivity.

A high azimuth and elevation resolution multiple-input-multiple-output(MIMO) radar prototype with 16 Tx and 16 Rx antenna elements was developed in this work to address the autonomous driving vehicle challenges in complex urban environments. This article describes the technological scope of the developed prototype, details the performance challenges and discusses the system design considerations. The main goal of the developed automotive radar prototype is to achieve a high 2D angular resolution in the presence of a large number of radar echoes while maintaining an industry acceptable antenna aperture size and reasonable cost.

InAs1−x Sb x material with an alloy composition of the absorber layer adjusted to achieve 200-K cutoff wavelengths in the 5-μm range has been grown. Compound-barrier (CB) detectors were fabricated and tested for optical response, and J dark–V d measurements were taken as a function of temperature. Based on absorption coefficient information in the literature and spectral response measurements of the midwave infrared (MWIR) nCBn detectors, an absorption coefficient formula α(E, x, T) is proposed. Since the presently suggested absorption coefficient is based on limited data, additional measurements of material and detectors with different x values and as a function of temperature should refine the absorption coefficient, providing more accurate parametrization. Material electronic structures were computed using a k·p formalism. From the band structure, dark-current density (J dark) as a function of bias (V d) and temperature (T) was calculated and matched to J dark–V d curves at fixed T and J dark–T curves at constant V d. There is a good match between simulation and data over a wide range of bias, but discrepancies that are not presently understood exist near zero bias.

Investigation of Parylene-N (Pa-N) as a flexible substrate, multilayer dielectric material, and passivation layer for microwave and millimeter-wave integrated circuits is presented. For the first time, the electrical properties of Parylene-N have been characterized up to 60 GHz using various microstrip ring resonators and transmission lines. As a flexible substrate, Parylene-N measures a nearly invariant relative dielectric constant (epsilon(gamma)) of 2.35-2.4, and a loss tangent (tan delta) of lower than 0.0006 for frequencies up to 60 GHz. Because of the above properties, as a passivation layer, Parylene-N causes insignificant modifications to the properties of underlying passive and active structures. Measurement of coplanar waveguide transmission lines before and after passivation reveals that a 5-mu m Parylene-N barely changes the insertion loss (below measurement accuracy) while a 10-mu m-thick Parylene-N layer increases the insertion loss by only 0.007 dB/mm (below measurement error) at 40 GHz. Ring resonators before and after a 5 or 10 mu m passivation show a frequency shift of less than 0.05% or 1.51%, respectively, up to 40 GHz. The influence of Parylene-N passivation on the RF performance of GaAs MESFETs is also found to be negligible. Finally, humidity studies with dew point sensors reveal that with a 10-mu m-thick passivation at 25 degrees C and 100% relative humidity, the MTTF is about 481.6 days. In summary, the results indicate that Parylene-N is an excellent and promising material for application at microwave and millimeter-wave frequencies.

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mu m CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved

InAsSb material with a cutoff wavelength in the 5 μm range has been grown on GaAs substrates. The MWIR InAsSb detector arrays were fabricated and hybridized to a ROIC to permit measurement of the electrical and optical properties of detectors. Detector arrays were fabricated in a 1024 x 1024 format on an 18 μm pitch. A fanout was utilized to directly acquire data from a set of selected detectors without an intervening read out integrating circuit (ROIC). Variable temperature Jdark vs Vd measurements have been made with the dark current density ~ 10-5 A/cm 2 at 150 K. The external QE measured using a narrow band filter centered at ~ 4 μm had values in the 65 – 70 % range. Since the detectors were illuminated through a GaAs substrate, which has a reflectance of 29%, the internal QE is greater than 90%. A 1024 x 1024 ROIC on an 18 μm pitch was also designed and fabricated to interface with the barrier detectors. The ROIC operates at 30 Hz frame rate and has a well capacity of 20.7 M electrons. QE at 150 K for a 1024 x 1024 detector array hybridized to a ROIC had a median D* at 150 K under a flux of 1.07 x 1015 ph/(cm 2 /s) was 1.2 x 1011 cm Hz1/2 /W. The NEdT was 44 mK and imagery was obtained at 150 K using an f/2.3 MWIR lens.

A novel method to fabricate substrate-less flexible and printable electronics for microwave and millimeter-wave applications is presented. InGaAs MHEMT technology is utilized in this work to demonstrate feasibility of the flexible electronics with bulk limited performance at microwave frequencies for the first time. The fabrication process and measurement results are discussed in detail.

InAsSb material with a cutoff wavelength in the 5 μm range has been grown on GaAs substrates. The MWIR InAsSb detector arrays were fabricated and hybridized to fanouts and ROICs to permit measurement of the electrical and optical properties of detectors. Detector arrays were fabricated in a 1024 x 1024 format on an 18 μm pitch. A fanout was utilized to directly acquire data from a set of selected detectors without an intervening read out integrating circuit (ROIC). Variable temperature Jdark vs Vd measurements have been made with the dark current density ~ 10 -5 A/cm 2 at 150 K. The external QE measured using a narrow band filter centered at ~ 4 μm had values in the 65 - 70 % range. Since the detectors were illuminated through a GaAs substrate which has a reflectance of 29%, the internal QE is greater than 90 %. A 1024 x 1024 ROIC on an 18 μm pitch was also designed and fabricated to interface with the barrier detectors. The ROIC operates at 30 Hz frame rate and has a well capacity of 20.7 M electrons. QE at 150 K for a 1024 x 1024 detector array hybridized to a ROIC had a median D* at 150 K under a flux of 1.07 x 10 15 ph/(cm 2 /s was 1.2 x 10 11 cm Hz 1/2 /W. The NEdT was 44 mK and imagery was obtained at 150 K using an f/2.3 MWIR lens.

HRL Laboratories is part of an intense research and development effort to leverage the enormously advanced infrastructure of Si CMOS and the high performance of diverse electronic and photonic devices in an integrated technology. While System in a Package (SiP) and System on a Chip (SoC) approaches involve chips produced in their native foundries and subsequent integration using hybridization or multi-chip modules, HRL has pioneered approaches where partially completed wafers of diverse technologies are integrated using highly intimate placement and heterogeneous interconnects to enable transistor-level integration. Novel ICs have been produced in InP BiCMOS and CMOS memristor-integrated technologies. Unprecedented design flexibility is being enabled with intimate integration of GaN HEMTs together with InP and CMOS.

Mid-wavelength infrared (MWIR) InAsSb alloy barrier detectors grown on GaAs substrates were characterized as a function of temperature to evaluate their performance. Detector arrays were fabricated in a 1024 × 1024 format on an 18 μm pitch. A fanout was utilized to directly acquire data from a set of selected detectors without an intervening read out integrating circuit (ROIC). The detectors have a cutoff wavelength equal to ~ 4.9 μm at 150 K. The peak internal quantum efficiency (QE) required a reverse bias voltage of 1 V. The detectors were diffusion-limited at the bias required to attain peak QE. Multiple 18 μm × 18 μm detectors were tied together in parallel by connecting the indium bump of each detector to a single large metal pad on the fanout. The dark current density at -1 V bias for a set of 64 × 64 and 6 × 6 array of detectors, each of which were tied together in parallel was ~ 10-3 A/cm2 at 200 K and 5 × 10-6 A/cm2 at 150 K. The 4096 (64 × 64) and 36 (6 × 6) detectors, both have similar Jdark vs Vd characteristics, demonstrating high operability and uniformity of the detectors in the array. The external QE measured using a narrow band filter centered at ~ 4 μm had values in the 65 – 70 % range. Since the detectors were illuminated through a GaAs substrate which has a reflectance of 29%, the internal QE is greater than 90 %. A 1024 × 1024 ROIC on an 18 μm pitch was also designed and fabricated to interface with the barrier detectors. QE at 150 K for a 1024 × 1024 detector array hybridized to a ROIC matched the QE measured on detectors that were measured directly through a fanout chip. Median D* at 150 K under a flux of 1.07 × 1015 ph/(cm2/s was 1.0 x 1011 cm Hz1/2 /W.

We describe our recent efforts in developing visible to mid-wave (0.5 µm to 5.0 µm) broadband photon-trap InAsSb-based infrared detectors grown on GaAs substrates operating at high temperature (150-200K) with low dark current and high quantum efficiency. Utilizing an InAsSb absorber on GaAs substrates instead of an HgCdTe absorber will enable low-cost fabrication of large-format, high operating temperature focal plane arrays. We have utilized a novel detector design based-on pyramidal photon trapping InAsSb structures in conjunction with compound barrier-based device architecture to suppress both G-R dark current, as well as diffusion current through absorber volume reduction. Our optical simulation show that our engineered pyramid structures minimize the surface reflection compared to conventional diode structures acting as a broadband anti-reflective coating (AR). In addition, it exhibits > 70-80% absorption over the entire 0.5 µm to 5.0 µm spectral range while providing up to 3× reduction in absorber volume. Lattice-mismatched InAs0.82Sb0.18 with 5.25 µm cutoff at 200K was grown on GaAs substrates. 128×128/60μm and 1024×1024/18μm detector arrays that consist of bulk absorber as well as photon-trap pyramid structures were fabricated to compare the detector performance. The measured dark current density for the diodes with the pyramidal absorber was 3× lower that for the conventional diode with the bulk absorber, which is consistent with the volume reduction due to the creation of the pyramidal absorber topology. We have achieved high D* (< 1.0 x 1010 cm √Hz/W) and maintain very high (< 80 %) internal quantum efficiency over the entire band 0.5 to 5 µm spectral band at 200K.

This paper presents a novel method to fabricate substrate-less flexible and printable electronics for microwave and millimeter-wave applications. InP HEMT technology is utilized in this work to demonstrate first W-band completely flexible low noise amplifier (LNA). 10dB gain per stage is achieved at 100GHz for a 2×25μm device as expected from the EEHEMT model with simulated noise figure (NF) of 2.0. The fabrication process and measurement results are discussed in detail.

In InAs1-xSbx material alloy composition was adjusted to achieve 200K cutoff wavelengths in the 5 mm range. Reflectance was minimized and absorption in the InAs1-xSbx material maximized by the use of pyramid shaped structures fabricated in the InAs1-xSbx material which function as an AR coating. Compound-barrier (CB) detectors were fabricated and tested for optical response and dark current density versus bias measurements were acquired as a function of temperature. For 5 mm cutoff detectors, QE is high, ~ 75 % between 4.0 mm and 4.6 mm and g 80 % between 2.0 mand 4.0 mm, demonstrating the efficacy of the pyramids as photon trap structures and as a replacement for multi-layer AR-coatings. Jdark in the low 10-3 A/cm2 range at 200 K and low 10-5 A/cm2 range at 150 K was measured at the bias at which the QE peaked.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

United States. Defense Advanced Research Projects Agency (DARPA under contract N66604-09-C-3652)

Recent efforts in developing InAs/GaSb strained-layer superlattices for LWIR detectors are described. The structural properties of the devices grown by MBE at HRL were evaluated using optical microscopy, x-ray diffraction, and atomic force microscopy. Epilayer roughness and surface morphology are briefly described. Small format focal plane arrays were fabricated to serve as a baseline for device study, and to determine the effects of underfill epoxy on detector performance. A novel approach for epilayer transfer on silicon is also presented.

parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15- m-thick parylene-N layer and 0.56 dB/mm for a 50- CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with underpasses that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13- m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of + 4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.

A three dimensional low noise amplifier using post-processed transmission lines on a 130nm CMOS technology is presented. A 15µm thick low-k and low-loss Parylene-N layer is used to elevate transmission lines from the lossy Si substrate. This reduces the attenuation per unit length of the transmission lines by about 60%, while preserves CMOS chip area (in this specific design) by approximately 25% that is otherwise dedicated to these lines. The 3D amplifier measures a gain of 13dB at 2GHz with 3dB bandwidth of 500MHz, noise figure of 3.3dB and output 1dB compression point of +4.6dBm. With a simple room temperature CMOS compatible post-fabrication process, smaller chips with better performances are achieved. It is also shown that accurate simulation of a 3D circuit is attained by considering various parasitic effects that exist in this type of implementation.

Coplanar waveguide transmission lines and vertical interconnects are implemented on a thick (15µm) Parylene-N dielectric layer over a lossy CMOS-grade Si substrate. Devices are measured up to 40GHz and show very low loss behavior. Low loss tangent and low dielectric constant characteristics of Parylene-N result in significant improvement of transmission lines and interconnects compared to those implemented in a standard Si integrated circuit technology.

A modification to a recently developed chip/wafer integration technology has proven to be very effective in suppressing the substrate crosstalk for mixed signal systems. In this implementation, analog and digital chips are fabricated on separate dies, and then integrated on a single Si substrate using a Self-Aligned Wafer-Level Integration Technology. A truly grounded faraday-cage structure is realized by sidewall metallization around each die resulting in an ultimate substrate noise reduction. Any planar chip with any thickness can be used in this technology. Simulation and measurement results show that when a high - resistivity silicon substrate as an integration medium is used along with grounded faraday cage, substrate coupling is suppressed to less than -60 dB for frequencies up to 25 GHz. For a low-resistivity silicon substrate, the substrate coupling is a dominant mechanism in generating mixed-signal noise, however, when sidewall metallization as faraday cage is utilized, the substrate coupling is reduced by at least 20 dB for frequencies below 25 GHz. The substrate noise suppression is higher than 35 dB for frequencies below 2 GHz. To our knowledge, these are the best values reported for isolation improvement of thick silicon substrates at microwave frequencies.

In this paper, a new mixed-signal substrate noise rejection technique is proposed and implemented using a recently-developed self-aligned wafer-level integration technology (SAWLIT). In this technique, chips with any thickness can be used. Using sidewall metallization of cavities in an interposer substrate, truly grounded Faraday-cage structures are realized. The simulation and measurement results show that a high-resistivity silicon substrate can suppress the substrate noise by more than 60dB for the frequency of less than 1 GHz. For the frequency range of 1GHz to 25GHz, using the grounded Faraday-cage, the isolation can be improved to less than -60dB. For the low-resistivity silicon substrate, the substrate coupling is worse than the high-resistivity Si, however, using sidewall metallization, the isolation can be improved to below -60dB. To our knowledge, these are the best values reported for isolation improvement of thick silicon substrates and chips using a very thin layer of metallization.

In this work Parylene-N is investigated as a passivation layer for microwave and millimeter-wave integrated circuits (MMIC). The electrical and mechanical properties of this material show great potential for various applications in integrated circuits especially at higher frequencies. For the first time, Parylene-N has been used as a passivation layer on different test structures and their performance is studied up to 40GHz. The measurement results obtained from ring resonators and Coplanar Waveguide (CPW) transmission lines before and after passivation show that a 10 μm thick Parylene-N layer increases the insertion loss by only a negligible amount (0.007dB/mm at 40GHz), while a 5 μm thick coating does not have any influence on the insertion loss, confirming that the loss tangent of this coating material is very low. Besides, in measuring the resonance frequencies of different ring resonators a frequency shift of less than 1% is observed with a 10 μm passivation at 40GHz, while the shift is less than 0.05% for a 5 μm thickness, indicating a very low dielectric constant. In this paper we also show the performance of a multi-layer structure using a Coplanar Waveguide (CPW) vertical transition with vias etched between two Parylene-N layers. The results demonstrate the ability to use this flexible material as a low loss multi-layer substrate for microwave frequency applications. Finally a humidity study is performed by employing an array of dewpoint sensors with 10 μm thick Parylene-N coating. Hence the Mean Time to Failure (MTTF) under different humidity and temperature conditions is derived. Results indicate that Parylene-N is a good candidate as an encapsulant for MMIC applications.

We have designed and evaluated (using computer simulations) several different 2D phased arrays with square elements for deep localized hyperthermia. These array include a 20x20 planar array, a 80x16 cylindrical-section array, and a 16x16 spherical-section array. Also, we have designed a new phased array with circular elements. We used single and multiple focus scanning methods with intensity gain maximization. We found that the array with circular elements is more effective in reducing grating lobes compared to the same array with square elements. The grating lobes were at least 30 dB smaller than the phased array with square elements and intensity gain was at least 1 dB greater. In addition, with equal intensity distribution patterns for rectangular and circular phased arrays, the number of elements in the circular phased array was smaller and its intensity gain was greater than the other arrays.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263 mA/mm are obtained for 1 mu m gate-length Al2O3 MOS-HEMTs with 3 and 6 nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is similar to 3x10(3) with a subthreshold swing of 90 mV/decade. A maximum cutoff frequency (f(T)) of 27.3 GHz and maximum oscillation frequency (f(max)) of 39.9 GHz and an effective channel mobility of 4250 cm(2)/V s are measured for the 1 mu m gate-length Al2O3 MOS-HEMT with 6 nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7x10(-5) for the same device.