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It is difficult to measure the random telegraph noises (RTN) of MOSFET subthreshold currents at the sub-pA level directly and accurately. In this work, we used a charge integration method similar to the operation of the CMOS image sensors (CIS) to characterize the RTN of subthreshold currents approximately from 1 fA to 1 nA, using a test chip of 1M cell array in a 40 nm process. We found that each RTN trap was active only within a specific window of gate voltages. The trap became less active or inactive outside the corresponding window of operations. We showed that the sets of RTN-active devices under different gate voltages were different. Furthermore, the choice of sampling frequency in measuring RTN and the number of sampled data points determined the observable range of RTN emission and capture time constants. For the data measured by sampling periods of 3.82 s, 299 ms, and 372 $\mu {\mathrm{ s}}$ , different sets of RTN traps were observed with different spans of time constants. The combined time constants range was about 7 orders of magnitude. For single-trap RTN, we found and verified a relation between the probability of trap occupancy (PTO) and the ratio of root-mean-square random noise (RN) versus the RTN amplitude.

The effects of X-ray irradiation on the random noises, especially the random telegraph noises (RTN), of a 45-nm on 65-nm stacked CMOS image sensor with 8.3M $1.1~\mu \text{m}$ pixels are investigated. It is found that before X-ray irradiation the dominant type of RTN among the noisiest pixels is the source follower (SF) MOSFET channel RTN. In contrast, after X-ray irradiation up to a total ionizing dose of 1 Mrad(SiO2), the RTN becomes dominated by the variable transfer-gate-induced sense node (SN) leakage. These two different types of RTN can be distinguished by their dependence on the transfer gate (TG) OFF voltage and the time between the correlated double sampling (CDS). The magnitude of the RTN from the variable SN leakage is proportional to the CDS time and can be suppressed effectively by increasing the TG OFF voltage, whereas the SF RTN is independent of the CDS time or the TG OFF voltage.

This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1- $\mu \text{m}$ pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated multiple sampling (CMS) technique is introduced to selectively reduce the dark pixel noise by using a full-range ramp and a small-range ramp. In this way, a sub-electron temporal readout noise CIS is achieved without degrading the frame rate dramatically, compared to the conventional CMS method. A column-parallel single slope ADC with dark pixel detection function is proposed as well. A dynamic-dark-signal-region detection technique is used to mitigate differential nonlinearity (DNL) errors due to ramp slope mismatch. The implemented prototype in 45-nm CIS/65-nm CMOS occupies an area of 35.89 mm2. This paper achieves a 0.66erms− with 5-time sampling at a frame rate of 7.2 frames/s, which corresponds to a sample-rate frequency of 36.1 kHz for the column ADC. The DNL (11 b) is improved from +0.98 LSB/−0.94 LSB to +0.29 LSB/−0.39 LSB by using dynamic dark-signal region technique. The figure of merit of this paper is 2.02 nVrms/Hz.

In this paper we present a systematic approach to sort out different types of random telegraph noises (RTN) in CMOS image sensors (CIS) by examining their dependencies on the transfer gate off-voltage, the reset gate off-voltage, the photodiode integration time, and the sense node charge retention time. Besides the well-known source follower RTN, we have identified the RTN caused by varying photodiode dark current, transfer-gate and reset-gate induced sense node leakage. These four types of RTN and the dark signal shot noises dominate the noise distribution tails of CIS and non-CIS chips under test, either with or without X-ray irradiation. The effect of correlated multiple sampling (CMS) on noise reduction is studied and a theoretical model is developed to account for the measurement results.

A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 ${\mathrm{ \mu }}\text{s}$ and 500 ${\mathrm{ \mu }}\text{s}$ with the median around 10 ${\mathrm{ \mu }}\text{s}$ at room temperature.

A conditional correlated multiple sampling (CCMS) technique for low noise CMOS image sensor (CIS) is proposed to reduce noise and address low frame rate issue caused by the conventional correlated multiple sampling (CMS) technique. An 8Mpixel 3D-stacked CIS with 1.1um pixel pitch is designed and verified. Measurement results show this technique can achieve 0.66e− rms at 36.1 kHz A/D sampling rate per pixel with analog gain at 16 and 5-times multiple sampling. The resulting DNL is within −0.49/+0.45LSB.

A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model.

A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented to reduce the total power and noise.