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The ability to localize defects in order to understand failure mechanisms in complex superconducting electronics circuits, while operating at low temperature, does not yet exist. This work applies thermally-induced voltage alteration (TIVA), to a biased superconducting electronics (SCE) circuit at ambient temperature. TIVA is a commonly used, laser-based failure analysis technique developed for silicon-based microelectronics. The non-operational circuit consisted of an arithmetic logic unit (ALU) in a high-frequency test bed designed at HYPRES and fabricated by MIT Lincoln Laboratory using their SFQ5ee process. Localized TIVA signals were correlated with reflected light images at the surface, and these sites were further investigated by scanning electron microscopy imaging of focused ion-beam cross-sections. The areas investigated, where prominent TIVA signals were observed, showed seams in the Nb wiring layers at contacts to Josephson junctions or inductors and/or disrupted junction morphologies. These results suggest that the TIVA technique can be used at ambient temperature to diagnose fabrication defects that may cause low temperature circuit failure.

In this work we give a characterization of the RF effect of memory switching on Nb-Al/AlOx-(Nb)-Pd$_{0.99}$Fe$_{0.01}$-Nb Josephson junctions as a function of magnetic field pulse amplitude and duration, alongside with an electrodynamical characterization of such junctions, in comparison with standard Nb-Al/AlOx-Nb tunnel junctions. The use of microwaves to tune the switching parameters of magnetic Josephson junctions is a step in the development of novel addressing schemes aimed at improving the performances of superconducting memories., Comment: IEEE Trans. Appl. Supercond. Special Issue ISEC2017

We report on the development of energy-efficient decoders for cryogenic random access memory and register file. To reduce the pitch, area, and energy, our decoder employs a scalable binary tree architecture. We implemented these decoders using ERSFQ logic controlled by magnetically coupled address lines. These lines are driven by energy-efficient drivers based on the current-stirring technique. A 4-to-16 version of the decoder was laid out and fabricated in HYPRES 6-layer 10 kA/cm2 and MIT LL 8-layer 10 kA/cm2 processes with 15 and 28 μ m decoder row pitch, respectively. The decoders were designed to have ∼30 ps latency and dissipate ∼40 aJ per clock. We experimentally confirmed the functionality of the circuits with ±8% dc bias margins and verified its operation up to 13 GHz clock.

Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2 fabrication processes and tested at low (∼kHz) and high (∼GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/–4% to over +/–19% when the Josephson junction count in the FJTL was increased to ∼30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.

A focused ion beam was used to obtain cross-sectional specimens from both magnetic multilayer and Nb/Al-AlOx/Nb Josephson junction devices for characterization by scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX). Automated multivariate statistical analysis of the EDX spectral images produced chemically unique component images of individual layers within the multilayer structures. STEM imaging elucidated distinct variations in film morphology, interface quality, and/or etch artifacts that could be correlated to magnetic and/or electrical properties measured on the same devices.

The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.

An approach for scalable quantum computing infrastructure based on the use of low-power digital superconducting single flux quantum (SFQ) circuits is described. Rather than replicating the room-temperature microwave control and measurement infrastructure solutions dominating the current systems, we use the inherent to superconducting technology methods – the use of SFQ pulses directly at the base temperature. For qubit control, we irradiate qubits with the coherent SFQ pulse sequences computed using optical control theory. For qubit measurement, Josephson photon counter performs projective quantum measurement, the result of which is converted to digital SFQ output. These operations are aided by a high-speed digital SFQ coprocessor located at higher temperature stage (e.g., 3 K) to process the measurement results and load new control sequences to 20 mK SFQ quantum-classical interface circuits.

We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm2 fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency., 7 pages, 10 figures, 2 tables, 41 references. Presented at Applied Superconductivity Conference 2018 (ASC 2018), Oct. 28 - Nov. 2, 2018, Seattle, WA, USA. Paper 1EOr1C-06

We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bi-directional SHIFT instruction of an 8-bit argument. It consists of a bi-direction triple-port shift register controlled by two (left and right) shift pulse generators asynchronously generating a set number of shift pulses. At first clock cycle, an 8-bit word is loaded into the binary shifter and a 3-bit shift argument is loaded into the desired shift-pulse generator. Next, the generator produces the required number of shift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set by the internal generator delay of ~ 30 ps. These SFQ pulses are applied to the left (positive) or the right (negative) input of the binary shifter. Finally, after the shift operation is completed, the resulting 8-bit word goes to the parallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820 Josephson junctions, was simulated and optimized using PSCAN2. It was fabricated in MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process with a high-kinetic inductance layer. We have successfully tested the binary shifter at both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shift arguments. A single shift operation on a single input word demonstrated operational margins of +/-16% of the dc bias current. The correct functionality of the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern was observed within +/-10% margins of the dc bias current. In this paper, we describe the design and present the test results for the ERSFQ 8-bit parallel binary shifter., Comment: 4 pages, 6 figures, 22 references. Presented at Applied Superconductivity Conference 2018 (ASC 2018), Oct. 28 - Nov. 2, 2018, Seattle, WA, USA. Paper 1EOr1C-07

As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.

We have designed and tested energy-efficient single flux quantum (eSFQ) circuits suitable for wave-pipelined architectures. The high energy-efficiency of eSFQ circuits combined with the sequential nature of SFQ logic makes eSFQ especially suitable for energy-efficient variants of highly-pipelined circuits such as modern arithmetic logic units (ALUs), without penalty to the clock speeds available to RSFQ logic. In previous work, we have demonstrated working eSFQ circuits in the form of shift registers, deserializers, counters. Here we expand on this work by introducing a means of moving data through eSFQ circuits without the need for buffering at every step, resembling the wave-pipelined architecture characterizing many large modern logic circuits. Specifically, we present a pipeline-friendly JTL, confluence buffer, and half adder, comprising the core components of many adder architectures. We also show how such an eSFQ full adder naturally lends itself to utilization in a computation pipeline. We report experimental demonstration of circuits manufactured in Hypres's 4.5 kA/cm 2 process.

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

We designed, fabricated, and demonstrated an energy-efficient ERSFQ 4-bit decoder. The first version of the decoder is designed and fabricated using HYPRES legacy 1.0-μm four-layer 4.5-kA/cm 2 process. It occupies an area of 700 μm × 1800 μm, which is to be reduced to 160 μm × 400 μm once fabricated using HYPRES's RIPPLE-2 0.25-μm six-layer process. The decoder features ±13% dc bias current operating margins and below 70-aJ energy consumption per one address select operation. We report test results of the decoder and discuss its future implementation in cryogenic random access memory devices, including magnetic memory devices.

We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.

We test the effect of an external RF field on the switching processes of magnetic Josephson junctions (MJJs) suitable for the realization of fast, scalable cryogenic memories compatible with Single Flux Quantum logic. We show that the combined application of microwaves and magnetic field pulses can improve the performances of the device, increasing the separation between the critical current levels corresponding to logical '0' and '1'. The enhancement of the current level separation can be as high as 80% using an optimal set of parameters. We demonstrate that external RF fields can be used as an additional tool to manipulate the memory states, and we expect that this approach may lead to the development of new methods of selecting MJJs and manipulating their states in memory arrays for various applications., Comment: 7 pages, 3 figures

We present test results for parallel data communication ERSFQ circuits with clock recovery. We experimentally study on-chip and chip-to-chip parallel data communication circuits with 4-, 8- and 16-bit word lengths. The largest circuit is a 16-bit chip-to-chip communication test circuit embedded into a testbed with clock distributed over a combination of active and passive transmission lines with transmitter/receiver pairs, and is comprised of 3464 Josephson junctions in total. All ERSFQ circuits are fabricated using MITLL 10-kA/cm2 SFQ5ee process. For the chip-to-chip communication experiment, a multi-chip module (MCM) is assembled using Hypres' MCM flip-chip bonding process which connected the MIT-LL-made flip-chip to the Hypres-made MCM carrier using 220 signal bumps with 50 um pitch. We experimentally confirmed correct functionality of 4-, 8- and 16-bit circuits and measured their current bias margins. For the 16- bit chip-to-chip communication circuit mounted to a MCM, we measured ±12% dc bias margins similar to the margins measured for the on-chip version of the same circuit. The MCM circuit is also evaluated at high clock speed generated by an external source, while the data words are changed at low speed. The correct functionality is observed without significant reduction in the bias margins using average-voltage test approach.

The lack of dense, fast, energy efficient memory has been the main detractor for multiple superconducting digital projects in the past. Recently, fundamental physics research in superconductor-ferromagnet thin-film tunnel structures created a new opportunity to solve this long-standing problem. Superconductivity and ferromagnetism, two deeply antagonistic electronic properties, can co-exist in form of Magnetic Josephson Junctions (MJJs). The superconducting-ferromagnetic MJJs are electrically compatible with traditional superconductor-insulator-superconductor (SIS) Josephson junctions (JJs) used for digital energy-efficient single flux quantum (eSFQ/ERSFQ) circuits. Both MJJ and JJ circuits have similar fabrication process and can be integrated on a single chip. As a result, a combination of MJJs and JJs can be used to form addressable memory cells, energy-efficient memory periphery circuits and programmable logic elements. In this paper, we present the test results of superconductor-insulator-ferromagnet-superconductor (SIFS) MJJs showing their applicability for superconducting spintronic memory and digital circuits.

We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES’ standard 4.5 kA/cm2 process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and high-speed test results for the 8-bit ALU circuit.

Superconductor digital receiver systems of increasing functionality, modularity and user-friendliness have been developed. The modular design methodology ensures that within its input-output and heat load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. One of the systems (ADR-004), originally equipped with a 10 × 10 mm2 channelizing receiver chip for signals intelligence application, was reconfigured with a 5 × 5 mm2 1.1-GHz bandpass ADC chip to perform world's first multi-net Link-16 demonstration at a U.S. Navy facility. Substantial improvements in system integration have been obtained in each successive generation of digital-RF receiver systems. The latest (third) generation system (ADR-005), hosting a 5 × 5 mm2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1-cm2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier. To our knowledge, this is the first time an X-band SATCOM receiver has been operated without analog amplification and down-conversion in a military application.

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2 HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.

We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulation-demodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been tested at sampling frequencies up to 29.44 GHz; a 89.15 dB signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to 46.08 GHz and 29.44 GHz for chips fabricated using the 4.5 and 1 kA/cm2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at 29.44 GHz, the SNR is 83.93 dB in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 dB. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fluxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 dB performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 kA/cm2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is 82.54 dB, with the noise measured in a reference 10 MHz bandwidth. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 dB performance enhancement.

We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation–demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4. 5k A cm −2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed.

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency (RF). Such a receiver consists of a wideband analog-to-digital converter (ADC) modulator and multiple digital channelizer units to extract different frequency bands-of-interest within the broad digitized spectrum. The single-bit oversampled data, from either a lowpass delta or bandpass delta-sigma modulator, are applied to one or more channelizers, each comprising digital in-phase and quadrature mixers and a pair of digital decimation filters. We perform channelization in two steps, the first at full ADC sampling clock frequency with rapid single flux quantum (RSFQ) digital circuits and the second at reduced (decimated) clock frequency with commercial field programmable gate array (FPGA) chips at room temperature. We have demonstrated lowpass and bandpass digital receivers by integrating an ADC modulator and a channelizer unit on the same chip at clock frequencies up to 20 GHz. These 1-cm2 single-chip digital-RF receivers contain over 10,000 Josephson junctions. The channelizing receiver approach can be extended to include multiple ADC modulators and multiple channelizer units on a multi-chip module.

HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm2 Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm2 process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.

Compact mm/submm integrated spectrometers are required for radio-astronomical research, remote monitoring of the Earth atmosphere and environmental monitoring for hazardous materials of chemical and biological origin. Assembled on a multi-chip module the all superconducting integrated spectrometer offers integration of thin film analog components such as a mixer, superconducting local oscillator and an intermediate frequency SQUID amplifier together with superconducting digital circuitry. A Rapid Single Flux Quantum (RSFQ) 128-bit autocorrelator formed by 16-bit autocorrelator and a 112-bit programmable shift register that adjusts the data delay in increments of 16, is used for digitizing of the down converted signals and real-time digital processing. Experimental results showing both operation of components and the way to their successful integration are presented.

We have designed, fabricated and tested the second-generation (2G) design of a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC chip uses the phase modulation–demodulation architecture and on-chip digital filtering. The 2G ADC design has been substantially enhanced. Both ADC front-end modulator and demodulator, as well as decimation digital filter, have been redesigned for operation at 20 GHz. Test results of this 6000 Josephson junction 2G ADC chip at clock frequencies up to 19.6 GHz are described. These test results were compared to the results of ADC functional simulation using MATLAB.

This paper presents the development of an Analog-to-Digital Converter (ADC) based on a low-temperature superconductor (Nb) chip and room-temperature interface modules for applications in digital receivers for communications, radars, and electronic warfare. The ADC design, MATLAB/sup TM/ simulations, and experimental results of single- and two-tone tests are described.

We have developed a high-performance time digitizer system using a superconductor technology for high-energy and nuclear physics detector instrumentation, CMOS chip diagnostics, and military applications. The system consists of an 8-channel, RSFQ multi-hit Time-to-Digital Converter (TDC) integrated into a single system with a semiconductor VXI interface and control modules. The Digitizer operation and output digital data analysis are performed and fully controlled using custom PC-based LabVIEW/sup TM/ software. This all-digital TDC contains eight 9-hit, 14-bit, 20-GHz TDC channels on a 1 cm /spl times/1 cm chip. The TDC chip is capable of operation in Common Start and Common Stop modes. The VXI digitizer part comprises a 200 MS/s, 8-channel data receiver module, a TDC control module, and a commercial VXI-PCI link. The data receiver module converts data into ECL format. The TDC control module based on Xilinx CPLD technology sorts this data and also controls the superconductive RSFQ chip operation by producing all necessary control and readout signals. We present results of operation and experimental performance evaluation of this system.

We have developed an interchip data transmission scheme through passive transmission lines on a multi-chip-module (MCM) carrier and 100-/spl mu/m solder bump bonds. In rapid single flux quantum (RSFQ) logic, digital data are in the form of single flux quantum (SFQ) pulses. A reliable scheme for transmission of SFQ pulses through non-superconducting solder bumps between chips through a passive MCM substrate is yet to be established. Therefore, we have devised a scheme that converts SFQ pulses into toggles in a voltage waveform for interchip transmission. Data in the form of SFQ pulses are reconstructed from this voltage waveform using a sensitive quantizing pulse receiver. Our objective is to eliminate the need for amplification of the transmitted signal. This is achieved by increasing the receiver sensitivity. However, a sensitive receiver, a dc SQUID, may produce more than one SFQ pulse for each rising/falling edge of the voltage waveform. A simple circuit, pulse resurrection logic (PRL), is employed to discard any extra SFQ pulses. Together with the sensitive quantizer, the PRL circuit makes our scheme error tolerant. We have demonstrated the receiver operation using 3-/spl mu/m Nb RSFQ circuits at frequencies up to 20 GHz.

Circuit parameter variations resulting from the fabrication process affect the timing parameters of rapid single flux quantum (RSFQ) digital circuits. This determines the maximum clock rate and the yield of the circuit. It is generally believed that the global parameter variations (target-to-wafer) are much more significant in this regard than the local parameter variations (on-chip), but there has been little experimental evidence for this. This experiment measures the distribution of local parameter variations of the timing parameter of RSFQ circuits. The experiment consists of a 10 by 10 matrix of nominally identical RSF~ "clock rings" covering an integrated circuit area, a total of 3500 Josephson junctions. Each ring is activated individually, and its frequency is measured with accuracy better than 1%.

We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.

Motivated by recent progress in development of cryogenic memory compatible with single flux quantum (SFQ) circuits we have performed a theoretical study of magnetic SIsFS Josephson junctions, where 'S' is a bulk superconductor, 's' is a thin superconducting film, 'F' is a metallic ferromagnet and 'I' is an insulator. We calculate the Josephson current as a function of s and F layers thickness, temperature and exchange energy of F film. We outline several modes of operation of these junctions and demonstrate their unique ability to have large product of a critical current $I_{C}$ and a normal-state resistance $R_{N}$ in the $\pi$ state, comparable to that in SIS tunnel junctions commonly used in SFQ circuits. We develop a model describing switching of the Josephson critical current in these devices by external magnetic field. The results are in good agreement with the experimental data for Nb-Al/AlO${_x}$-Nb-Pd$_{0.99}$Fe$_{0.01}$-Nb junctions., Comment: 10 pages, 5 figures, accepted to Applied Physics Letters

We investigate Magnetic Josephson Junction (MJJ) - a superconducting device with ferromagnetic barrier for a scalable high-density cryogenic memory compatible with energy-efficient single flux quantum (SFQ) circuits. The superconductor-insulator-superconductor-ferromagnet-superconductor (SIS'FS) MJJs are analyzed both experimentally and theoretically. We found that the properties of SIS'FS junctions fall into two distinct classes based on the thickness of S' layer. We fabricate Nb-Al/AlOx-Nb-PdFe-Nb SIS'FS MJJs using a co-processing approach with a combination of HYPRES and ISSP fabrication processes. The resultant SIS'FS structure with thin superconducting S'-layer is substantially affected by the ferromagnetic layer as a whole. We fabricate these type of junctions to reach the device compatibility with conventional SIS junctions used for superconducting SFQ electronics to ensure a seamless integration of MJJ-based circuits and SIS JJ-based ultra-fast digital SFQ circuits. We report experimental results for MJJs, demonstrating their applicability for superconducting memory and digital circuits. These MJJs exhibit IcRn product only ~30% lower than that of conventional SIS junctions co-produced in the same fabrication. Analytical calculations for these SIS'FS structures are in a good agreement with the experiment. We discuss application of MJJ devices for memory and programmable logic circuits., 8 pages,6 figures, Applied Superconductivity Conference (ASC'2012)

We develop a fast Magnetic Josephson Junction (MJJ) - a superconducting ferromagnetic device for a scalable high-density cryogenic memory compatible in speed and fabrication with energy-efficient Single Flux Quantum (SFQ) circuits. We present experimental results for Superconductor-Insulator-Ferromagnet-Superconductor (SIFS) MJJs with high characteristic voltage IcRn of >700 uV proving their applicability for superconducting circuits. By applying magnetic field pulses, the device can be switched between MJJ logic states. The MJJ IcRn product is only ~30% lower than that of conventional junction co-produced in the same process, allowing for integration of MJJ-based and SIS-based ultra-fast digital SFQ circuits operating at tens of gigahertz., 10 pages, 4 figures

It is known that the long annular Josephson junction allows to avoid the influence of boundaries and soliton(fluxon)- soliton collisions on the dynamics of soliton chains. With new experimental methods and junction design a fully controlable way of introducing individual solitons into such a system is realized. For the homogeneous junction crossover at high velocities of the fluxon chain is seen and explained in terms of the fluxon bunching. In the periodically modulated junction a new resonant mode called a supersoliton is observed.

We present an experiment that detects photons by use of an annular Nb-based superconducting tunnel junction (STJ). In one magnetic field configuration, we stably trapped a single magnetic fluxon in the STJ barrier during a transition to the superconducting state. This is an innovative configuration which avoids the use of an externally applied field during detector operation. It offers potential benefits for STJs used in imaging arrays. In this configuration, and also in the conventional one with an externally applied parallel magnetic field, we observed current pulses produced by single 6 keV x-ray photons. The pulses were the same for the two configurations.

We report on the successful operation of partially depleted silicon on insulator (PD-SOI) ring oscillators at temperatures down to 2.8 K. This 45 nm CMOS technology node hardware was fabricated on 300 mm wafers that were part of a development lot not optimized for low temperature operation. The test structure comprises a set of ring oscillators, an output multiplexer and a divide by 1024 circuit followed by an off-chip driver. By reducing the temperature of the device from 300 K to 2.8 K, the static power dissipation decreases by more than an order of magnitude. Circuit delays improve by approximately 20%, 16% from drive current enhancement and 4% from capacitance reduction. To gain further insight on this behavior we are measuring at cryogenic temperatures single MOSFETs and small arrays of MOSFETs that were fabricated alongside the ring oscillators. Experimental results and potential applications of cryogenic PD-SOI are presented.

We report on the experimental observation of a new resonant mode in a spatially modulated annular Josephson junction with a trapped chain of solitons. We observed voltage steps in the current-voltage characteristics of the junction. These steps appear when the spatial periods of the soliton chain and the junction modulation are incommensurate. The effect is explained in terms of the motion of defects (supersolitons) along the pinned soliton chain, which were found earlier iin numerical simulations by Ustinov [Phys. Lett. A 136 (1989) 155].

We present an experiment detecting X-rays by an annular Nb-based Superconducting Tunnel Junction (STJ). In one magnetic field configuration, we stably trapped a single magnetic fluxon in the STJ barrier during the transition to the superconducting state. This is an innovative configuration which avoids the use of an externally applied field during detector operation. This offers potential benefits for STJs used in imaging arrays. In this configuration, and also in the conventional one with an externally applied parallel magnetic field, we observed current pulses produced by single 6 keV X-rays. The pulses were identical for both configurations.

We designed and tested new energy-efficient single flux quantum (eSFQ) circuits. The eSFQ design approach is based on biasing logic gates via decision-making pairs (DMPs) which connect clock lines to synchronous gates. The eSFQ design of asynchronous gates is more challenging, since these gates are not clocked. We demonstrate eSFQ designs of asynchronous circuits and implemented two versions of eSFQ toggle flip-flops (eTFF) cells embedded in a synchronous shift register environment. The first design is based on the bias-free version of a TFF operating in the ballistic mode. In the second design, the TFFs dc bias is applied symmetrically, while the necessary half-quantum phase skew is achieved by magnetic flux bias, which can also be done with a pi-junction phase shifter. Surrounding shift registers are the eSFQ versions of the RSFQ shift register with two junctions per bit. In this work, we report the functional operation of these eSFQ circuits and their energy consumption.

By studying soliton (fluxon) motion in long annular Josephson junctions it is possible to avoid the influence of the boundaries and soliton-soliton collisions present in linear junctions. A new experimental design consisting of a niobium coil placed on top of an annular junction has been used to insert individual fluxons or antifluxons into the junction in a controllable way. The dynamical behavior of different numbers of trapped fluxons was investigated. In addition, we were able to change the junction parameters by changing temperature. In some of the zero-field steps, the experiments reveal a small jump to higher values of the voltage at the top of the steps. This phenomenon can be caused by a crossover from a nonbunched state to a bunched state of the fluxon motion. By performing direct numerical simulations using the perturbed sine-Gordon equation with parameter values determined from the experiments we have been able to confirm the above explanation. ©1996 American Institute of Physics.

We report for the first time the trapping of several solitons (flux quanta) in annular Josephson junctions. We have realized experimentally two different techniques for the magnetic flux trapping in the junctions. First, using low temperature scanning electron microscopy (LTSEM) we applied the electron beam producing a local heating of the top superconducting film and trapped one by one several magnetic flux quanta in the tunnel barrier area of the Josephson junction. Second, by applying the external monopole-like magnetic field by means of a special coil we were also able to trap the flux in the junction at temperatures near the critical temperature of the superconducting electrodes. We have studied the I-V curves of the junction with several trapped solitons and compared the velocity of the soliton chain with one soliton velocity and the perturbation theory. We link the deviations of the soliton chain velocity from the one soliton velocity with the effects of the interaction between solitons and their bunching at high velocity.