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In this paper, the origin of the gate oscillations with a stray capacitance in the load inductor is analyzed with a device/circuit mix-mode simulation. It is found that the gate ringing occurs when the superjunction device reaches its pinch-off potential (the n-pillar and the p-pillar are fully depleted by the lateral depletion process). The progress of the depletion profiles of the superjunction leads to a rapid change of the drain-to-source capacitance and the dV/dt. Finally, the dV/dt causes a sudden change of the current flow rate across the stray capacitance of the load inductor and the device while triggering the parasitic inductances. Based on these results, a comparative study was carried out with an ideal inductive load switching and, finally, the dampers for relieving the gate ringing were investigated.

A trench split gate metal-oxide-semiconductor field-effect transistor (MOSFET) inductive switching is analyzed by adopting six-terminal method. Owing to the buried source terminal in the trench oxide, conventional three-terminal (gate, source, and drain) analysis has a limitation for investigating the detailed time-dependent current flow in the drift region, channel, as well as each terminal. However, a mixed-mode simulation tools enable us to look into the complicated current flow mechanisms in the device by dividing the gate terminal into the gate-to-source and the gate-to-drain terminals and the source terminal into the ${n} +$ , the ${p} +$ , and the shielded source terminals. The six-terminal method enables us to understand the fundamental turn-on and turn-off switching mechanisms that we have not found out so far from the measurement. [ABSTRACT FROM AUTHOR]

This work studies the avalanche characteristics of the 1.2 kV vertical GaN p-n diodes with implanted edge termination, based on quasi-static current-voltage (I-V) sweeps and unclamped inductive switching (UIS) tests. The UIS tests reveal a ~1.7 kV avalanche breakdown voltage ($BV_{{\text {AVA}}}{)}$ , 51 A maximum avalanche current (${I}_{{\text {AVA}}}{)}$ , and 63 mJ maximum avalanche energy (${E}_{{\text {AVA}}}$). The ${I}_{{\text {AVA}}}$ and ${E}_{{\text {AVA}}}$ are the highest reported in high-voltage GaN power devices. A lower $BV_{{\text {AVA}}}$ is observed in the I-V curves and a trap mediated avalanche model is proposed to explain it. The $BV_{{\text {AVA}}}$ in I-V curves is believed to be induced by avalanche-assisted trap-filling in the edge termination region, while the $BV_{{\text {AVA}}}$ in the UIS test reflects the robust avalanche at the main p-n junction. These results provide important new insights on the avalanche breakdown in GaN devices and address some seemingly contrary observations of vertical GaN p-n diodes published recently. [ABSTRACT FROM AUTHOR]

Reactor switching is a test duty for circuit breakers (CBs) in special locations. This duty is characterized by a relatively low current but the CB is stressed with high voltages. Furthermore, this is a stress which will appear frequently in breakers used for switching voltage-control elements. The different international standards define test procedures, which should be used to determine the CB characteristic and the withstand capability for the corresponding operating voltages. Usually, HV CBs need to be tested in synthetic test circuits. Due to the strong interaction between CBs and network synthetic test circuits, it is not possible to be used for inductive switching. Also, the direct test circuit may not be available due to the necessary short-circuit power and the required test voltages. Therefore, a test method has been developed to obtain the necessary information in a multistep method combining testing and calculation. Using the proposed method will enable smaller testing stations to give judgment on CB capabilities. For other very high requirements where even no test possibilities may exist, it will provide some evidence avoiding field tests. A validation of the presented multistep method is given in this paper. [ABSTRACT FROM AUTHOR]

SiC vertical MOSFETs were fabricated and characterized, achieving blocking voltages around 1 kV and specific on-resistances as low as RSP,ON = 8.3 mΩ · cm². DC and transient characteristics are shown. Room and elevated temperature (up to 200 °C) 600V/5A inductive switching performance of the SiC MOSFETs are shown with turn-on and turn-off transients of approximately 20-40 ns. [ABSTRACT FROM AUTHOR]