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6 results on '"J. Goguet"'

1. Implementation of Electron–Phonon Scattering in a CNTFET Compact Model

Author

Thomas Zimmer, Cristell Maneux, Sebastien Fregonese, J. Goguet, Fregonese, Sebastien, Programme National en Nanosciences et Nanotechnologies (PNANO) - Action Calcul Composants En NanoTubes de carbone : simulation multi-échelle, de l'atomistique au circuit - - ACCENT2006 - ANR-06-NANO-0069 - PNANO - VALID, Laboratoire de l'intégration, du matériau au système (IMS), Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1, and ANR-06-NANO-0069,ACCENT,Action Calcul Composants En NanoTubes de carbone : simulation multi-échelle, de l'atomistique au circuit(2006)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Circuit design, 02 engineering and technology, CNTFET, 01 natural sciences, Light scattering, Ballistic conduction, 0103 physical sciences, Electronic engineering, Figure of merit, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, phonon, 010302 applied physics, Physics, Operating point, Phonon scattering, Scattering, scattering, non-ballistic transport, 021001 nanoscience & nanotechnology, Carbon, compact mode, Electronic, Optical and Magnetic Materials, Carbon nanotube field-effect transistor, nanotube, transistor, 0210 nano-technology
Abstract

International audience; This paper presents an extension of a ballistic compact model to the case of nonballistic transport for the conventional carbon nanotube FET featuring a MOSFET-like operation. A large part of the novelty lies on the analytical implementation of acoustic phonon (AP) and optical phonon (OP) scattering mechanism. To carry out this implementation, some simplifications of the theoretical description are proposed while staying as close as possible to physics and keeping the high-speed simulation and good convergence capability of the compact model. The compact model simulation results are systematically compared and validated with respect to nonequilibrium Green function simulation results. Then, we have investigated the impact of AP and OP scattering on transistor figures of merit. Taking into account the scattering processes is of utmost importance for both analog and digital circuit designs, since neglecting the scattering leads to an overestimation of more than 70% of the main figures of merit and will mislead designers when optimizing the operating point for analog applications.

Published
2009
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2. Compact Model of a Dual Gate CNTFET: Description and Circuit Application

Author

J. Goguet, C. Maneux, T. Zimmer, S. Fregonese, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1

Subjects
Materials science, Schottky barrier, Nanotechnology, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, Capacitance, law.invention, Computer Science::Hardware Architecture, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, Transistor, Charge (physics), Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, 021001 nanoscience & nanotechnology, Carbon nanotube field-effect transistor, Logic gate, Field-effect transistor, 0210 nano-technology, Hardware_LOGICDESIGN, Communication channel
Abstract

We present a physical compact model of a dual gate carbon nanotube field effect transistor (DG CNTFET). To obtain an accurate and predictive model, the expression of the drain current is based on the description of the local channel potentials as well as the injected charge. The comparison between the simulation results and experiments highlights the influence of the parasitic Schottky barrier at high injection level. Hence, assuming a higher DG-CNTFET technology maturity, this predictive model allows to evaluate the performance of logic circuits in terms of reconfigurable architecture.

Published
2008
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3. Computationally Efficient Physics-Based Compact CNTFET Model for Circuit Design

Author

Thomas Zimmer, Sebastien Fregonese, Cristell Maneux, H. Cazin d'Honincthun, Jean-Philippe Bourgoin, Philippe Dollfus, J. Goguet, S. Galdin-Retailleau, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1 (UB)-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Département de Recherche sur l'Etat Condensé, les Atomes et les Molécules (DRECAM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-06-NANO-0069,ACCENT,Action Calcul Composants En NanoTubes de carbone : simulation multi-échelle, de l'atomistique au circuit(2006), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), ANR: ACCENT & HF CNTFET,ACCENT & HF CNTFET, and Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1

Subjects
Engineering, Circuit design, Monte Carlo method, technological dispersion, 02 engineering and technology, Ring oscillator, CNTFET, 01 natural sciences, Carbon nanotube, law.invention, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Monte Carlo simulation, 010302 applied physics, Computer simulation, business.industry, Transistor, Propagation delay, compact modeling, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Carbon nanotube field-effect transistor, Nanoelectronics, transistor, 0210 nano-technology, business
Abstract

International audience; Abstract—We present a computationally efficient physics-based compact model designed for the conventional CNTFET featuring a MOSFET-like operation. A large part of its novelty lies on the implementation of a new analytical model of the channel charge. In addition, Boltzmann Monte Carlo (MC) simulation is performed with the challenge to cross-link this simulation technique to the compact modeling formulation. The comparison of the electrical characteristics obtained from the MC simulation and from the compact modeling demonstrates the compact model accuracy within its range of validity. Then, from a study of the CNT diameter dispersion for three technological processes, the compact model allows us to determine the CNTFET threshold voltage distribution and to evaluate the resulting dispersion of the propagation delay from the simulation of a ring oscillator.

Published
2008

4. A Charge Approach for a Compact Model of Dual Gate CNTFET

Author

Thomas Zimmer, J. Goguet, Sebastien Fregonese, Cristell Maneux, Laboratoire de l'intégration, du matériau au système (IMS), Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1, Fregonese, Sebastien, and Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Physics, business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Transistor, Gate dielectric, Electrical engineering, Charge (physics), 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, 01 natural sciences, Carbon nanotube field-effect transistor, law.invention, Transmission (telecommunications), law, Gate oxide, 0103 physical sciences, Optoelectronics, Field-effect transistor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Energy (signal processing)
Abstract

International audience; We present a physical approach to model the Dual Gate CNTFET. In this transistor, whose type (N or P) depends on the Back Gate bias, the charge of each region (source and drain accesses and inner part) remains an essential quantity to evaluate the channel potential and thus the drain current. The charges are calculated (i) considering 0 or 1 carrier transmission probability and (ii) assuming that the carrier energy is not affected by backscattering mechanisms to obtain a physical compact description. Using this compact model, typical electrical characteristics of such transistor are presented.

Published
2008

5. CNTFET modeling and reconfigurable logic circuit design

Author

Sebastien Fregonese, Thomas Zimmer, Frédéric Gaffiot, Regis Leveugle, Trong-Trinh Dang, Christophe Lallement, Liu Junchen, Fabien Prégaldiny, Ian O'Connor, Cristell Maneux, J. Goguet, Lorena Anghel, Institut des Nanotechnologies de Lyon (INL), Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Université de Lyon-École Centrale de Lyon (ECL), Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE), Laboratoire Physique de l'Homme Appliquée à Son Environnement (PHASE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées, Institut d'Electronique du Solide et des Systèmes (InESS), Université Louis Pasteur - Strasbourg I-Centre National de la Recherche Scientifique (CNRS), Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), INL - Conception de Systèmes Hétérogènes (INL - CSH), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École Centrale de Lyon (ECL), Université de Lyon, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Laboratoire de Physique des Composants à Semiconducteurs (LPCS), École Nationale Supérieure d'Électronique et de Radioélectricité de Grenoble (ENSERG)-Centre National de la Recherche Scientifique (CNRS), University Politehnica of Bucharest [Romania] (UPB), CSI, INPG, Grenoble (CSI), Institut National Polytechnique de Grenoble (INPG), and CSI, Inst. Nat. Polytech. de Grenoble, France (CSI)

Subjects
Computer science, Circuit design, circuit-design, 02 engineering and technology, CNTFET, 01 natural sciences, law.invention, law, 0103 physical sciences, MOSFET, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, Design technology, 010302 applied physics, business.industry, Transistor, Electrical engineering, 021001 nanoscience & nanotechnology, Carbon nanotube field-effect transistor, Logic synthesis, PACS 8542, Logic gate, Field-effect transistor, 0210 nano-technology, business, Hardware_LOGICDESIGN
Abstract

International audience; This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.

Published
2007
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6. Analysis of CNTFET physical compact model

Author

Sebastien Fregonese, H. Cazin d'Honincthun, S. Galdin-Retailleau, Thomas Zimmer, J. Goguet, Cristell Maneux, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Institut d'électronique fondamentale (IEF), and Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Logical disjunction, Materials science, compact, Basis (linear algebra), carbon, 02 engineering and technology, CNTFET, 021001 nanoscience & nanotechnology, 01 natural sciences, Carbon nanotube field-effect transistor, modelling, Maxima and minima, 0103 physical sciences, nanotube, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Equivalent circuit, Field-effect transistor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, ComputingMilieux_MISCELLANEOUS, Energy (signal processing), Hardware_LOGICDESIGN, Electronic circuit
Abstract

On the basis of acquired knowledge, the paper present a DC compact model designed for the conventional CNTFET (C-CNTFET) featuring a doping profile similar to n-MOSFET. The specific enhancement lies on the implementation of a physical based calculation of the minima of energy conduction subbands. This improvement allows a realistic analysis of the impact of CNT helicity and radius on the DC characteristics. The purpose is to enable the circuit designers to challenge CNTFET potentialities for performing logical or analogical functionalities within complex circuits

Published
2006
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