Search

Broadband phototransistors have attracted considerable attention for numerous applications.

This study investigated the effect of hydrogen (H) on the performance of amorphous In-Ga-Zn-Sn oxide (

In this paper, the feasibility of an indium-gallium oxide (In

Amorphous indium-gallium-zinc oxide (

In this study, we examine the effect of oxygen vacancies ( ${V}_{O}$ ) near the back surface of p-type tin monoxide (SnO) semiconductors on the device performance of its thin-film transistors (TFTs). Non-stoichiometry of the SnO surface layer was controlled through oxidant exposure conditions during alumina (Al2O3) growth using plasma-enhanced atomic layer deposition (PEALD). During the initial period of Al2O3 deposition, trimethylaluminum precursors absorbed oxygen from the SnO layer and created the ${V}_{O}$ , which can form a ${V}_{O}$ -rich region at the Al2O3/SnO interface. By modulating the oxygen plasma density during the PEALD process, the ${V}_{O}$ was effectively controlled, allowing the electrical characteristics to transition from ambipolar behavior to ${p}$ -channel only conduction. This study demonstrates the importance of the back surface of SnO, suggesting a new perspective of ambipolar behavior in p-type SnO semiconductors.

In this work, high-performance amorphous In0.75Ga0.23Sn0.02O (a-IGTO) transistors with an atomic layer-deposited Al2O3 dielectric layer were fabricated at a maximum processing temperature of 150 °C. Hydrogen (H) and excess oxygen (Oi) in the Al2O3 film, which was controlled by adjusting the oxygen radical density (PO2: flow rate of O2/[Ar+O2]) in the radio-frequency (rf) plasma during ALD growth of Al2O3, significantly affected the performance and stability of the resulting IGTO transistors. The concentrations of H and Oi in Al2O3/IGTO stacks according to PO2 were characterized by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, hard X-ray photoemission spectroscopy, and thermal desorption spectroscopy. The high concentration of H at a low PO2 of 2.5% caused heavy electron doping in the underlying IGTO during thermal annealing at 150 °C, leading to a conductive behavior in the resulting transistor without modulation capability. In contrast, a high PO2 condition of 20% introduced O2 molecules (or Oi) into the Al2O3 film, which negatively impacted the carrier mobility and caused anomalous photo-bias instability in the IGTO transistor. Through in-depth understanding of how to manipulate H and Oi in Al2O3 by controlling the PO2, we fabricated high-performance IGTO transistors with a high field-effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V, and ION/OFF ratio of ∼109 even at the maximum processing temperature of 150 °C. Simultaneously, the optimized devices were resistant to exposure to external positive gate bias stress (PBS) and negative bias stress (NBS) for 3600 s, where the VTH shifts for exposure to PBS and NBS for this duration were 0.1 V and -0.15 V, respectively.

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through a pillar in the P+ crystal silicon sub-region located at the bottom of the 3D NAND flash structure to which the COP structure is applied. To verify this, we first confirmed that when the Gate Induced Drain Leakage (GIDL) erasing method used in the 3D NAND structure using the existing Charge Trap Flash (CTF) memory is applied as it is, the operation speed takes more than 10ms, for various reasons. Next, as a result of using the SP structure to solve this problem, even if the conventional erasing method was used until the thickness of the pillar was 20 nm, thanks to the rapidly supplied hole carriers, a fast-erasing rate of 1us was achieved. Additionally, this result is up to 10,000 times faster than the GIDL deletion method. Next, it was confirmed that when the pillar thickness is 10 nm, the erase operation time is greatly delayed by the conventional erasing method, but this can also be solved by appropriately adjusting the operating voltage and time. In conclusion, it was confirmed that, when the proposed SP structure is applied, it is possible to maximize the fast operation performance of the ferroelectric memory while securing the biggest advantage of the 3D NAND flash structure, the degree of integration.

For portable and low-power flexible devices, metal-oxide (M − O) materials offer high performance, superior stability, and a low-cost printing process that permits facile mass production. However, realization of printed flexible electronics using inorganic M − O materials has proven challenging because of obstacles associated with producing high-quality and dense dielectric films through a solution process at low temperatures. In this study, the effect of the solution stirring temperature and H2O2 loading on the structural and electrical properties of lanthanum zirconium oxide (LZO) dielectric films was investigated in detail. The surface roughness, mass density, and purity of H2O2–assisted LZO improved with increasing stirring temperature, resulting in a low leakage current of 4 × 10−8 A/cm2 at 2 MV/cm, a high-breakdown electric field of ~5.8 MV/cm, and relatively high permittivity (>12) at a low photochemical activation temperature of 180 °C for optimized LZO dielectric films. This can be attributed to the synergetic interaction of oxygen radicals introduced by H2O2 oxidants during deep ultraviolet photochemical annealing, causing hydrolysis of metal precursors, removal of organic residue, and formation of an M − O lattice. The fabricated indium gallium oxide thin-film transistor on a polyimide substrate at a maximum processing temperature of 180 °C exhibited a high mobility of 14.5 cm2/Vs, a high ION/OFF ratio of 107, negligible hysteresis, and a small driving voltage range (−2 to 2 V).

This letter reports the fabrication of high performance polycrystalline InGaSnO (IGTO) thin-film transistors (TFTs) at a low temperature of 400 °C. The microstructure of IGTO films was analyzed using X-ray diffraction and high-resolution transmission electron microscopy. The fabricated polycrystalline IGTO TFTs exhibited an unexpected high mobility of 116.5 cm2/Vs, threshold voltage of 0.47 V, low subthreshold gate swing of 134 mV/decade, and ${I}_{ON/OFF}$ ratio of $> 1\times 10^{9}$ . Moreover, the stable behavior against external gate bias stress was observed for crystalline IGTO TFTs, which was attributed to the high degree of metal-oxygen lattice ordering.

We report on a stable and sensitive biochemical sensor based on amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with a versatile extended-gate electrode used as the sensing membrane. The extended-gate allows the active transistor channel not to be exposed to the ionic analyte and the gate surface may be modified with chemicals or affinity reagents without affecting the operation of the active sensor. The extended-gate a-IGZO TFT was able to detect the pH levels of various solutions based on protonation and deprotonation at the surface of the indium-tin-oxide (ITO) extended-gate electrode achieving a pH dependent threshold voltage shift of 22.8 mV/pH. Highly sensitive and specific protein sensing was achieved for both electrical polarities according to pH values of solutions using the biotin-streptavidin interaction. The extended-gate TFT sensor demonstrated a detection limit for streptavidin down to 10 fM, using the biotin-streptavidin binding on the extended-gate surface. It was also possible to detect changes in the streptavidin concentration in real-time with specificity and repeatability. Since the extended-gate can be easily replaced without affecting the performance of the a-IGZO TFT, this sensor configuration may be utilized for future multifunctional biomolecular sensing and analysis.

This study examines the impact of channel length ( $L$ ) on the performance of amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors with self-aligned structures. The negative threshold voltage ( ${V}_{\text{TH}}$ ) displacement for IGZO transistors with increasing drain voltage ( ${V}_{\text{DS}}$ ) becomes severe with decreasing ${L}$ from 10 to $2~ \mu \text{m}$ . The $V_{\text{DS}}$ -dependent negative $V_{\text{TH}}$ shift can be mitigated by increasing the oxygen flow rate (OFR) ratio during a-IGZO preparation from 40% to 80%, which suppresses the number of oxygen vacancy defects near the n+ drain of the a-IGZO region. In contrast, the hot carrier stress (HCS)-induced degradation in terms of the threshold voltage was accelerated for devices with increasing OFR ratio, presumably due to the creation of excessive oxygen-originated defects. The rationale for these observations is discussed with regard to the increasing local electric field near the drain junction, which was calculated by technology computer-aided design (TCAD) simulation. We concluded that an acceptable compromise between short channel effect and HCS-induced degradations can be achieved by choosing an intermediate OFR ratio of 64%.

Low-temperature (≤400 °C), stackable oxide semiconductors are promising as an upper transistor ingredient for monolithic three-dimensional integration. The atomic layer deposition (ALD) route provides a low-defect, high-quality semiconducting oxide channel layer and enables accurate controllability of the chemical composition and physical thickness as well as excellent step coverage on nanoscale trench structures. Here, we report a high-mobility heterojunction transistor in a ternary indium gallium zinc oxide system using the ALD technique. The heterojunction channel structure consists of a 10 nm thick indium gallium oxide (IGO) layer as an effective transporting layer and a 3 nm thick, wide band gap ZnO layer. The formation of a two-dimensional electron gas was suggested by controlling the band gap of the IGO quantum well through In/Ga ratio tailoring and reducing the physical thickness of the ZnO film. A field-effect transistor (FET) with a ZnO/In

An organic-inorganic hybrid superlattice with near perfect synergistic integration of organic and inorganic constituents was developed to produce properties vastly superior to those of either moiety alone. The complementary hybrid superlattice is composed of multiple quantum wells of 4-mercaptophenol organic monolayers and amorphous ZnO nanolayers. Within the superlattice, multichannel formation was demonstrated at the organic-inorganic interfaces to produce an excellent-performance field effect transistor exhibiting outstanding field-effect mobility with band-like transport and steep subthreshold swing. Furthermore, mutual stabilizations between organic monolayers and ZnO effectively reduced the performance degradation notorious in exclusively organic and ZnO transistors.

This article reports the fabrication of high-performance amorphous indium gallium zinc tin oxide ( ${a}$ -IGZTO) thin-film transistors (TFTs) with superior bias stability. For comparison, amorphous indium gallium zinc oxide ( ${a}$ -IGZO) TFTs were also investigated to clarify the origin of the superior performance of IGZTO TFTs. It was found that the simultaneous heavy loading of In and Sn into the IGZTO system facilitated an effective mass densification, leading to a reduction in tail states and deep states. The fabricated ${a}$ -IGZTO TFTs exhibited a high electron mobility ( $\boldsymbol {\mu }_{\text {FE}}$ ) of 46.7 cm2/Vs, a subthreshold swing (SS) gate of 0.15 V/decade, and an ${I}_{\text {ON/OFF}}$ ratio $> {1} \times {10}^{{8}}$ . Furthermore, greater gate-bias stress stability was observed for the IGZTO TFTs compared with the IGZO TFTs.

A low on–off current modulation ratio (ION/OFF) in p-type tin monoxide (SnO) field-effect transistors (FETs) is a critical bottleneck hampering their widespread application to transparent complementary metal oxide semiconductors (CMOSs) or monolithic integrated devices. To solve this problem, this study focuses on the source/drain (S/D) contact region. Also, a new perspective on the origin of the high off-current in SnO FETs, an electron injection from the drain electrode into the channel by Fermi-level pinning (FLP) at the off-state, is suggested. In this work, a metal–interlayer–semiconductor (MIS) S/D contact structure is adopted to suppress this adverse electron injection. An ultrathin interlayer (IL) of MIS contact alleviates metal-induced gap state (MIGS) penetration which is a primary cause of the severe FLP. A considerable enhancement is achieved by using the MIS contact structure: the off-current value decreased by approximately 20-fold from 5.1 × 10−8 A to 2.4 × 10−9 A; the ION/OFF value increased 10-fold from 2.7 × 102 to 2.8 × 103, which is interpreted by increased MIS contact-mediated electron SBH. This work presents a new approach that can be easily used alongside previously reported methods to suppress the off-current, providing enhanced switching capability of p-type SnO FETs using a simple method.

As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors (OS) have gained tremendous attention to continue the ever-demanding downscaling represented by Moore's law. Amongst, OS is considered to be the most promising alternative material because it has intriguing features such as modest mobility, extremely low off-current, great uniformity, and low temperature processibility with conventional complementary metal oxide semiconductor-compatible methods. In practice, OS has successfully replaced hydrogenated amorphous Si in high-end liquid crystal display devices and has now become a standard backplane electronic for organic light-emitting diode displays despite the short time since their invention in 2004. For OS to be implemented in next generation electronics such as back-end-of-line transistor applications in monolithic three-dimensional integration beyond the display applications, however, there is still much room to be studied such as high mobility, imune short-channel effects, and low electrical contact properties etc. This study reviews the brief history of OS and recent progress in device applications from a material science and device physics point of view. Simultaneously, remaining challenges and opportunities in OS for use in next generation electronics are discussed. This article is protected by copyright. All rights reserved.

Effects of lanthanum (La) loading on the structural, optical, and electrical properties of tin monoxide (SnO) films were examined as a p-type semiconducting layer. La loading up to 1.9 atom % caused the texturing of the tetragonal SnO phase with a preferential orientation of (101), which was accompanied by the smoother surface morphology. Simultaneously, the incorporated La cation suppressed the formation of n-type SnO

We propose a novel structure to solve the hole erase problem of Indium-Gallium-Zinc-Oxide (IGZO) channels. The proposed structures are an IGZO-nitride-P filler (INP) structure and an IGZO-P filler (IP) structure. In the simulations using both structures, stable operation and erase efficiency can be achieved in an INP structure when the nitride barrier thickness is 7 nm. The erase performance achieved exceeds that of the polysilicon channel under the same conditions. Conversely, if the nitride thickness exceeds 8 nm, the read operation becomes unstable. Therefore, nitride thickness is an important parameter in the operation of an INP structure, and its maximum value is 7 nm. For improving upon this INP structure, the nitride was removed to create an IP structure, in which, leakage currents could be limited by reducing doping concentration. In particular, such an IP structure showed that the maximum erase performance (2 ms) of the polysilicon channel can only be achieved at $2.3~\mu \text{s}$ , and then the erase operation can continue. This result is due to lack of electron accumulation in the channel and their ability to move quickly through the filler directly connected to the IGZO channel. As a result, both proposed structures have shown that low erase performance can be overcome without sacrificing the excellent leakage current blocking characteristics of IGZO material.

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the &ldquo, Y-mode&rdquo, operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.

In this Letter, we report a demonstration of p-channel tin monoxide (SnO) thin-film transistors (TFTs) with high field-effect mobility ( μFE) exceeding 10 cm2/Vs and hysteresis-free like behavior. We demonstrate that maintaining metallic states before encapsulation is a key process to enhance μFE in p-type SnO thin-films. Sustaining this meta-stability involves the following two processes during fabrication: (1) postdeposition annealing (PDA) in two steps and (2) encapsulation in the middle of each PDA. This simple process not only suppresses creation of oxidized states such as adverse Sn4+ but also facilitates the lateral growth of crystals with improved crystallinity by interfacial energy stabilization. The resultant SnO TFT reveals a record-high μFE up to 15.8 cm2/Vs with a negligible hysteresis of 0.1 V. This study suggests a practical route to grant high μFE to p-channel SnO TFTs without any dopant or complex postdeposition treatment.

In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV.

This work was supported by the industrial strategic technology development program funded by MKE/KEIT under grants 10079974 and Samsung research funding center for future technology through Samsung Electronics

This study examined the effect of maternal positive parenting attitudes on school adjustment among multi-cultural adolescents in Korea and investigated if multi-cultural adolescents’ ego-resiliency mediates the relationship between maternal positive parenting attitudes and school adjustment. We used panel data from the fifth wave (2015) of the Multicultural Adolescents Panel Study (MAPS) collected by the National Youth Policy Institute. Participants were 1,297 multi-cultural adolescents (639 boys, 658 girls) who are second-year middle school students and have foreign mothers. SPSS 25.0 performed descriptive statistical analysis and correlation analysis. The structural equation model (SEM) was estimated with Mplus 5.12. The results of this study were as follows. First, a higher level of maternal positive parenting attitudes were related to higher level of ego-resiliency and school adjustment for multi-cultural adolescents. Second, maternal positive parenting attitudes had an indirect effect on school adjustment for multi-cultural adolescents via ego-resiliency. The results of this study indicate that maternal positive parenting behaviors would help improve the school adjustment of multi-cultural adolescents by increasing the level of ego-resiliency. In addition, the results of this study suggest that improving ego-resiliency for multi-cultural adolescents can be an effective method to help in school adjustment, as well as education for maternal parenting attitude.

With potentials to outperform traditional semiconductors, oxide semiconductors are penetrating into a wide range of energy, environmental, and electronic applications. However, an insufficient libr...

Novel TaO x encapsulation was presented to enhance the field-effect mobility (μFE) of ZnON thin-film transistors (TFTs) consisting of a metallic Ta film deposited onto the ZnON surface followed by a modest annealing process. The resulting TaO x/ZnON film stack exhibited a more uniform distribution of nanoscale ZnON crystallites with increased stoichiometric anion lattices compared to the control ZnON film. The control ZnON TFTs exhibited a reasonable μFE, subthreshold gate swing (SS), and ION/OFF ratio of 36.2 cm2/V·s, 0.28 V/decade, and 2.9 × 108, respectively. A significantly enhanced μFE value of 89.4 cm2/V·s was achieved for ZnON TFTs with a TaO x encapsulation layer, whereas the SS of 0.33 V/decade and ION/OFF ratio of 8.6 × 108 were comparable to those of the control device. This improvement could be explained by scavenging and passivation effects of the TaO x film on the ZnON channel layer. Density of states (DOS)-based modeling and simulation were performed to obtain greater insight with regard to increasing the performance of the ZnON TFTs with a TaO x encapsulation layer. A smaller number of subgap states near the conduction band (CB) minimum and a higher net carrier density for the TaO x-capped device increased the Fermi energy level toward the CB edge under thermal equilibrium conditions, leading to efficient band conduction and fast carrier transport under the on-state condition.