Search

This brief presents a power- and area-efficient forwarded-clock (FC) receiver with a delay-locked loop (DLL)-based self-tracking loop for unmatched memory interfaces. In the proposed FC receiver, the self-tracking loop is composed of two-stage cascaded DLLs to support a burst mode. The proposed scheme compensates for a delay drift neither by relying on data (DQ) transitions nor by re-training but with a write training of the memory controller to fine-tune a data strobe (DQS) path delay through DLLs. The proposed FC receiver is fabricated in the 65-nm CMOS technology and the active area including 4 DQ lanes is 0.0329 mm2. After the write training is completed at supply voltage of 1 V, the measured timing margin remains larger than 0.31 UI when the supply voltage drifts in the range of 0.94 V and 1.06 V from the training voltage, 1 V. At the data rate of 6.4 Gb/s, the proposed FC receiver achieves an energy efficiency of 0.45 pJ/bit.

Skews between data and strobe signals can occur in HBM transceivers due to process and voltage variations across the base die. Skew compensation is introduced into the deserializers of our quarter-rate single-ended receiver for next-generation unmatched source-synchronous HBM interfaces. Data and strobe signals are energy-efficiently realigned by using a 45° strobe phase DQS45. This phase, which is equidistant between quadrature strobe phases DQS0 and DQS90, is generated by a digital type phase interpolator of our receiver. The transceiver, including the proposed receiver, was designed and fabricated in a 65nm CMOS process. The receiver corrects skews to within 7.8ps at a data-rate of 6.4Gb/s, with an energy cost of 0.83pJ/bit per pin.

This brief presents a 9Gb/s transmitter for intra-panel interfaces, with dual-loop calibration and a 2D binary-segmented driver. The dual-loop calibration during the training period compensates the transmitter output for the variations in operating conditions such as supply voltage and reference current. The 2D binary-segmented driver provides wide range and high resolution output characteristics, and independent adjustments for VOD, VCM and FFE strength while maintaining signal integrity. The transmitter reduces power consumption by optimizing the output for the channel. A prototype chip, fabricated in a 55nm CMOS process, occupies 0.057mm2. It provides FFE strength from 0dB to 26.4dB, common-mode voltage from 260mV to 690mV, and differential output voltage from 100mVppd to 1200mVppd, which varies by less than 4% across supply voltage and reference current variations. It also consumes 36mW at a data-rate of 9Gb/s with a 1.2V supply.

This paper proposes a fractional-N phase-locked loop (PLL) with a transition-detection DAC (TD-DAC) for jitter reduction. By introducing a TD-DAC, the sigma-delta modulator (SDM) quantization error of the PLL is compensated, and its overall jitter performance is improved. In order for the output frequency to cover the output frequency range of voltage controlled oscillator (VCO), the division ratio of the multi-modulus divider (MMD) is extended. Implemented in a 110nm CMOS process, the proposed fractional-N PLL dissipates 7.9mA from a 1.5V and 3.3V supply while occupying an area of 0.284mm2. It operates over a frequency range of 0.4-1.7GHz, and a division range 4-4048. The prototype chip achieves an integrated RMS jitter of 3.78ps (100Hz to 40MHz), and the long-term jitter of it is 3.52ps rms and 22.1ps pp .

The increasing data rate of serial links makes it difficult to match timing constraints of serializers in transmitters. Delay compensation clock buffers can alleviate this issue by matching the timing between data and clock. However, these buffers consume significant power and become sources of noise to the transmitter output. The problem is more serious for serializers other than 2n:1, and using only 2n:1 serializer could be a limitation on system design. In this paper, a 20:1 serializer using two calibration feedback loops is presented to solve this issue and reduce power consumption. The two loops detect the phase difference between data and clock, and automatically align the clock phase to the center of the data phase. The loops eliminate the power-consuming clock buffers on the critical clock path and operate at maximum quarter rate, enabling the transmitter to have low power consumption and high performance. A 6.4 Gb/s serializer prototype is fabricated in 55-nm CMOS process with a 1.2 V supply voltage. It achieves 97.5 ps eye width, which is 62.4% of a unit interval (UI) using PRBS-7 data, and its energy efficiency is 1.60 pJ/bit.

This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage difference and detects the phase skew from the voltage difference. An offset calibration scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing circuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver operates without any performance degradation under ${a}\pm 10$% supply variation.