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A silicon/silicon carbide (Si/SiC) hybrid switch (HyS), comprised of a high-current Si insulated gate bipolar transistor and a low-current SiC metal oxide semiconductor field effect transistors, gains attention because it offers lower on-state loss under both light and heavy loads. However, the dynamic overcurrent stress experienced by the HyS under the heavy load has to be coped with to avoid reliability degradation and the maximum current rating limitation. This article comprehensively studies how gate resistances regulate the dynamic behavior of the HyS under the heavy load condition. Experiments and analyses are conducted for both turn-on and turn-off processes. It is found that the gate resistance is important for not only the dv/dt control but also the overcurrent suppression. Moreover, the lower switching loss can be achieved by adjusting gate resistances when the HyS operates at a heavy load, compared with the gate timing control. A guideline is developed for the design of the gate resistances. This study offers an insight into the role of gate resistances in switching performances of the HyS and an alternative way of coping with the dynamic overstress stress. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are regarded as the key device for the next generation of power electronics. However, wide applications are hindered by the threshold voltage instability. How the threshold voltage drifts under both static and dynamic gate stress has been reported. But the underpinning mechanism remains to be revealed, which is the basis of the exploration of the application solutions. This letter is to investigate why the threshold voltage drifts. It is found that the local electric field plays the key role behind the threshold instability, which is a function of dVGS/dt. Based on that, a physical model is proposed and experimentally verified. These findings provide not only a way to understand the mechanism but also a hint of how to mitigate the threshold instability by active gating in power electronics applications. [ABSTRACT FROM AUTHOR]

For silicon carbide power mosfets, high dv/dt in switching may bring about a high level of electromagnetic interference. This letter shows that the dv/dt rate decreases at lower load currents. A dynamic dv/dt control strategy is then proposed for switching loss reduction in the whole operating range, by maintaining the dv/dt at the maximum acceptable level. The effectiveness of the proposed control strategy is verified by an experiment, showing that the total switching loss can be reduced by as much as 22% at 30% load. Furthermore, the simulation shows that a power loss reduction of 11.4% can be obtained for an electric vehicle converter which typically operates at light loads for most of the time. [ABSTRACT FROM AUTHOR]

As the silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistor (MOSFET) develops, increasing efforts are placed on ac bias temperature instability (AC BTI). It was reported that AC BTI becomes significant when and only when the gate stress is bipolar. A detailed study is made in this article to reveal the underpinning mechanism. A physical model is proposed to explain on how and why the gate stress bipolar affects the threshold drift. It is found that the gate stress polarity has to be carefully defined. As the model shows, it is the bipolar electric field, rather than the gate voltage itself, that speeds up the threshold voltage drift. It is hoped that this study provides a stepping stone toward the eventual understanding and management of AC BTI. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]

In a harsh environment, power modules have to be subjected to deep power cycling, which causes large temperature fluctuations and, hence, leads to fatigue stresses. Reducing the junction temperature fluctuation of chips can significantly improve power module reliability. This article proposes a power module design with considerably reduced junction temperature fluctuation by using phase change material (PCM) as a part of thermal management. Cyclical power is applied to the proposed power module, and experiment results show that the reduction of junction temperature fluctuation is effective in a certain range of power periods. Thermodynamic simulations are used to illustrate the mechanism of PCM in reducing junction temperature fluctuation and the factors influencing the optimal range of power periods. With the significant reduction of junction temperature fluctuation, the reliability of the proposed power module is enhanced. The approach is significant to improve the reliability of power modules in power fluctuating conditions. [ABSTRACT FROM AUTHOR]

A comparative study on SiC MOSFETs is carried out with an emphasis on the design of integrated Schottky barrier diode (SBD) with numerical simulations by Sentaurus TCAD. Compared with the conventional SiC MOSFET (C-MOS) and the conventional SBD-embedded SiC MOSFET (C-MOSBD), the MOSFET (M-MOSBD) features a hybrid doping mesa above the JFET region where a Schottky contact is formed, which exhibits a superior trade-off between the on-state resistance (R dson) and the reverse transfer capacitance (C rss). Besides, the integrated diode in M-MOSBD renders a better trade-off between OFF-state junction field (E Smax) and forward voltage (V F) when compared to C-MOSBD and the conventional junction barrier Schottky diode (JBS), i.e., the external SBD of C-MOS. In the double pulse test simulation, C-MOS exhibited the largest switch loss followed by C-MOSBD, and M-MOSBD is the smallest. Therefore, in power switching applications where reverse conduction is required, M-MOSBD greatly reduces the chip area while presenting better characteristics. [ABSTRACT FROM AUTHOR]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]

A number of studies have focused on Insulated Gate Bipolar Transistor (IGBT) junction temperature prediction methods. Some methods introduce extra circuits or sensors for an invasive prediction. However, the most of current methods hardly consider the situation that the junction temperature prediction may be affected by the IGBT degradation after long term operation. In this paper, the neural network using DC link voltage, switching frequency, load current and Negative Thermal Coefficient thermistor (NTC) temperature as inputs is proposed for junction temperature online prediction. The neural network training is completed through the IGBT module tests. The accelerated aging tests are then performed to validate the neural network results over lifetime. The static and transient working conditions are respectively validated at different aging degrees. Finally, a neural network with good accuracy could be achieved by a series of experiments considering IGBT device degradation. [ABSTRACT FROM AUTHOR]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

DC bias in a transformer is a threat to the safe and efficient operation of dual active bridge (DAB) converters. Detecting a dc component in milliamperes mixed with a large ac current is difficult. This article proposes a current sensor based on ac magnetic flux (MF) cancellation. The proposed sensor utilizes a current transformer (CT) to extract the ac component in the measured current. Then, a power op-amp copies the CT signal to an additional winding to generate an ac MF opposite to that of the main ac current. Hence, the sensor range required to measure the dc is greatly reduced for a much smaller absolute measurement error. Using only a CT and a simple op-amp circuit, the proposed solution features low complexity and power consumption. The relative error in a range of 15-A ac current is 0.038%, showing a five-fold improvement compared to off-the-shelf sensors. The proposed sensor is verified on a 1-kW DAB prototype, where the dc bias is suppressed to nearly null owing to the proposed sensor. [ABSTRACT FROM AUTHOR]

A concern with the isolation transformer in a dual active bridge (DAB) dc–dc converter is the dc bias in magnetization. This article proposes a fluxgate-based current sensor to measure the dc component mixed with a large, high-frequency ac current. Compared with a commercial Hall effect current sensor, the proposed sensor significantly reduces measurement error. This article presents the working principle and design considerations. A prototype is demonstrated for dc bias elimination control in a DAB converter. [ABSTRACT FROM AUTHOR]

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications. [ABSTRACT FROM AUTHOR]

The capability of dynamic grid support of a voltage source converter-high voltage direct current (VSC-HVdc) system depends on the maximum allowable current of the converter. This study attempts to increase the capability by overloading the power semiconductor device for a short period of time. Keeping the device temperature low is a major challenge due to the extra loss and small local thermal capacity. This study investigates a solution to increase the transient thermal capacity by making use of the latent heat of a phase change material (PCM). This article presents an integration scheme for a press pack power module, focusing on the fast recovery diode in an IGBT-diode package. Experiment and finite element analysis are used to evaluate the concept and analyze the factors affecting the design. It is shown that as heat is absorbed by the integrated PCM, the device temperature rise during a power surge is effectively tempered, providing a high short-term overcurrent rating of the device and an increased dynamic grid support capability of the VSC-HVdc system. [ABSTRACT FROM AUTHOR]

Power semiconductor chips are paralleled in modules to increase current rating. Under thermo-mechanical stresses in service, the die-attach solder layers will gradually develop into different levels of degradation. Early fault detection requires to monitor the occurrence of such an uneven degradation pattern. Internal temperature differences only slightly affect the current sharing between chips, and some temperature sensitive electric parameters are considerably weakened at module terminals. This article presents an external heat-flux-based condition monitoring method, implemented in a two-stage neural network. The first stage consists of a set of subnetworks to represent the mapping between the electrical operating point of the module and its external temperature distribution, for a range of solder degradation patterns and severities. The respective levels of matching are then extracted and applied to the second stage to diagnose the health condition of the power module. This condition monitoring method, validated by experiment, can sensitively detect individual solder degradation in multichip power modules or multimodule power electronic systems. [ABSTRACT FROM AUTHOR]

As grid codes evolve, inverter-interfaced renewable generation may be required to take greater responsibility for grid support. It may be obliged to source a large current during a short-circuit fault in the grid and provide large dynamic reactive power, beyond the inverter rating, for voltage recovery after the fault clearance. In this sense, the inverter-interfaced generating system would behave more similarly to a conventional synchronous machine. This is not yet mandatory but current technology cannot readily support it if required in the future, because the power semiconductors would overheat unless they are drastically derated. This study proposes a method to increase the power semiconductor's transient thermal capacity, and hence its short-term over-current capability, by integrating a phase-change material inside the power semiconductor module. Experiment and thermodynamic simulation across different materials are used to illustrate the feasibility of the concept and the factors that should be considered in such a design. The study shows that 1.5 p.u. (per unit) overcurrent could be achieved for 30 s, which is typical of synchronous generators; and 3.0 p.u. fault current could be achieved for 3 s. A custom-made 1200-V, 50-A IGBT half-bridge module integrating a liquid metal as the phase change material is compared with a conventional commercially available module. A validated simulation model is then used to further evaluate the proposal, regarding a 1700-V, 1000-A IGBT module for use in a wind turbine. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFET chips are often connected in parallel in a module to increase the current rating. However, the current capability is degraded due to unbalanced current and temperature distributions which affect the avalanche processes particularly in extreme operating conditions. To obtain the root cause of the degradation and identify the dominant factors, single-pulse avalanche testing is carried out in this study, and TCAD simulation is used for mechanism analysis. It is revealed that electrothermal parameters have different effects on current sharing in different stages of avalanching. The corresponding failure mechanisms are analyzed, and the main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. Device with smaller BV shares more current as well as more heat, which fails first eventually. To resolve such issues, proper device screening/paring should be carried out. The findings are helpful for a better understanding of avalanche capability degradation in parallel devices application. • To determine the influence of parameters inconsistency and identify the dominant factors in the parallel avalanche capability. • To obtain the root cause of the degradation, single-pulse avalanche testing and TCAD simulation are carried out. • The main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. • The research has guiding significance in power module designs and application of SiC MOSFET devices. [ABSTRACT FROM AUTHOR]

A 4H‐SiC trench metal–oxide–semiconductor field‐effect‐transistor (MOSFET) design with an integrated merged PiN Schottky (MPS) diode is proposed. The Schottky contact is embedded on the bottom of the trench structure for the first time. The low electric field in the oxide and Schottky contact surface can be achieved simultaneously using the proposed integration design which enhances the oxide reliability and reduces leakage from the Schottky diode. The integration of the MPS diode reduces the total chip area and the required number of dies compared with the conventional method of using an external Schottky diode. [ABSTRACT FROM AUTHOR]

Abstract: Background: Prevailing data suggest that ATP-sensitive potassium channels (KATP) contribute to a surprising resistance to hypoxia in mammalian embryos, thus we aimed to characterize the developmental changes of KATP channels in murine fetal ventricular cardiomyocytes. Methods: Patch clamp was applied to investigate the functions of KATP. RT-PCR, Western blot were used to further characterize the molecular properties of KATP channels. Results: Similar KATP current density was detected in ventricular cardiomyocytes of late development stage (LDS) and early development stage (EDS). Molecular–biological study revealed the upregulation of Kir6.1/SUR2A in membrane and Kir6.2 remained constant during development. Kir6.1, Kir6.2, and SUR1 were detectable in the mitochondria without marked difference between EDS and LDS. Acute hypoxia–ischemia led to cessation of APs in 62.5% of tested EDS cells and no APs cessation was observed in LDS cells. SarcKATP blocker glibenclamide rescued 47% of EDS cells but converted 42.8% of LDS cells to APs cessations under hypoxia-ischemic condition. MitoKATP blocker 5-HD did not significantly influence the response to acute hypoxia–ischemia at either EDS or LDS. In summary, sarcKATP played distinct functional roles under acute hypoxia-ischemic condition in EDS and LDS fetal ventricular cardiomyocytes, with developmental changes in sarcKATP subunits. MitoKATP were not significantly involved in the response of fetal cardiomyocytes to acute hypoxia–ischemia and no developmental changes of KATP subunits were found in mitochondria. [Copyright &y& Elsevier]

In order to obtain junction temperature of insulated-gate bipolar transistor (IGBT) on electric vehicle, a number of studies have proposed junction temperature (T j) estimation methods. However, some of these methods require additional circuits which lead to cost increase, some methods simulate the IGBT thermal process with thermal model, which induces a deviation between real functional results and simulation, and the other algorithm based methods may involve upgrading the main control unit (MCU) with increased costs. This paper proposes a method of IGBT T j estimation with regression analysis. The presented method firstly extracts the most sensitive factors from IGBT power loss model, and then the factors are applied in a data fitting function to characterize T j. After that, the mentioned fitting function is validated by regression analysis with statistics Anderson – Darling (AD) and P -value. Finally the T j estimation fitting function is demarcated by the negative thermal coefficient (NTC) measured temperature (T NTC). With the method using T NTC demarcation, the error bandwidth between estimated T j and measured T j is 3.4 °C in total. Compared with the T j estimation without T NTC demarcation, the error bandwidth of T j decreased from 6.9°C to 3.4 °C. The T j estimation method with T NTC demarcation is efficient for an online T j estimation of IGBT modules without increased costs. [ABSTRACT FROM AUTHOR]