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Resistive random-access memory (ReRAM) memristors are promising candidates for various compute in memory and flow-based computing approaches. As an alternative to traditional von Neumann computation, flow-based computing avoids serial movement of data between memory and processor. In this paper, we demonstrate arrays of 1 transistor 1 ReRAM (1T1R) to detect edges between 8 bit pixels using flow-based computing, and the effects of stochastic variation of ReRAM on edge detection outputs. Three different $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ resistance ratios (1.5:1, 2.5:1 or 28.6:1) were utilized to implement multiple flow-based edge detection computation matrices for 8 bit pixels. Edge detection was distinguishable for all $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ ratios used, for all flow-based computing matrices. However, the binary output resistance ratio of the matrices improved 3-fold when the patterned $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ ratio was increased to 28.6:1. A Gaussian simulation of ReRAM resistance variability validates the experimental data, with a correlation coefficient (r) of 0.9547. These results suggest a trade-off between the flow-based edge detection output ratio and the variability of the ReRAM resistance in $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ resistance ratio.

In this work, hafnium zirconium oxide (HZO)-based 100 × 100 nm2 ferroelectric tunnel junction (FTJ) devices were implemented on a 300 mm wafer platform, using a baseline 65 nm CMOS process technology. FTJs consisting of TiN/HZO/TiN were integrated in between metal 1 (M1) and via 1 (V1) layers. Cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy analysis confirmed the targeted thickness and composition of the FTJ film stack, while grazing incidence, in-plane x-ray diffraction analysis demonstrated the presence of orthorhombic phase Pca21 responsible for ferroelectric polarization observed in HZO films. Current measurement, as a function of voltage for both up- and down-polarization states, yielded a tunneling electroresistance (TER) ratio of 2.28. The device TER ratio and endurance behavior were further optimized by insertion of thin Al2O3 tunnel barrier layer between the bottom electrode (TiN) and ferroelectric switching layer (HZO) by tuning the band offset between HZO and TiN, facilitating on-state tunneling conduction and creating an additional barrier layer in off-state current conduction path. Investigation of current transport mechanism showed that the current in these FTJ devices is dominated by direct tunneling at low electric field ( E 0.4 MV/cm). The modified FTJ device stack (TiN/Al2O3/HZO/TiN) demonstrated an enhanced TER ratio of ∼5 (2.2× improvement) and endurance up to 106 switching cycles. Write voltage and pulse width dependent trade-off characteristics between TER ratio and maximum endurance cycles (Nc) were established that enabled optimal balance of FTJ switching metrics. The FTJ memory cells also showed multi-level-cell characteristics, i.e., 2 bits/cell storage capability. Based on full 300 mm wafer statistics, a switching yield of >80% was achieved for fabricated FTJ devices demonstrating robustness of fabrication and programming approach used for FTJ performance optimization. The realization of CMOS-compatible nanoscale FTJ devices on 300 mm wafer platform demonstrates the promising potential of high-volume large-scale industrial implementation of FTJ devices for various nonvolatile memory applications.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 102 times lower power consumption compared to GPU and 103 times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architectures offer an energy-efficient solution for DNN acceleration. However, the performance of RRAM-based IMC is limited by device nonidealities, ADC precision, and algorithm properties. To address this, in this work, first, we perform statistical characterization of RRAM device variation and temporal degradation from 300mm wafers of a fully integrated CMOS/RRAM 1T1R test chip at 65nm. Through this, we build a realistic foundation to assess the robustness. Second, we develop a cross-layer simulation tool that incorporates device, circuit, architecture, and algorithm properties under a single roof for system evaluation. Finally, we propose a novel loss landscape-based DNN model selection for stability, which effectively tolerates device variations and achieves a post-mapping accuracy higher than that with 50% lower RRAM variations. We demonstrate the proposed method for different DNNs on both CIFAR-10 and CIFAR-100 datasets.

Limitations related to the von Neumann bottleneck have resulted in novel circuits and architectures, including designs that utilize Resistive Random Access Memory (ReRAM) as nonvolatile memory (NVM) devices. ReRAM implemented with hafnium oxide (HfO 2 ) is a strong candidate for such applications. The non-volatility of these devices and their amenability to compute in memory functionality makes them ideal for neuromorphic applications, deep learning, and mathematical accelerator circuits (e.g. Vector Matrix Multiplication - VMM). However, these devices suffer from stochastic switching variability that currently limits their usage and performance. To realize the full potential of these devices, reliability analysis is required. In this work, a reliability study was performed using previously developed a 65 nm CMOS/Memristor process on a 300 mm wafer platform. To address the influence of switching compliance current on the variability of Low Resistance State (LRS) and High Resistance State (HRS), a total of 23 different compliance current values were implemented. The effects of temperature on device performance was also measured.

In this work, we have improved switching reliability of Hafnium Oxide (HfO 2 ) based CMOS integrated RRAM devices by tuning Atomic Layer Deposition (ALD) Co-reactant pulse time for HfO 2 switching layer deposition. Three different pulse times for H 2 O vapor pulses were chosen for this split: standard pulse time, 1.5X pulse time and 5X pulse time. Based on full wafer device testing results, the 5X pulse time RRAM devices showed higher mean forming voltages attributed to lower leakage current density. Additionally, 1T1R cells fabricated with 5X cycle time showed more than 2X improvement in memory window and significant reduction in HRS switching variability. We also report $\gt 95$% switching yield and a sigma of $\lt 0.5$ for cell-to-cell switching variability based on over 450 tested 1T1R devices across full 300 mm wafers, demonstrating the robustness of our process.

Resistive random-access memory (RRAM) is a promising technology for in-memory computing with high storage density, fast inference, and good compatibility with CMOS. However, the mapping of a pre-trained deep neural network (DNN) model on RRAM suffers from realistic device issues, especially the variation and quantization error, resulting in a significant reduction in inference accuracy. In this work, we first extract these statistical properties from 65 nm RRAM data on 300mm wafers. The RRAM data present 10-levels in quantization and 50% variance, resulting in an accuracy drop to 31.76% and 10.49% for MNIST and CIFAR-10 datasets, respectively. Based on the experimental data, we propose a combination of machine learning algorithms and on-line adaptation to recover the accuracy with the minimum overhead. The recipe first applies Knowledge Distillation (KD) to transfer an ideal model into a student model with statistical variations and 10 levels. Furthermore, an on-line sparse adaptation (OSA) method is applied to the DNN model mapped on to the RRAM array. Using importance sampling, OSA adds a small SRAM array that is sparsely connected to the main RRAM array; only this SRAM array is updated to recover the accuracy. As demonstrated on MNIST and CIFAR-10 datasets, a 7.86% area cost is sufficient to achieve baseline accuracy for the 65 nm RRAM devices.

Recent developments in nanophotonics have provided a clear roadmap for improving the efficiency of photonic devices through control over absorption and emission of devices. These advances could prove transformative for a wide variety of devices, such as photovoltaics, photoelectrochemical devices, photodetectors, and light-emitting diodes. However, it is often challenging to physically create the nanophotonic designs required to engineer the optical properties of devices. Here, we present a platform based on crystalline indium phosphide that enables thin-film nanophotonic structures with physical morphologies that are impossible to achieve through conventional state-of-the-art material growth techniques. Here, nanostructured InP thin films have been demonstrated on non-epitaxial alumina inverted nanocone (i-cone) substrates via a low-cost and scalable thin-film vapor-liquid-solid growth technique. In this process, indium films are first evaporated onto the i-cone structures in the desired morphology, followed by a high-temperature step that causes a phase transformation of the indium into indium phosphide, preserving the original morphology of the deposited indium. Through this approach, a wide variety of nanostructured film morphologies are accessible using only control over evaporation process variables. Critically, the as-grown nanotextured InP thin films demonstrate excellent optoelectronic properties, suggesting this platform is promising for future high-performance nanophotonic devices.

In this work, we have addressed cycle to cycle switching variability by modifying a key step in CMOS integrated RRAM devices fabrication, namely the atomic layer deposition (ALD) process used to deposit the HfO 2 switching layer. Two different HfO 2 ALD processes were utilized, one with an organic-based precursor, the other with a chlorine-based precursor. The trade-off between memory window (MW) and variability in the high resistance state (HRS) for RRAM cells was investigated with respect to compliance currents and reset voltages for multiple devices using both ALD precursors. The RRAM devices fabricated with the Cl-based precursor showed significant improvement in their MW/HRS resistance variability trade-off, compared to devices fabricated with the organic-based precursor over a range of compliance currents (150 μΑ to 450 μΑ) and reset voltages (−1.3V to −1.7V). Additionally, the MW shows stronger correlation with resistance variability as a function of reset voltage, mostly due to the significant change in average HRS values. To gain a statistically significant comparison, all 64 1 Transistor 1 RRAM (1T1R) cells in an 8×8 RRAM array were tested on a center die on wafers processed using both ALD precursors. Based on those 64 tested 1T1R cells, we demonstrated more than 80% switching yield for the Cl precursor HfO 2 based RRAM devices, as compared to 38% for the organic precursor devices. Additionally, 1T1R RRAM arrays fabricated using the Cl-based precursor showed more than 2× improvement in MW versus those fabricated using the organic-based precursor.

In neuromorphic applications, resistive memory solutions (implemented as Resistive Random Access Memory or ReRAM) have significant potential in emulating the desired two-terminal synaptic functionality of real synapses. One of the unique features for the demonstrated ReRAM devices includes conductance modulation, which allows for the implementation of the synaptic weight between neuronal elements. In this paper, we illustrate the multi-resistance level switching capabilities of our unique ReRAM-CMOS hybrid system, which is a demonstration vehicle for implementation of a memristive Dynamic Adaptive Neural Network Array, also known as mrDANNA. Discrete resistance levels have been achieved through application of varying gate voltage and discrete electric pulses in the order of nanoseconds.

We present a comparative study of quasi-metallic (Eg ∼ 100 meV) and semiconducting (Eg ∼ 1 eV) suspended carbon nanotube pn-junctions introduced by electrostatic gating. While the built-in fields of the quasi-metallic carbon nanotubes (CNTs) are 1-2 orders of magnitude smaller than those of the semiconducting CNTs, their photocurrent is 2 orders of magnitude higher than the corresponding semiconducting CNT devices under the same experimental conditions. Here, the large exciton binding energy in semiconducting nanotubes (∼400 meV) makes it difficult for excitons to dissociate into free carriers that can contribute to an externally measured photocurent. As such, semiconducting nanotubes require a phonon to assist in the exciton dissociation process, in order to produce a finite photocurrent, while quasi-metallic nanotubes do not. The quasi-metallic nanotubes have much lower exciton binding energies (∼50 meV) as well as a continuum of electronic states to decay into and, therefore, do not require the absorption of a phonon in order to dissociate, making it much easier for these excitons to produce a photocurrent. We performed detailed simulations of the band energies in quasi-metallic and semiconducting nanotube devices in order to obtain the electric field profiles along the lengths of the nanotubes. These simulations predict maximum built-in electric field strengths of 2.3 V/μm for semiconducting and 0.032-0.22 V/μm for quasi-metallic nanotubes under the applied gate voltages used in this study.

The III–V compound semiconductors exhibit superb electronic and optoelectronic properties. Traditionally, closely lattice-matched epitaxial substrates have been required for the growth of high-quality single-crystal III–V thin films and patterned microstructures. To remove this materials constraint, here we introduce a growth mode that enables direct writing of single-crystalline III–V's on amorphous substrates, thus further expanding their utility for various applications. The process utilizes templated liquid-phase crystal growth that results in user-tunable, patterned micro and nanostructures of single-crystalline III–V's of up to tens of micrometres in lateral dimensions. InP is chosen as a model material system owing to its technological importance. The patterned InP single crystals are configured as high-performance transistors and photodetectors directly on amorphous SiO2 growth substrates, with performance matching state-of-the-art epitaxially grown devices. The work presents an important advance towards universal integration of III–V's on application-specific substrates by direct growth., Growth of high-quality III–V semiconductors for electronics and optoelectronics usually requires an atomic-lattice matched substrate. Here, the authors use templated liquid-phase crystal growth to create single-crystalline III–V material up to ten micrometres across on an amorphous substrate.

The present work provides a new approach to evolve ligand structures which represent possible drug to be docked to the active site of the target protein. The structure is represented as a tree where each non-empty node represents a functional group. It is assumed that the active site configuration of the target protein is known with position of the essential residues. In this paper the interaction energy of the ligands with the protein target is minimized. Moreover, the size of the tree is difficult to obtain and it will be different for different active sites. To overcome the difficulty, a variable tree size configuration is used for designing ligands. The optimization is done using a quantum discrete PSO. The result using fixed length and variable length configuration are compared., 4 pages, 6 figures (Published in IEEE SCEECS 2012). arXiv admin note: substantial text overlap with arXiv:1205.6412

Design of non-uniform circular antenna arrays is one of the important optimization problems in electromagnetic domain. While designing a non-uniform circular array the goal of the designer is to achieve minimum side lobe levels with maximum directivity. In contrast to the single-objective methods that attempt to minimize a weighted sum of the four objectives considered here, in this article we consider these as four distinct objectives that are to be optimized simultaneously in a multi-objective (MO) framework using one of the best known Multi-Objective Evolutionary Algorithms (MOEAs) called NSGA-II. This MO approach provides greater flexibility in design by producing a set of final solutions with different trade-offs among the four objective from which the designer can choose one as per requirements. To the best of our knowledge, other than the single objective approaches, no MOEA has been applied to design a non-uniform circular array before. Simulations have been conducted to show that the best compromise solution obtained by NSGA-II is far better than the best results achieved by the single objective approaches by using the differential evolution (DE) algorithm and the Particle Swarm Optimization (PSO) algorithm.

This paper proposes a high speed low power circular convolution implementation of two finite length sequences by taking the advantage of fast Vedic Urdhva-Tiryakbhyam multiplication algorithm with a very efficient leakage control technique called Mutilple Channel CMOS (McCMOS) technique. The use of this Vedic formula allows for high speed convolution processing which happens frequently during the treatment of the time domain of signals. In this paper, the circular convolution is approached as a combination of Vedic multiplication unit and transmission gates based adders. The idea for designing the multiplication unit from Vedic Sutra is adopted because the partial sums and products are generated in only a single step. Furthermore McCMOS technique is used having non-minimum length transistors to offer the possibility of achieving excellent leakage control in nano-scale CMOS design with a very modest increase in area and switched capacitance. The simulations have been carried out in Cadence spice spectre using 130nm, 90nm, 65nm and 45nm node technology and presents comparative simulation results indicating the performance of the circuit. Thorough simulations show that the proposed architecture of designing the circular convolution achieves approximately 74–97% better performance in terms of PDP compared to the conventional architecture. The proposed technique will be very useful in different applications of time and space domains in digital image and signal processing.

This paper proposes an efficient design technique of high performance linear convolution of two finite length sequences using Multiple Channel CMOS technique. McCMOS technique uses non-minimum length transistors which offer the possibility of achieving excellent leakage control in nano-scale CMOS design with a very modest increase in area and switched capacitance. This paper approaches the linear convolution technique of two finite length sequences as the conventional multiplication procedure A TG array based novel architecture has been proposed for the implementation of the partial products of the multiplication of two input sequences which gives enormously better performance in terms of the power and speed compared to the conventional design. Thorough simulations of the proposed architecture of linear convolution show that the PDP is reduced approximately 77–97% than the conventional linear convolution design. The proposed technique will be very useful in different applications of time and space domains in digital image and signal processing where power and delay are the main area of concerns.

We describe here a new burst scheduling algorithm to avoid burst overlapping in the egress router of optical burst switching (OBS) network, and hence to improve the quality of service (QoS) in developing several optical networks to fulfill the increasing demand of Internet facilities. We consider TAG (tell-and-go) protocol where many lightpaths pass in a given link and burst overlap may occur. In an intermediate node having many incoming links and one outgoing link at lower traffic loads, we found the conditions for the burst controls, either passing of all bursts or blocking of some bursts in the egress nodes of optical domain. It is shown that in low traffic loads, burst blocking can be made zero but in higher traffic loads there is burst blocking, which can be reduced using different sets of fiber delay lines (FDLs) for which minimum usage of wavelengths can be achieved. The relation between number of burst blocking and the requirements of FDLs are shown. We used time-based assembly algorithm in an assembly node to build the burst at low and high traffic loads. The analysis for throughput depending on burst size, inter-arrival time, and sizes of fiber delay lines (FDLs), is made and improvement of throughput using FDLs is shown. Passing of bursts at the input channel and hence the priority of channels depending upon the burst size, intermediate gap between two successive bursts in the input channels, the arrival time for the first burst in the second & third input channels, and the FDL used in core nodes are shown.

We study photocurrent generation in individual, suspended carbon nanotube pn-junction diodes formed by electrostatic doping using two gate electrodes. Photocurrent spectra collected under various electrostatic doping concentrations reveal distinctive behaviors for free particle optical transitions and excitonic transitions. In particular, the photocurrent generated by excitonic transitions exhibits a strong gate doping dependence, while that of the free particle transitions is gate independent. Here, the built-in potential of the pn-junction is required to separate the strongly bound electron-hole pairs of the excitons, while free particle excitations do not require this field-assisted charge separation. We observe a sharp, well defined E11 free particle interband transition in contrast with previous photocurrent studies. Several steps are taken to ensure that the active charge separating region of these pn-junctions is suspended off the substrate in a suspended region that is substantially longer than th...