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As the computation cost increases to meet the design requirements for computation-intensive applications on today's systems, the pressure to develop high performance parallel processors on a chip will increase. Network-on-Chip (NoC) techniques that interconnect multiple processing elements with routers are the solution for reducing computation time and power consumption by parallel processing on a chip. The shared communication platform is also essential to meet the scalability and complexity challenges for System-on-Chip (SoC). However not many parallel applications have been studied for such an architecture and workload characterizations have not been researched to benefit the architecture design optimization. In this paper, we study multiple data-parallel applications on a multicore NoC architecture with distributed memory space. We introduce an efficient runtime workload distribution algorithm that balances workloads of parallel processors and apply for selected embedded applications. Using our cycle accurate multicore simulator, we simulated our NoC-enabled multicore architecture model and executed data-parallel applications on various number of processing elements using the proposed runtime load balancing algorithm and analyzed performance and communication overheads.

This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in network-on-chip (NoC) environment. Three different methods of parallel FFT are presented. One is the reference parallel FFT for comparison, and the other two with well-distributed computation as well as reduced communication overhead. By evenly distributing parallel computation tasks which uses data locality, the execution time for completing each stage of FFT can be reduced. Moreover, by optimizing data exchanges we minimize the communication overhead. Depending on the communication regularity, one can select appropriate parallel FFT algorithm. By using the simulation results of our cycle-accurate SystemC NoC model with a parameterizable 2-D mesh architecture, and the performance analysis in time as well as complexity, our proposed algorithms are shown to outperform other parallel FFT algorithm or high-speed DSP implementations.

The computational performance of network-on-chip (NoC) and multi-processor system-on-chip (MPSoC) for implementing cryptographic block ciphers can be improved by exploiting parallel and pipelined execution. In this paper, we present a parallel and pipeline processing method for block cipher algorithms using purely software implementation on an NoC. Algorithms are decomposed into task loops, functions and data flow for parallel and pipeline execution. Tasks are allocated by the proposed mapping strategy to each processing element (PE). In order to provide fault tolerance on nanoscale NoC circuits, we add Hamming error correction code (ECC) encoder and decoder at the network interface. The proposed parallel block cipher algorithm implementation on the fault tolerant NoC is simulated by using networked processor array (NePA), the cycle-accurate SystemC and hardware description language (HDL) model platform. Our parallel software implementation method on a multicore NoC architecture has the advantage of flexibility compared with traditional ASIC solutions. In addition, the simulation result presents that the parallel and pipeline processing approach for software block ciphers can be implemented on various NoC platforms which have different complexities and constraints.