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This research presents a simulated device structure for an Inductive Line Tunneling Tunnel Field-Effect Transistor (iTFET) with a high Schottky barrier and a control gate. We based our design process on real-world production components, factored in actual processing steps, and verified all software parameters to ensure the study's close alignment with practical manufacturing scenarios. Our configuration employs Silicon Germanium (SiGe), a narrow-bandgap semiconductor known for its cost-effectiveness, mature technology, and ability to enhance electron tunneling. We implemented Schottky Barrier Height (SBH) modulation engineering to increase the ON- state current (ION) by integrating an electrode into the semiconductor via Schottky contact. To further optimize the device performance, a control gate was included between the source and drain regions. This modification increased the ION and reduced the OFF-state current (IOFF) through the manipulation of the electric field. The simulation results demonstrated an average subthreshold swing (SSAVG) of 31.5 mV/dec, an ION of 4.96x10-6 A/μm, and an ION/IOFF ratio of 1.1x108 at a VDS of 0.2V, indicating a remarkably low subthreshold swing. These outcomes highlight the feasibility of utilizing a low thermal budget approach to fabricate high-performing TFETs that are well-suited for economical and low-energy applications.

Via the Sentaurus TCAD of 2D device simulation, the PN junction of Double-Gate Tunneling Field-Effect Transistor (PN-DGTFET) with the junctionless concept is investigated in this paper. The results demonstrate a PN-DGTFET of the source region completely overlapped with the gate region can effectively improve on-state current. This PN-DGTFET structure is major relies on the traditional band-to-band tunneling mechanism, and the minimum SS value can reach 8.83mV/decade, the average SS value can get 16.0mV/decade, the I ON /I OFF ratio can achieve $5.98 \times 10^{8}$ , and this device PN stack architecture can successfully reduce the manufacturing cost. Here, it can be found that reduction the drain region and parallel with the gate oxide layer, which can quickly create the depletion region and easily happen the tunneling switch-on state.

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness ( ${T}_{\textsf {Shell}}$ ) of 2 nm yields maximum retention. An SD ( ${N}_{\mathrm {d}}$ ) of $10^{18}$ cm $^{-\textsf {3}}$ attains RT of ~5.5 s and ~630 ms at 27 °C and 85 °C, respectively, whereas higher ${N}_{\textsf {d}}$ ( $10^{19}$ cm $^{-\textsf {3}}$ shows RT of ~13ms at 85 °C for ${L}_{\textsf {g}} = \textsf {200}$ nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of ~11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths.

This paper proposes symmetrical and crossed double-sided passivation emitter and surface field solar cells for bifacial applications which are fully compatible with the passivated emitter and rear contact (PERC) fabrication process. Our simulations use Silvaco TCAD Atlas, calibrated by real measurements. At an ideal albedo level where light enters both sides equally, these symmetrical and crossed structures boost energy by 88.78% and 106.74%, respectively. The reason for the crossed structure’s better performance is that it has a surrounding electric field. The crossed structure also obtains a 40.18 mA/cm2 short-circuit current ( ${J} _{\mathrm{ sc}}$ ), a 0.67 V open-circuit voltage ( ${V} _{\mathrm{ oc}}$ ), an 81.07% fill factor and a 21.93% conversion efficiency ( $\eta $ ). Compared with PERC+, the crossed structure improves low bifaciality factor ( $\varphi _{\eta }$ ) and increases $\eta $ by 6.44% and energy boost by 31.41% for bifacial. For more-realistic albedo levels, the structure also performs strongly. At the spectral albedo level of snow, the energy boost of the crossed structure is 102.06%, which is close to the performance at ideal albedo. At the spectral albedo level of white sand, the energy boost is 77.13%. At lower albedos, the energy boost remains between 20% and 30%.

This paper reports on the potential benefits of a vertically stacked ${n}$ - and ${p}$ -type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention time (RT) of capacitorless dynamic random access memory (1T-DRAM), with a significant improvement $(\sim \!\!\times 10^{3})$ compared with a conventional JL transistor with a doping ( ${N}_{\text{d}}$ ) of 1019 cm−3. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top ${n}$ -type JL transistor) and storage region (bottom ${p}$ -type JL), while maintaining an electrostatic coupling between them. The charge stored in the ${p}$ -type JL determines RT, and also impacts the read currents, and thus, influences the sense margin of DRAM. Stacked JL (SJL) 1T-DRAM achieves a maximum RT of ~2.5 s for ${N}_{\text{d}} = 5 \times 10^{18}$ cm−3 and ~1 s for 1019 cm−3 with a gate length ( ${L}_{\text{g}}$ ) of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The enhanced DRAM metrics (better scalability and high RT) are attributed to optimal architecture due to the vertical stacking of ${n}$ - and ${p}$ -type regions.

To investigate the effect of surface texturing for high-efficiency heterojunction with intrinsic thin layer (HIT) solar cells, we have systematically designed different textures and numerically evaluated their ability to trap light. These evaluations were first calibrated by physically fabricating a general pyramid-structured HIT solar cell. The performance of various textures is compared, such as a flat structure, a pillar structure, and different types of pyramid and inverse pyramid structures. Simulation results identify the pillar structure as the best, because the light is reflected several times onto the surface, so that more of the light is trapped by the substrate. The pillar structure HIT solar cell's conversion efficiency of 25.73% is an improvement over the 24.7% of the conventional random pyramid HIT solar cell.

In this paper, we propose symmetrical and crossed bifacial crystalline silicon solar cells with heterojunctions employing a double-sided emitter, for use in environments with ambient light. We perform real measurement-based simulation analysis by using Silvaco TCAD Atlas. At an albedo level of 30%, our symmetrically structured solar cell achieves a $\text{47.42}\,{\text{ mA/cm}}^{\text{2}}$ short-circuit current ( J sc) and a 29.72% conversion efficiency ( η ), due to the double-sided emitter's large area. These J sc and η values are, respectively, 14.2% and 16.1% better than for a conventional Interdigitated Back Contact (IBC) [1] . The crossed structure obtains an 84.34% fill factor (FF) and a 29.81% conversion efficiency, due to its surrounding electric field. Conversion efficiency is increased by 16.4% compared with a conventional IBC solar cell [1] . Also, conversion efficiencies for the symmetrical and crossed bifacial SHJs are increased by 11.60% and 11.94%, respectively, compared with the state-of-the-art IBC solar cells [2] .

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches $1.44 \times 10^{-6}$ A/ $\mu \text{m}$ of on current and $3.22 \times 10^{9}$ ON/ OFF current ratio. A minimum subthreshold swing SS $_{{\textsf {min}}} = 28.3$ mV/dec and an average swing SS $_{{\textsf {avg}}} = 59.8$ mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters show good noise margins of $\textsf {NM}_{H} = 65$ mV (38.5 % $V_{{\textsf {DD}}}$ ) and NM $_{L} = 77$ mV (32.5 % $V_{{\textsf {DD}}}$ ) and also a high voltage gain even at $V_{{\textsf {DD}}} = 0.2$ V.

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gate-control depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of $33.6~\mu \text{A}/\mu \text{m}$ when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application.

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( ${L}_ {\text {gap}})$ between the gates, and an underlap region ( ${L}_{\text {un}})$ between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of ${L}_{\text {gap}}$ at 85 °C, which can be further improved to ~600 ms with the introduction of ${L}_{\text {un}}$ . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation.

This paper analyzes different transistor architectures (inversion mode (IM), accumulation mode (AM) and junctionless (JL)) for standalone as well as embedded DRAM. The performance metrics (retention time (RT), sense margin (SM), current ratio (CR) and write time (WT)) of JL based 1T-DRAM can be improved through stacked JL (SJL) and core-shell (CS) topologies, which separate conduction and storage regions. Results including gate length scalability (25 nm) and high temperature (125 °C) operation indicate the preference for SJL for standalone applications while CS architecture for embedded DRAM.

We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are primarily stored in drain-side and source-side p-type pseudo-neutral regions under the oxide spacer. These regions are isolated by the gate/drain or gate/source depletion regions during programming and read “1” operations which facilitates the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, thereby the programming window remains viable at high temperatures, while also maintaining 26% of the retention performance at 358 K. The benefits of the planar cell enable the realization of a scalable vertical channel structure.

The electrical conduction mechanisms of Ni–Cr thin film resistor are demonstrated by different film thickness through scattering models fitting. The resistivity and temperature coefficient of the resistance of Ni–Cr thin film are measured to investigate the influence of thickness with different annealing temperature. Finally, an oxidation and atom inter-diffusion model was proposed to explain the effects of film thickness on the electrical properties of Ni–Cr thin film resistor under different annealing temperature.

We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time ( RT ) of $\sim 1.5$ s at 85 °C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125 °C).

A device design technique for boosting nanowire MOSFET performance beyond a 10-nm technology node is proposed using physical modeling and 3-D numerical simulation. The revisited subthreshold kink effect improves the transistor ON–OFF current ratio and is achievable with supply bias lower than 1 V. The proposed technique overcomes the fundamental and thermal voltage-limited subthreshold swing (SS). An optimized device design methodology to exploit the lowered SS is provided as well.

In this work, we have investigated Double Gate junctionless transistor based capacitorless Dynamic Random Access Memory (1T-DRAM). The back gate is responsible for formation of an electrostatic potential well, while the front gate distinguishes the two states based on the charge stored at the back. The read operation is performed through drift-diffusion mechanism. The independent gate operation results in a retention time of 170 ms for gate length of 400 nm at 85 °C.

To achieve high efficiency in bifacial application, recessed back-surface-field (BSF) are designed on the crystalline silicon (c-Si) wafer with high quality hydrogenated amorphous silicon layer to improve the short-circuit current (J sc ) and reduce the carrier recombination. We perform simulation analysis by utilizing Silvaco TCAD Altas. At an albedo intensity of 30%, our recessed BSF (RBSF) silicon heterojunction (SJT) solar cell reaches a 47.07 mA/cm2 short-circuit current (J sc ) and 30.16 % of conversion efficiency (η) which is 9.24 % and 9.2 % more than the J sc and η of flat SJT solar cell thank to the additional recessed BSF area. When the albedo intensity reaches 100 %, the increase percentages of J sc and η arrive 12.66 % and 13.1 %, respectively.

We propose a Gated-PN iTFET that places the gate over the source to increase the line-tunneling area and ON current. The device avoids the ambipolar effect, reduces trap-assisted tunneling, and improves subthreshold swing (SS). Across a very wide range of I d values, the SS exceeds SS min = 10.5 mV/dec, and averages SS avg = 31.8 mV/dec. At V d = 0.1 V, the device achieves a 1.46 × 10−7 A/μm ON current and a 3.57 × 107 ON/OFF current ratio. When trap-assisted tunneling is considered, the device still averages a SS of 51.8 mV/dec and an I on /I off ratio of 1.35 × 105.

In this paper, we proposed an new Double-Gate (DG) PN-type tunneling field-effect transistor with exploiting induced channel layer (iTFETs) for line tunneling and low power applications (V D = 0.1V & 0.05V). Unlike conventional TFET, with same type of doping in source and underneath the gate change the topology from PIN to PN TFET. We replace point tunneling with line tunneling, which can improves currents, average and minimum subthreshold swing. By using PN structure, the ambipolar effect can be effectively suppressed. Furthermore, the proposed topology improves the double and vertical gate results. These devices achieve 4.1 × 10−7 A/μm of ON current (I ON (I d @ V G = V D ), 2.1 × 10−17 A/μm of OFF current (I OFF (I d @ V G = 0 V), and 1.95 × 1010 of ON/OFF current ratio (I ON /I OFF ). A minimum subthreshold swing SS avg = 12.2 mV/dec and the SS min = 5 mV/dec are obtained.

An assessment of Tunnel FET (TFET) architectures for capacitorless dynamic memory applications is presented through composite metrics to balance various trade-offs while regulating hole distribution to determine sense margin, retention time and current ratio. The impact of temperature, bias and scalability on device performance is also investigated. Results highlight the potential of TFET to overcome various trade-offs through optimal architecture, and achieve enhanced composite metrics at sub-100 nm gate lengths. (0)

In this work, vertically stackedn-oxide-p transistor architecture is explored as 1T-DRAM. The moderately dopedp type region is utilized to modulate (i) state currents flowing through the top n-type conduction region, and (ii) Retention Time (RT) through charges stored at the back surface of p-type storage region. The creation of deeper potential well for charge storage inp-region is based on electrostatic doping effect (underneath Source/Drain regions and high gate workfunction values). ART of $\sim$1 s and $\sim$1 ms at gate lengths of 200 nm and 25 nm, respectively, at 85°C can be achieved. A low-$\kappa$ (SiO 2 ) material for the separation of conduction and storage regions enables a higher RT due to lower electric field in the storage region.

This paper presents new solar cell architecture, the double-sided copper indium gallium selenide (DS-CIGS) solar cell. The device introduces a third terminal between the two CIGS sides, comprised of a layer of conductive indium tin oxide (ITO). Being transparent, the ITO layer allows light to pass through and be absorbed by the CIGS cell on the other side. Designed for bifacial applications, simulation results indicate a 68.3% increase in conversion efficiency for equal front and back illumination, versus a comparable conventional bifacial CIGS architecture (η=29.68 % versus η=17.64 %).

This paper proposes symmetrical and crossed double- sided passivation emitter and surface field solar cells for bifacial applications which are fully compatible with the PERC fabrication process. Our simulations use Silvaco TCAD Atlas, calibrated by real measurements. At 100% albedo level, these symmetrical and crossed structures boost energy by 88.78 % and 106.74 %, respectively. The reason for the crossed structure’s better performance is that it has a surrounding electric field. The crossed structure also obtains a 40.18 mA/cm2 short-circuit current (J sc ), a 0.67 V open-circuit voltage (V oc ), an 81.07 % fill factor (F.F.) and a 21.93 % conversion efficiency (ƞ). Compared with PERC+, the crossed structure improves low bifaciality factor (φ ƞ ) and increases ƞ by 6.44% and energy boost by 31.41% for bifacial