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The first part of this dissertation focuses on the millimeter-wave power amplifier in silicon where both switching and linear power amplifiers were investigated. In Chapter 2, a Q-band, Class-E power amplifier has been designed and fabricated in a 120 nm SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 mm². A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz. Chapter 3, presents a W-band, tapered constructive wave power amplifier (TCWPA) that has been designed and fabricated in a 120 nm SiGe BiCMOS technology. The amplifier has a 3 dB BW of 19 GHz from 91-110 GHz and a maximum gain of 12.5 dB at 101 GHz. At 98 GHz, OP1dB is 4.9 dBm. At 97 GHz, saturated output power is 5.9 dBm and the PAE is 7.2%. The amplifier operates from a 2.4 V supply and occupies an area of 0.22 mm2. A novel circuit topology for power amplifier was introduced in Chapter 4 where only one network is used to provide both input and output matching. This new topology incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The power amplifier is fabricated in a 120 nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power added efficiency of 20% at 38 GHz. The second part of this dissertation focuses on the performance analysis of phase- interpolated dual loop clock and data recovery. It presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase- interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase -dependent jitter contributions to the recovered clock. The multilane receiver was designed in 130 nm CMOS technology. The die occupies an area of 1930 [mu]m by 1250 [mu]m and consumes 67.9 mW per channel. It achieves a maximum data rate of 7 Gbps per channel for 0 and ±200 ppm clock frequency deviation. Quadrature clocks are used in locking mechanism of phase-interpolated CDRs. Due to circuit non-idealities, any mismatch in the quadraure phase causes jitter increase and ultimately increase of bit error rate. The material is presented in Chapter 5