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Activation of CD40-mediated signaling in antigen-presenting cells is a promising therapeutic strategy to promote immune responses against tumors. Agonistic anti-CD40 antibodies currently in development require Fcγ-receptor-mediated crosslinking of CD40 molecules for meaningful activation of CD40 signaling but have limitations due to dose-limiting toxicities. Here we describe the identification of CD40 antibodies which strongly stimulate antigen-presenting cells in an entirely Fc-independent manner. These novel Fc-silenced anti-CD40 antibodies induce upregulation of costimulatory receptors CD80 and CD86 and cytokine release by dendritic cells with an efficacy exceeding that of existing antibodies. Binding to the CD40L interaction region on CD40 appears to be a prerequisite to achieving such strong activities. Finally, the most active identified anti-CD40 antibody shows evidence of activity in terms of the expected markers of canonical CD40 signaling when injected in humanized mice. There are no signs of obvious toxicities whereas the clinical-stage anti-CD40 antibody CP-870,893 induced severe signs of toxicity in these animals despite a lower dose compared with the novel Fc-silenced canonical agonist. These studies thus demonstrate potent activation of antigen-presenting cells with anti-CD40 antibodies lacking Fcγ-receptor-binding activity and open the possibility of an efficacious and safe combination therapy for cancer patients.One Sentence SummaryTreatment of antigen-presenting cells and humanized mice with novel Fc-silenced CD40 antibodies demonstrates an Fcγ-receptor-independent canonical agonistic mode of action for therapeutic use.

Resistive random-access memory (ReRAM) memristors are promising candidates for various compute in memory and flow-based computing approaches. As an alternative to traditional von Neumann computation, flow-based computing avoids serial movement of data between memory and processor. In this paper, we demonstrate arrays of 1 transistor 1 ReRAM (1T1R) to detect edges between 8 bit pixels using flow-based computing, and the effects of stochastic variation of ReRAM on edge detection outputs. Three different $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ resistance ratios (1.5:1, 2.5:1 or 28.6:1) were utilized to implement multiple flow-based edge detection computation matrices for 8 bit pixels. Edge detection was distinguishable for all $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ ratios used, for all flow-based computing matrices. However, the binary output resistance ratio of the matrices improved 3-fold when the patterned $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ ratio was increased to 28.6:1. A Gaussian simulation of ReRAM resistance variability validates the experimental data, with a correlation coefficient (r) of 0.9547. These results suggest a trade-off between the flow-based edge detection output ratio and the variability of the ReRAM resistance in $\text{R}_{\mathrm {off}}/\text{R}_{\mathrm {on}}$ resistance ratio.

Despite drawing inspiration from biological systems which are inherently noisy and variable, artificial neural networks have been shown to require precise weights to carry out the task which they are trained to accomplish. This creates a challenge when adapting these artificial networks to specialized execution platforms which may encode weights in a manner which restricts their accuracy and/or precision. Reflecting back on the non-idealities which are observed in biological systems, we investigated the effect these properties have on the robustness of spiking neural networks under perturbations to weights. First, we examined techniques extant in conventional neural networks which resemble noisy processes, and postulated they may produce similar beneficial effects in spiking neural networks. Second, we evolved a set of spiking neural networks utilizing biological non-idealities to solve a pole-balancing task, and estimated their robustness. We showed it is higher in networks using noisy neurons, and demonstrated that one of these networks can perform well under the variance expected when a hafnium-oxide based resistive memory is used to encode synaptic weights. Lastly, we trained a series of networks using a surrogate gradient method on the MNIST classification task. We confirmed that these networks demonstrate similar trends in robustness to the evolved networks. We discuss these results and argue that they display empirical evidence supporting the role of noise as a regularizer which can increase network robustness.

Resistive Random Access Memory (ReRAM), a form of non-volatile memory, has been proposed as a Flash memory replacement. In addition, novel circuit architectures have been proposed that rely on newly discovered or predicted behavior of ReRAM. One such architecture is the memristive Dynamic Adaptive Neural Network Array, developed to emulate the functionality of a biological neuron system. We demonstrated ReRAM devices that show a synaptic tendency by changing their resistance in an analog fashion. The CMOS compatible nanoscale ReRAM devices shown are based on an HfO 2 switching layer that sits on a tungsten electrode and is covered by a titanium oxygen scavenger layer and a titanium nitride top electrode. In this work, we showed devices exceeding endurance values of 10B cycles with a discrete R off /R on ratio of 15. Multi-level states were achieved by using consecutive ultra-short 5/1.5 ns pulses during the reset operation. A neural network simulation was performed in which the synaptic weights were perturbed with the ReRAM variability, which was extracted from two different characterization methods: (1) via direct write, and (2) via a write/read verification approach during the reset operation. A substantial improvement of the neural network fitness was demonstrated when using the write/read verification approach.

In this work, hafnium zirconium oxide (HZO)-based 100 × 100 nm2 ferroelectric tunnel junction (FTJ) devices were implemented on a 300 mm wafer platform, using a baseline 65 nm CMOS process technology. FTJs consisting of TiN/HZO/TiN were integrated in between metal 1 (M1) and via 1 (V1) layers. Cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy analysis confirmed the targeted thickness and composition of the FTJ film stack, while grazing incidence, in-plane x-ray diffraction analysis demonstrated the presence of orthorhombic phase Pca21 responsible for ferroelectric polarization observed in HZO films. Current measurement, as a function of voltage for both up- and down-polarization states, yielded a tunneling electroresistance (TER) ratio of 2.28. The device TER ratio and endurance behavior were further optimized by insertion of thin Al2O3 tunnel barrier layer between the bottom electrode (TiN) and ferroelectric switching layer (HZO) by tuning the band offset between HZO and TiN, facilitating on-state tunneling conduction and creating an additional barrier layer in off-state current conduction path. Investigation of current transport mechanism showed that the current in these FTJ devices is dominated by direct tunneling at low electric field ( E 0.4 MV/cm). The modified FTJ device stack (TiN/Al2O3/HZO/TiN) demonstrated an enhanced TER ratio of ∼5 (2.2× improvement) and endurance up to 106 switching cycles. Write voltage and pulse width dependent trade-off characteristics between TER ratio and maximum endurance cycles (Nc) were established that enabled optimal balance of FTJ switching metrics. The FTJ memory cells also showed multi-level-cell characteristics, i.e., 2 bits/cell storage capability. Based on full 300 mm wafer statistics, a switching yield of >80% was achieved for fabricated FTJ devices demonstrating robustness of fabrication and programming approach used for FTJ performance optimization. The realization of CMOS-compatible nanoscale FTJ devices on 300 mm wafer platform demonstrates the promising potential of high-volume large-scale industrial implementation of FTJ devices for various nonvolatile memory applications.

The stabilization of the threshold switching characteristics of memristive [Formula: see text] is examined as a function of sample growth and device characteristics. Sub-stoichiometric [Formula: see text] was deposited via magnetron sputtering and patterned in nanoscale ([Formula: see text]–[Formula: see text]) W/Ir/[Formula: see text]/TiN devices and microscale ([Formula: see text]–[Formula: see text]) crossbar Au/Ru/[Formula: see text]/Pt devices. Annealing the nanoscale devices at 700 [Formula: see text]C removed the need for electroforming the devices. The smallest nanoscale devices showed a large asymmetry in the IV curves for positive and negative bias that switched to symmetric behavior for the larger and microscale devices. Electroforming the microscale crossbar devices created conducting [Formula: see text] filaments with symmetric IV curves whose behavior did not change as the device area increased. The smallest devices showed the largest threshold voltages and most stable threshold switching. As the nanoscale device area increased, the resistance of the devices scaled with the area as [Formula: see text], indicating a crystallized bulk [Formula: see text] device. When the nanoscale device size was comparable to the size of the filaments, the annealed nanoscale devices showed similar electrical responses as the electroformed microscale crossbar devices, indicating filament-like behavior in even annealed devices without electroforming. Finally, the addition of up to 1.8% Ti dopant into the films did not improve or stabilize the threshold switching in the microscale crossbar devices.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 102 times lower power consumption compared to GPU and 103 times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

The radiation response of TaO x -based resistive memory (RRAM) devices fabricated in academic (Set A) and industrial (Set B) settings was compared. Ionization damage from a 60Co gamma source did not cause any changes in device resistance for either device type, up to 45 Mrad(Si). Displacement damage from a heavy ion beam caused a decrease in resistance at $1 \times 10 ^{21}$ oxygen displacements per cm3 in Set B devices in the high-resistance state (HRS); meanwhile, Set A devices did not exhibit any decrease in resistance due to displacement damage. Both types of devices exhibited an increase in resistance around $3 \times 10 ^{22}$ oxygen displacements per cm3, possibly due to the damage at the oxide/metal interfaces. These extremely high levels of damage represent near-total atomic disruption, and if this level of damage was ever reached, other circuit elements would likely fail before the RRAM devices in this article. Overall, both sets of devices were much more resistant to radiation effects than the similar devices reported in the literature. Displacement damage effects were only observed in the Set A devices once the displacement-induced oxygen vacancies surpassed the intrinsic vacancy concentration in the devices, suggesting that high oxygen vacancy concentration played a role in the devices’ high tolerance to displacement damage.

The recent discovery of ferroelectric behavior in doped hafnia-based dielectrics, attributed to a non-centrosymmetric orthorhombic phase, has potential for use in attractive applications such as negative differential capacitance field-effect-transistors (NCFET) and ferroelectric random access memory devices (FeRAM). Alloying with similar oxides like ZrO2, doping with specific elements such as Si, novel processing methods, encapsulation and annealing schemes are also some of the techniques that are being explored to target structural modifications and stabilization of the non-centrosymmetric phase. In this study, we utilized synchrotron-based x-ray diffraction in the grazing incidence in plane geometry (GIIXRD) to determine the crystalline phases in hafnia-zirconia (HZO) compositional alloys deposited by atomic layer deposition (ALD). Here we compare and contrast the structural phases and ferroelectric properties of mechanically confined HZO films in metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) structures. Both MIM and MIS structures reveals a host of reflections due to non-monoclinic phases in the d-spacing region between 1.75A to 4A. The non-monoclinic phases are believed to consist of tetragonal and orthorhombic phases. Compared to the MIS structures a suppression of the monoclinic phase in MIM structures with 50% zirconia or less was observed. The correlation of the electrical properties with the structural analysis obtained by GIIXRD highlights the importance of understanding the effects of the underlying substrate (metal vs. Si) for different target applications.

Material properties of Ga–Sb binary alloy thin films deposited under ultra-high vacuum conditions were studied for analog phase change memory (PCM) applications. Crystallization of this alloy was shown to occur in the temperature range of 180–264 °C, with activation energy >2.5 eV depending on the composition. X-ray diffraction (XRD) studies showed phase separation upon crystallization into two phases, Ga-doped A7 antimony and cubic zinc-blende GaSb. Synchrotron in situ XRD analysis revealed that crystallization into the A7 phase is accompanied by Ga out-diffusion from the grains. X-ray absorption fine structure studies of the local structure of these alloys demonstrated a bond length decrease with a stable coordination number of 4 upon amorphous-to-crystalline phase transformation. Mushroom cell structures built with Ga–Sb alloys on ø110 nm TiN heater show a phase change material resistance switching behavior with resistance ratio >100 under electrical pulse measurements. TEM and Energy Dispersive Spectroscopy (EDS) studies of the Ga–Sb cells after ∼100 switching cycles revealed that partial SET or intermediate resistance states are attained by the variation of the grain size of the material as well as the Ga content in the A7 phase. A mechanism for a reversible composition control is proposed for analog cell performance. These results indicate that Te-free Ga–Sb binary alloys are potential candidates for analog PCM applications.

Among various phase-change memory materials (PCMs), Ge 2 Sb 2 Te 5 (GST) is an outstanding representative, widely used in both optical storage and electronic memories [1] . The intrinsic drawbacks of this GST, however, such as tellurium volatility and low amorphous phase stability (resistance retention), hinder it from being a perfect candidate. Tellurium-free antimony-based PCMs have been the subject of considerable recent interest, due to their excellent resistance contrast, rapid crystallization, and high amorphous phase stability [2] . Moreover, with increasing demand for high-capacity memory in consumer electronics, the multibit high-density storage capability of various memory devices has become very attractive [3] – [5] . Here, a bilayer Ga-Sb stack structure is demonstrated, showing multilevel switching properties. The origin of multilevel states and their stability are also studied.

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architectures offer an energy-efficient solution for DNN acceleration. However, the performance of RRAM-based IMC is limited by device nonidealities, ADC precision, and algorithm properties. To address this, in this work, first, we perform statistical characterization of RRAM device variation and temporal degradation from 300mm wafers of a fully integrated CMOS/RRAM 1T1R test chip at 65nm. Through this, we build a realistic foundation to assess the robustness. Second, we develop a cross-layer simulation tool that incorporates device, circuit, architecture, and algorithm properties under a single roof for system evaluation. Finally, we propose a novel loss landscape-based DNN model selection for stability, which effectively tolerates device variations and achieves a post-mapping accuracy higher than that with 50% lower RRAM variations. We demonstrate the proposed method for different DNNs on both CIFAR-10 and CIFAR-100 datasets.

Limitations related to the von Neumann bottleneck have resulted in novel circuits and architectures, including designs that utilize Resistive Random Access Memory (ReRAM) as nonvolatile memory (NVM) devices. ReRAM implemented with hafnium oxide (HfO 2 ) is a strong candidate for such applications. The non-volatility of these devices and their amenability to compute in memory functionality makes them ideal for neuromorphic applications, deep learning, and mathematical accelerator circuits (e.g. Vector Matrix Multiplication - VMM). However, these devices suffer from stochastic switching variability that currently limits their usage and performance. To realize the full potential of these devices, reliability analysis is required. In this work, a reliability study was performed using previously developed a 65 nm CMOS/Memristor process on a 300 mm wafer platform. To address the influence of switching compliance current on the variability of Low Resistance State (LRS) and High Resistance State (HRS), a total of 23 different compliance current values were implemented. The effects of temperature on device performance was also measured.

In this work, we have improved switching reliability of Hafnium Oxide (HfO 2 ) based CMOS integrated RRAM devices by tuning Atomic Layer Deposition (ALD) Co-reactant pulse time for HfO 2 switching layer deposition. Three different pulse times for H 2 O vapor pulses were chosen for this split: standard pulse time, 1.5X pulse time and 5X pulse time. Based on full wafer device testing results, the 5X pulse time RRAM devices showed higher mean forming voltages attributed to lower leakage current density. Additionally, 1T1R cells fabricated with 5X cycle time showed more than 2X improvement in memory window and significant reduction in HRS switching variability. We also report $\gt 95$% switching yield and a sigma of $\lt 0.5$ for cell-to-cell switching variability based on over 450 tested 1T1R devices across full 300 mm wafers, demonstrating the robustness of our process.

As CMOS scaling approaches its limitation, the power consumption of computations performed using the von Neumann architecture have become an issue. As a promising alternative solution, Resistive Random Access Memory (ReRAM) overcomes this bottleneck by enabling computationin-memory. In this work, arrays of HfO 2 -based bipolar ReRAM are simulated to carry out one such computation, called temporal correlation detection in binary processes. The correlation detection algorithm is presented, and the ReRAM model of fabricated devices was used in a Python-based simulation. The correlated and uncorrelated processes were assigned to ReRAM devices in a 5x5 array, where the ReRAM with correlated process was driven to a high conductance over time. The results show that the correlated processes are successfully detected over time.

Resistive random-access memory (RRAM) is a promising technology for in-memory computing with high storage density, fast inference, and good compatibility with CMOS. However, the mapping of a pre-trained deep neural network (DNN) model on RRAM suffers from realistic device issues, especially the variation and quantization error, resulting in a significant reduction in inference accuracy. In this work, we first extract these statistical properties from 65 nm RRAM data on 300mm wafers. The RRAM data present 10-levels in quantization and 50% variance, resulting in an accuracy drop to 31.76% and 10.49% for MNIST and CIFAR-10 datasets, respectively. Based on the experimental data, we propose a combination of machine learning algorithms and on-line adaptation to recover the accuracy with the minimum overhead. The recipe first applies Knowledge Distillation (KD) to transfer an ideal model into a student model with statistical variations and 10 levels. Furthermore, an on-line sparse adaptation (OSA) method is applied to the DNN model mapped on to the RRAM array. Using importance sampling, OSA adds a small SRAM array that is sparsely connected to the main RRAM array; only this SRAM array is updated to recover the accuracy. As demonstrated on MNIST and CIFAR-10 datasets, a 7.86% area cost is sufficient to achieve baseline accuracy for the 65 nm RRAM devices.

Material properties of Al-Sb binary alloy thin films deposited under ultra-high vacuum conditions were studied for multi-level phase change memory applications. Crystallization of this alloy was shown to occur in the temperature range of 180 °C–280 °C, with activation energy >2 eV. X-ray diffraction (XRD) from annealed alloy films indicates the formation of two crystalline phases, (i) an Al-doped A7 antimony phase, and (ii) a stable cubic AlSb phase. In-situ XRD analysis of these films show the AlSb phase crystalizes at a much higher temperature as compared to the A7 phase after annealing of the film to 650 °C. Mushroom cell structures formed with Al-Sb alloys on 120 nm TiN heater show a phase change material resistance switching behavior with reset/set resistance ratio >1000 under pulse measurements. TEM and in situ synchrotron XRD studies indicate fine nucleation grain sizes of ∼8–10 nm, and low elemental redistribution that is useful for improving reliability of the devices. These results indicate that Te-free Al-Sb binary alloys are possible candidates for analog PCM applications.

Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating such issues by providing hardware-specific fingerprints based on intrinsic process variations within individual IC implementations. As technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies, such as memristors or RRAMs (resistive random-access memory), have become interesting options for emerging computing systems. In this article, using a comprehensive temperature dependent model of an HfO x (hafnium-oxide) memristor, based on experimental measurements, we explore the best region of operation for a memristive crossbar PUF (XbarPUF). The design considered also employs XORing and a column shuffling technique to improve reliability and resilience to machine learning attacks. We present a detailed analysis for the noise margin and discuss the scalability of the XbarPUF structure. Finally, we present results for estimates of area, power, and delay alongside security performance metrics to analyze the strengths and weaknesses of the XbarPUF. Our XbarPUF exhibits nearly ideal (near 50%) uniqueness, bit-aliasing and uniformity, good reliability of 90% and up (with 100% being ideal), a very small footprint, and low average power consumption ≈104μW.