Search

The potential of source/drain extension (SDE) region engineering in FinFETs for ultra-low voltage (ULV) analog applications is evaluated. Findings reveal the usefulness of the SDE region design in improving intrinsic dc gain and cutoff frequency.

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1=SM×RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2=SM×CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM. [ABSTRACT FROM AUTHOR]

This paper proposes an accurate model to investigate the small-signal microwave parameters of fully strained (FS) and partially relaxed (PR) [Al.sub.m][Ga.sub.1-m]N/GaN high electron-mobility transistors (HEMTs). It is observed that elastic strain relaxation of the [Al.sub.m][Ga.sub.1-m]N layer imposes an upper limit on the maximum two-dimensional electron-gas sheet charge density and is, thus, extremely critical in determining the microwave performance of high Al-content [Al.sub.m][Ga.sub.1-m]N/GaN HEMTs. The model incorporates the effects of strain relaxation of the barrier layer, field-dependent mobility, parasitic source/drain resistance, and velocity saturation to evaluate drain current, transconductance, drain conductance, cutoff frequency, and transit time of FS and PR [Al.sub.m][Ga.sub.1-m]N/GaN HEMTs with different A1 mole fractions. The proposed model predicts a high drain current of 5.94 A/mm for a PR 0.3-/[micro]m [Al.sub.0.4][Ga.sub.0.6]N/GaN N/GaN HEMT, which is in close proximity with previously published simulated results. A peak transconductance of 154 mS/mm is also estimated for a 1-/[micro]m gate-length device with aluminum concentration of 15% (FS), which is in close agreement with previously published measured data. A high cutoff frequency of 21.09 GHz was predicted for a 0.6-/[micro]m device with an A1 mole fraction of 0.5 (PR), thus showing the potential of AlGaN/GaN HEMTs for microwave applications. Index Terms--[Al.sub.m][Ga.sub.1-m]N/GaN HEMTs, current-voltage characteristics, cutoff frequency, drain conductance, strain relaxation, threshold voltage, transconductance, transit time.

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ~2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory. [ABSTRACT FROM AUTHOR]