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International audience; The steady expansion of the number of wireless devices and the ubiquity of the networks give rise to various interesting challenges for the future sixth generation (6G) of wireless communication systems. Particularly, the operators have to handle massive connectivity among Machine Type Devices (MTDs) and increasing demand for eMMB through limited spectrum resources. Non-Orthogonal Multiple Access (NOMA) has been spotlighted as an emerging technology to meet the above-mentioned challenges. In this paper, we consider a densely deployed network in which users are divided into NOMA coalitions. Firstly, we model the power allocation problem as a differential game. Then, we extend the formulated game using a Mean Field Game (MFG) theoretic framework by considering the effect of the collective behavior of devices. Furthermore, we derive a distributed power control algorithm that enables the users to appropriately regulate their transmit power according to brief information received from the BS. Indeed, the analysis of the proposed approach is governed by the two fundamental Hamilton- Jacobi-Bellman (HJB) and Fokker-Planck-Kolmogorov (FPK) equations. Numerical results are presented to analyze the equilibrium behaviors of the proposed power control algorithm and to demonstrate the effectiveness of the formulated MFG compared to existing works in the literature.

International audience; Bio-inspired Spiking Neural Networks (SNNs) are promising candidates to replace standard Artificial Neural Networks (ANNs) for energy-efficient keyword spotting (KWS) systems. In this work, we compare the trade-off between accuracy and energy-efficiency of a gated recurrent SNN (Spik-GRU) with a standard Gated Recurrent Unit (GRU) on the Google Speech Command Dataset (GSCD) v2. We show that, by taking advantage of the sparse spiking activity of the SNN, both accuracy and energy-efficiency can be increased. Lever-aging data sparsity by using spiking inputs, such as those produced by spiking audio feature extractors or dynamic sensors, can further improve energy-efficiency. We demonstrate state-of-the-art results for SNNs on GSCD v2 with up to 95.9% accuracy. Moreover, SpikGRU can achieve similar accuracy than GRU while reducing the number of operations by up to 82%.

International audience; The new video coding standard, Versatile Video Coding (VVC), released by the end of 2020 has increased the coding complexity both at encoder and decoder sides. This complexity increase is due to several coding tools proposed to enhance the coding efficiency. One of these tools is the Multiple Transform Selection (MTS) concept, a new approach for the transform unit. This paper aims at providing a new optimization of the MTS based on dataflow modeling. The proposed approach takes benefit of the different parallelism levels of the MTS in order to create an optimized multicore implementation. Also, this paper study the impact of the dataflow model granularity and the dynamic reconfiguration on the implementation efficiency on x86 multicore architectures. The PREESM tool is used in this study to develop the proposed dataflow models and for the granularity analysis. The dynamic reconfiguration study is here performed using the SPIDER runtime optimized for the multicore execution of applications modeled using Parameterized and Interfaced Synchronous Dataflow (PiSDF) dataflow graphs. Two architectures were used in this work: an x86 architecture with 4 cores and an x86 architecture with 24 cores. The results show that the SPIDER overhead time is almost negligible (0.05%) compared to the execution time of the application. Furthermore, a speed-up of 3.9 and up to 22 for all block sizes was achieved using a 4-core and 24-core machine, respectively.

International audience; Attracted by the advantages of Non-Orthogonal Multiple Access (NOMA) in accommodating multiple users within the same resource, this paper investigates the power allocation problem for Machine Type Devices (MTDs) in a Hybrid NOMA system. Particularly, we consider a densely deployed network in which the devices are divided into orthogonal coalitions. Firstly, the power control problem is modeled as a differential game. Then, we formulate the proposed game as a Mean Field Game (MFG) in order to handle massive Internet of Things (IoT) access scenarios. Furthermore, we design an iterative algorithm that paves the way for distributed control in which the devices can appropriately regulate their transmit power in response to brief information received from the Base Station (BS). The analysis of the proposed approach is conducted through coupled equations, namely the Hamilton-Jacobi-Bellman (HJB) and the Fokker-Planck-Kolmogorov (FPK). Our simulation results prove the convergence of the proposed power control strategy and spotlight the robustness of our formulated MFG.

The additional discrete transforms from cosine (DCT) and sine (DST) families that come with the Adaptive Multiple Transform (AMT) approach is one of the major enhancements involved in the new Versatile Video Coding (VVC) standard. They have increasingly brought additional complexity compared to HEVC standard. The transform module is one of the most consuming stages in terms of time and hardware resources. This paper focuses on the optimization of the DST-VII transform. It deals with a multicriteria optimization algorithm for approximate computing that aims at the identification of the optimal approximation of the DST-VII according to several approximation measures. The resulting transform matrix has extremely low arithmetic complexity as well as close proximity to the exact DST-VII. Moreover, hardware synthesis results denote that the simplified design of DST-VII consumes only a third of the hardware resources used by the original algorithm. Experimental results obtained from joint exploration model simulations show a slight bit-rate increase while maintaining almost the same video quality. Such results confirm the effectiveness of the proposed approximate transform. The latter yields good performance in terms of computational complexity reduction and proximity to the exact transform while exhibiting a video coding performance comparable to the original algorithm.

International audience; The emergence of the new video coding standard, Versatile Video Coding (VVC), has resulted in a 40-50% coding gain over its predecessor HEVC for the same visual quality. However, this is accompanied by a sharp increase in computational complexity. The emergence of the VVC standard and the increase in video resolution have exceeded the capacity of single-core architectures. This fact has led researchers to use multicore architectures for the implementation of video standards and to use the parallelism of these architectures for real-time applications. With the strong growth in both areas, video coding and multicore architecture, there is a great need for a design methodology that facilitates the exploration of heterogeneous multicore architectures, which automatically generates optimized code for these architectures in order to reduce time to market. In this context, this paper aims to use the methodology based on data flow modeling associated with the PREESM software. This paper shows how the software has been used to model a complete standard VVC video decoder using Parameterized and Interfaced Synchronous Dataflow (PiSDF) model. The proposed model takes advantage of the parallelism strategies of the OpenVVC decoder and in particular the tile-based parallelism. Experimental results show that the speed of the VVC decoder in PiSDF is slightly higher than the OpenVVC decoder handwritten in C/C++ languages, by up to 11% speedup on a 24-core processor. Thus, the proposed decoder outperforms the state-of-the-art dataflow decoders based on the RVC-CAL model.

International audience; The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K.

International audience; Local mechanical properties of submicron features are of particular interest due to their influence on macroscopic material performance and behaviour. This study is focused on local nanomechanical measurements, based on the latest Atomic Force Microscopy (AFM) mode, where the peak force set point is finely controlled at each pixel. After probe calibration, we evaluate the impact of spring constant of two AFM hand-crafted natural full diamond tips with steel cantilevers, used for mapping. Based on the fast capture of the cantilever deflection at each pixel and real time force curve analysis in the elastic region, AFM local measured contact moduli mappings of the silica beads ('50 GPa) incorporated in an epoxy resin matrix, are compared with those determined using classical instrumented nanoindentation tests. Our analyses show that with the two AFM probes, without local residual deformation, the high moduli of the silica beads measured with this advanced AFM mode are within the standard deviation of the values determined by classical nanoindentation. Lay Description: The knowledge of material properties at the nanometer scale is a key parameter for well understanding and determining the behavior of material at macroscopic scale. In this paper, we compare two methods (an advanced mode and a classical one) based on the analysis of probes in interaction with the surface of studied material. We focus on a latest developed mode for determining local mechanical properties with a very high spatial resolution. For the advanced mode, we also consider two different hand-crafted probes. Our analyses show that with the high spatial resolution advanced mode, local mechanical properties are well determined. We also highlight the impact of the properties of the used probes for this advanced mode. In a final step, the power of the presented investigation lies in the fact that it does not modify the topography of the surface.

International audience; With the rapid surge of M-Health and smart city systems, the need to accommodate sensors and actuators to achieve effective automation turns out to be imposed, for an efficient machine-to-machine communication to be maintained. In this regard, the key elements necessary for a successful M-Health system to take place are discovered to be the power consumption and interoperability maintaining factors. In this context, the present study is conducted to devise a special elderly tracking and monitoring system, closely connected to a walking stick device. The proposed design involves a cane cased transmitter node, enabling to send data related to the position and the state of the elderly to a base station, through implementation of the LoRa technology. The latter would then apply the message queuing telemetry transport (MQTT) protocol to interact with the environment once a fall proves to take place. For the purpose of evaluating the advanced design associated coverage range and power consumption rate, as enhanced via LoRa network, several experimental tests have been administered. The achieved results appear to reveal that the suggested architecture recorded average covered area turns out to be of the rate of 6 km2.

This paper presents the design and the implementation of a fully integrated active phase shifter for beamforming at 5.8 GHz. The proposed circuit, implemented in a 0.25 µm BiCMOS SiGe:C process, is based on an original architecture using an injection-locked oscillator (ILO) associated with an in-phase/quadrature (IQ) modulator. The dynamic behaviour of an ILO is first analysed theoretically and important characteristics are deduced. At 2.5 V power supply voltage and total power dissipation of only 92.5 mW, the proposed circuit allows to obtain a 360° phase shift range and occupies 1.43 mm2. This phase shift is synthesised using the ILO for fine-tuning and the IQ modulator for coarse tuning.

International audience; In the context of constructing an embedded system to help visually impaired people to interpret text, in this paper, an efficient High-level synthesis (HLS) Hardware/Software (HW/SW) design for text extraction using the Gamma Correction Method (GCM) is proposed. Indeed, the GCM is a common method used to extract text from a complex color image and video. The purpose of this work is to study the complexity of the GCM method on Xilinx ZCU102 FPGA board and to propose a HW implementation as Intellectual Property (IP) block of the critical blocks in this method using HLS flow with taking account the quality of the text extraction. This IP is integrated and connected to the ARM Cortex-A53 as coprocessor in HW/SW codesign context. The experimental results show that the HLS HW/SW implementation of the GCM method on ZCU102 FPGA board allows a reduction in processing time by about 89% compared to the SW implementation. This result is given for the same potency and strength of SW implementation for the text extraction.

The H.266/Versatile Video Coding (VVC) standard, released in July 2020, has improved the encoder performance over the previous High Efficiency Video Coding (HEVC) with a significant increase in coding complexity. Enhancements on the transform module mainly involve the introduction of the Adaptive Multiple Transform (AMT) which has led to an additional computational complexity. This paper aims at reducing the transform module complexity by approximating the AMT core. The transform approximation has to reach a low MSE, a low total error energy, a low transform distortion and a high transform efficiency. The Particle Swarm Optimization (PSO) is used to solve the optimization problem modeled as a constrained one. The proposed approximate transforms preserve a good coding efficiency compared to the exact transforms and require a less arithmetic complexity as well. The hardware architectures of both the exact and the approximate versions of the 8, and 16-point DST VII transform are designed. The exact transforms are defined using multipliers and MCM-based designs. The approximate transforms are described using additions and bit-shifting operations. All the designs are implemented in the Arria 10 FPGA device. Synthesis results have shown that the proposed approximation saves more than 75% and 63% of logic utilization when compared to multipliers and MCM-based designs, respectively. The maximum operational frequency is of 180 MHz, supporting 2K and 4K videos at 231 and 58 fps, respectively.

International audience; The applicability of the Lambert-W function-based parameter extraction methodology is demonstrated for 28nm FDSOI MOSFETs down to deep cryogenic temperatures (4.2K). The Lambert-W function enables to accurately model the inversion charge and drain current MOSFET characteristics from weak to strong inversion, while using the classical mobility law down to liquid helium temperature. The main MOSFET parameters were extracted versus temperature and gate length, showing the temperature independence of short channel effects and the strong mobility degradation at short channel length due to increased neutral defect scattering.

Neodymium being an expensive strategic metal indispensable for our society, the key issue is to secure its supply and make its usage sustainable. However, with less than 1% of it currently being recycled, we are far from achieving this. Although some work is underway to recycle electrical engines’ large Nd-based magnet alloys, little attention has been given to recycling small Nd-containing ceramic-based components, despite their 12% share of the Nd market. Herein, we demonstrate an economically viable Nd recycling process from such components found in electronic wastes. We tackled the issue of high Nd dilution in complex e-wastes through the upstream deployment of simultaneous disassembly, machine vision and multi-energy X-ray transmission sorting (first-of-its-kind), followed by precise beneficiation in virtue of the difference in magnetism, density and fracture toughness. The resulting concentrates are mainly dielectric ceramics (BaO-Nd2O3-TiO2), containing 38.3 wt% of Nd. Although ceramics are refractory in general, Nd can be simply leached in concentrated HNO3 from these dielectrics with high selectivity under optimized conditions. Subsequently, Nd can be recovered by oxalate precipitation while 60% of HNO3 can be regenerated. To elaborate on the mechanism of the leaching, the related kinetics, thermodynamics and bonding nature were investigated through theoretical computations. The overall Nd recovery efficiency reaches 91.1% ending up with commercial-grade Nd2O3 (> 99.6%). More importantly, the recycling route is estimated profitable within four years based on conservative margins. This work provides a promising strategy to recover rarely recycled strategic metals towards a closed-loop design. National Environmental Agency (NEA) National Research Foundation (NRF) Published version All authors acknowledge financial support from SCARCE project, which is supported by the National Research Foundation, Singapore, and the National Environment Agency, Singapore under its Closing the Waste Loop R&D Initiative (Award No. USS-IF-2018-4).

The optical absorption spectra of the azobenzene-functionalized metal–organic framework (MOF), PCN-123, are calculated in cis and trans configurations using the Bethe–Salpeter equation (BSE) formal...

The ternary alloy of germanium, antimony, and tellurium (GST) is widely used as a material for phase-change memories. In particular, the stoichiometric compound Ge 2Sb 2Te 5 exhibits a rapid congruent crystallization. To increase the temperature at which spontaneous crystallization erases the stored information, alloys that are enriched in germanium have been investigated. Their crystallization is accompanied by segregation and eventually the nucleation of a new, germanium-rich phase. In order to model the redistribution of alloy components and the time evolution of the microstructure during device operations, we develop a multi-phase-field model for the crystallization of GST that includes segregation and couple it with orientation fields that describe the grain structure. We demonstrate that this model is capable to capture both the emergence of a two-phase polycrystalline structure starting from an initially amorphous material, and the melting and recrystallization during the SET and RESET operations in a memory cell of the “wall” type.

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

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International audience; In this study, the amorphous structure of Ge-Se-Sb-N chalcogenide thin films is investigated through Raman, Infrared and X-ray Absorption Spectroscopies in the light of the electrical performances of such materials once integrated in OTS selector devices. In particular, we show that the presence of homopolar and wrong bonds in the amorphous structure has a detrimental impact on the subthreshold leakage current of OTS devices. Whereas the presence of Sb-Sb and Ge-Sb bonds tends to increase the leakage current in pristine devices, the presence of Se-Se bonds is correlated to a significant device-to-device dispersion of sub-threshold characteristics after the device initialization. Finally, the incorporation of a proper N concentration in Ge-Se-Sb glass permits to suppress the homopolar bonds, leading to a very low leakage current and a low device-to-device dispersion.

Vu le développement rapide des systèmes E-santé et de la ville intelligente, la nécessité de prendre en charge les capteurs et les actionneurs, pour une automatisation efficace, s'avère être une exigence essentielle pour la maintenance de la communication machine à machine (M2M). Les éléments clés d’un système E-santé performant sont la consommation d’énergie et l’interopérabilité. C’est dans ce contexte que l’on pourrait définir notre thèse,un système dédié aux personnes âgées,agissant et surveillant à l’aide de leur canne connectée qui est mis en œuvre. Notre système consiste en un nœud émetteur positionné sur la canne qui transmet les données relatives aux déplacements et à l'état des personnes âgées à une station de base via la technologie LoRa. Cette dernière utilise ensuite le protocole MQTT (Message Queuing Telemetry Transport) pour interagir avec l'environnement quand une chute est survenue. Plusieurs expériences ont été menées pour évaluer la zone couverte par notre réseau LoRa et la consommation d’énergie de notre système.Les résultats indiquent que la superficie moyenne couverte est d'environ 6 km2 et que la consommation électrique de notre système est au moins dix fois inférieure à celle d'un système de transmission basé sur le GSM, With the increasing surge of M-Health and smart city systems, the need to accommodate sensors and actuators, for an effective automation to take place, proves to constitute a critical requirement for Machine-to-Machine (M2M) communication to be maintained. The key elements for a successful M-Health system are power consumption and maintaining interoperability .It is in this context that the present work could be set, whereby a system dedicated to the elderly tacking and monitoring using their connected walking stick is implemented. Our system consists of a transmitter node positioned on the cane that transmits data related to the position and the state of the elderly, to a base station via LoRa technology, then the latter uses Message Queuing Telemetry Transport (MQTT) protocol to interact with the environment when a fall has occurred. Several experiments have been conducted to evaluate the area covered by our LoRa network and the power consumption of our system. The results indicate that the average covered area is around 6 km2 and the power consumption of our system is at least ten times lower than for a GPRS-based transmission system

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International audience; Thermal transport properties bear a pivotal role in influencing the performance of phase change memory (PCM) devices, in which the PCM operation involves fast and reversible phase change between amorphous and crystalline phases. In this paper, we present a systematic experimental and theoretical study on the thermal conductivity of GeTe at high temperatures involving fast change from amorphous to crystalline phase upon heating. Modulated photothermal radiometry (MPTR) is used to experimentally determine thermal conductivity of GeTe at high temperatures in both amorphous and crystalline phases. Thermal boundary resistances are accurately taken into account for experimental consideration. To develop a concrete understanding of the underlying physical mechanism, rigorous and in-depth theoretical exercises are carried out. For this, first-principles density functional methods and linearized Boltzmann transport equations (LBTE) are employed using both direct and relaxation time based approach (RTA) and compared with that of the phenomenological Slack model. The amorphous phase experimental data has been described using the minimal thermal conductivity model with sufficient precision. The theoretical estimation involving direct solution and RTA method are found to retrieve well the trend of the experimental thermal conductivity for crystalline GeTe at high temperatures despite being slightly overestimated and underestimated, respectively, compared to the experimental data. A rough estimate of vacancy contribution has been found to modify the direct solution in such a way that it agrees excellently with the experiment. Umklapp scattering has been determined as the significant phonon-phonon scattering process. Umldapp scattering parameter has been identified for GeTe for the whole temperature range which can uniquely determine and compare Umklapp scattering processes for different materials.

International audience; Automatic detection of epileptic seizures is a very crucial step for diagnosing patients with drug-resistant epilepsies. If visual analysis of long-term electroencephalographic signals is the most reliable technique, automatic seizures detection can help the physicians in comparing seizures and extracting common patterns. In this paper, a new approach to classify background activity and pre-ictal stereoelectroencephalographic signals is proposed. Linear and nonlinear features are extracted directly from the derived intrinsic mode functions of multivariate empirical mode decomposition technique and the classification is performed using support vector machines. The effectiveness of the proposed approach is evaluated using real datasets. Our results show good performance of the proposed approach since an accuracy of 100% is achieved using the first intrinsic mode function and a window size of 1024 samples. © 2020 IEEE.

International audience; Many multifaceted images comprise observable text. If the occurrences of this text can be identified, segmented, and recognized automatically, they will be a prized source of high-level semantics; for retrieval and indexing. In this paper, we will propose a novel method for localizing and detecting text in complex images and video frames based on morphology. A morphological Gardient is generated by computing the variance between the dilation and the erosion image. Then the candidate of regions are connected via a morphological closing operation and every text areas are determined used the occurrence of text in each candidate. The identified text regions are localized perfectly via the projection of the text pixels in the morphological Gardient map. This method is sturdy to different position, character size, color and contrast. The updating of the text region between images is also used to minimize the processing time. Tests are realized on divers images to confirm the good efficient of our method.

The standardization of the Versatile Video Coding (VVC) is still carrying out. Its first version is planned to be finished by the end of 2020. VVC promises higher coding efficiency than the High Efficiency Video Coding (HEVC) due to the improvements of the different coding tools. The adaptive Multiple Transform (AMT) is one of the major enhancements of the transform module of the VVC where five transform types have been introduced. However, the encoder and decoder complexities have been increased dramatically. This paper discusses one solution for codec complexity alleviation by considering transform approximation. It focuses on the approximation of the DST of type VII. The proposed approximation consists in applying the Particle Swarm Optimization (PSO) algorithm to the target transform in order to get an approximate matrix with low computational complexity requirements. This algorithm is used to cope with traditional approximation techniques based on constrained optimization of the DST transform. The proposed transform has shown a significant computational complexity reduction with no quality degradation and a tolerable BD-rate loss.

International audience; Wireless Sensor Networks (WSN) is an evolving field of research with various applications. Deploying sensors is a decisive operation that greatly influences the performance and the functioning of the network. Comparing the 2D deployment with the 3D one, the latter is more complex because of its ability to attend more constraints imposed by real problems. On this article, we discuss the 3D node positioning problem, while minimizing the global number of sensors, the consumption levels of energy, and maximizing the covered area and the hybrid localization rate based on the 3D DV-HOP protocol and the RSSI. We seek to solve our problem by choosing the ideal 3D locations to add nomad nodes to achieve the mentioned objectives. An approach based on variants of optimization algorithms based on the NSGA-II algorithm [1] and the ACO algorithm [2] is proposed. The simulation model considers the implementation of the IEEE 802.15.4 standard, and a reactive AODV based routing layer. The results of simulations with OMNeT++ indicate the sustainability of the tested algorithms (NSGA-II, ACO).

International audience; This paper presents an efficient High-level synthesis (HLS) hardware design to implement the Inverse Quantization and Transform (IQ/IT) for a High Efficiency Video Coding (HEVC) decoder. Using Xilinx Vivado HLS tool, different directives are applied to the IQ/IT C code to select the optimized hardware architecture in terms of area and clock cycles. This architecture is implemented in a SW/HW context for verification. In fact, it is connected to ARM Cortex-A9 processor using AXI stream interface and integrated on Xilinx Zynq ZC702 platform. Therefore, the experimental results show that the SW/HW design can only decode 240p@15fps with a gain of 8% in throughput and 74% in power consumption compared to SW implementation.

This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform IQ/IT for a high-efficiency video coding HEVC decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit TU sizes: 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array FPGA and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware SW/HW enviro nment in order to evaluate different implementation methods SW and SW/HW in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

International audience; The Gamma Correction Method GCM is used as an important task in the text extraction process. In this paper, we propose a co-design implementation of the GCM using an FPGA board. This HW/SW implementation uses VHDL and C language to build a real embedded system validation. The implementation methodology performs an optimized run time of the GCM for text extraction in complex images. Our experiments are based on an FPGA HW/SW board. The obtained results showed that the proposed method can help to improve the performance of the GCM for text extraction by using the NiosII processor and hardware custom instructions. The proposed architecture enables to gain of 35% of the run time.

Versatile video coding is the next generation video coding standard expected by the end of 2020. Several new contributions have been proposed to enhance the coding efficiency beyond the high efficiency video coding standard. One of these tools is the adaptive multiple transform (AMT) as a new approach of the transform core design. The AMT involves five discrete cosine transform/discrete sine transform types with larger and more flexible partitioning block sizes. However, the AMT coding efficiency comes with the cost of higher computational complexity, especially at the encoder side. In this paper, a efficient pipelined hardware implementation of the AMT including the five types of sizes $4\times 4$ , $8\times 8$ , $16\times 16$ and $32\times 32$ is proposed. The architecture design takes advantage of the internal software/hardware resources of the target field-programmable gate array device such as library of parametrized modules core intellectual properties and digital signal processing blocks. The proposed 1-D 32-point AMT design allows to process 4K video at 44 frames/s. A unified 2-D implementation of the 4, 8, 16, and 32-point AMT design is also presented.The implementation takes into account all the asymmetric 2-D block size combinations from 4 to 32. The 2-D architecture design is able to sustain 2K video coding at 50 frames/s with an operational frequency up to 147 MHz.

International audience; Energy consumption of large-scale networks has become a primary concern in a society increasingly dependent on information technology. Novel solutions that contribute to achieving energy savings in wired networks have been proposed to mitigate ongoing and alarming climate change and global warming. A detailed survey of relevant power-saving approaches in wired networks is presented here. We give a special focus on carrier-grade networks. At first we perform a comprehensive study of communication infrastructures regarding energy saving. Then, we highlight key issues to enable green networks, ranging from network design to network operation. After that, we present the major contributors to power consumption in wireline networks. Afterwards, we survey, classify, and compare the main energy-aware methods and mechanisms that are the most appropriate for improving the energy efficiency of carrier-grade networks.

co-publication avec un laboratoire étranger; International audience; Wireless Multimedia Sensor Networks (WMSNs) are a particular instance of Wireless Sensor Networks that support the transmission of multimedia data such as video, image or sound. Those multimedia data should be delivered with a variety of predefined levels of Quality of Service which imposes the development of specific routing protocols. In this paper, we propose a new routing protocol based on clustering, that balances the number of nodes in clusters, called Equal Size Clusters to reduce Congestion in WMSNs. We seek to balance the number of members in each cluster in order to reduce intra-cluster congestion and reduce the number of congested cluster-heads. Therefore, we propose a novel metric called Maximum Cluster-heads Utilization Ratio (MCUR) that indicates the largest number of members assigned to a cluster-head to ensure a reliable transmission of multimedia data. Simulation results indicate that our proposed scheme outperforms other protocols proposed in the literature in terms of MCUR, number of cluster-heads and energy consumed.

JIF=1.200; International audience; Research interest has been focused on vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communication systems, known as V2X technologies, namely in road safety and traffic ergonomics. The evaluation of their performance is crucial before their potential integration and deployment in real systems. The present work aims at investigating the correspondences between two sets of scenarios of a simulation and an experimental model pertaining to the performance of IEEE 802.11p communication standard, and confronting their results. Concerning the first set, it pertains to the simulation of the physical layer PHY IEEE 802.11p standard, involving the implementation of V2X PHY transmission model, in a vehicle-to-vehicle V2V and vehicle-to-infrastructure V2I, according to different scenarios. The simulation series also involved data exchange between high-speed vehicles over Rice Race channel. This paper highlights several main parameters that may affect the physical layer network performance and the quality of transmission QoT. In this paper, the Bit Error Rate BER according to the Signal to Noise Ratio SNR was used to assess the performance of the V2X communication standard using all modulation types. Regarding the second set of evaluation scenarios, it includes the development of real-case measurements using the Arada LocoMate OBU transmission system to test the effects of the transmission range on V2X communications. V2I and V2V communications are evaluated in terms of real low and high mobility effects with transmission being taken into account.

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In this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architecture as the combination of a SOI transistor in parallel with a variable-resistance bridge. The crucial aspect is the analytical description of the bridge threshold voltage. The complete A2RAM compact model is implemented in Verilog-A to allow the use of SPICE simulator. DC and memory characteristics are validated by TCAD. SPICE simulations show the operation of 2 × 2 A2RAM matrix.

Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. VVC introduces several new coding tools that enable better coding performance compared to the High Efficiency Video Coding (HEVC) standard. The Multiple Transform Selection (MTS) concept, as introduced in VVC, relies on three trigonometrical transforms, and at the encoder side, selects the couple of horizontal and vertical transforms that maximises the RateDistortion cost. However, the new Discrete Sine Transform (DST)VII and Discrete Cosine Transform (DCT)-VIII do not have fast computing algorithms and rely on matrix multiplication, which requires high hardware resources especially for large block sizes.This paper tackles the hardware implementation of an approximation of MTS module. This approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variants of DCT-II family mainly DCT-II and its inverse. Therefore, an efficient 2D hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform. A unified 2D implementation of 16 and 32-point forward-inverse DCTII, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain 2K and 4K videos at 377 and 94 frames per second, respectively, while using only 18% of Alms, 40% of registers and 34% of Digital Signal Processing (DSP) blocks of the ArrialO SoC platform.

This paper presents the design and implementation of an RF energy harvester system at 5.8[Formula: see text]GHz for low-power wireless transmission applications. The potential application of the proposed system is to wirelessly power sensor nodes. First, a design methodology of the rectifier based on a theoretical approach is presented. The simulation results show an excellent correlation with the theoretical ones, proving the accuracy of the proposed design methodology. A prototype is fabricated and the simulation results are validated by the measurements. Then, the rectenna is combined to a commercial power management circuit and a load which emulates the behavior of a sensor. The power management circuit boosts and regulates the output DC voltage as well as stores the collected energy into a capacitor. Finally, the complete system is experimentally tested and excellent performances are demonstrated. The efficiency of the RF energy harvester is 24% at [Formula: see text]10[Formula: see text]dBm input power and 47% at [Formula: see text]5[Formula: see text]dBm input power which are the highest reported measured efficiencies at this frequency and at those power levels. The complete rectenna system is able to harvest 4.62[Formula: see text]mJ in 40 s and 192[Formula: see text]s for [Formula: see text]6[Formula: see text]dBm and [Formula: see text]10[Formula: see text]dBm input power, respectively allowing us to power wirelessly low-power electronic devices.

The HEVC video coding standard supports different transform sizes ranging from 4-point to 32-point. In fact, multiple transform sizes improve coding efficiency, but increase as well the computational complexity. Hardware decoders apply different techniques to satisfy real-time requirements. This paper describes a novel design methodology of a unified 2D inverse core transform IICT. The hardware architecture is based on a 1D-IICT block and a transpose buffer FIFO memory used to store the intermediate values of 1D transform. All this process is controlled in such a way to reduce the hardware and memory resources. To support the different transform sizes, matrix multiplications are simplified based on transform blocks decomposition into fixed-size sub-blocks in previous works. The architecture was developed for an FPGA device. Synthesis results on Startix III FPGA device show that the proposed design, operating at 266 MHz, is sufficient to decode high resolution videos using only 10% of total pins and about 33% of the hardware resources offered.

International audience; Bluetooth Low Energy (BLE) has revealed for decades many interesting opportunities especially in the field of positioning that made of it one of the most used technologies in indoor localization solutions. The system we propose is a combination of BLE, Acoustic and LiFi technologies. Our approach is not just arithmetic but using real time computed metrics that act precision indicators or "Dilution of precision" (DOP) weights of the results given by each technology. Depending on these DOP-like indicators, we were able to judge how much precise and accurate the returned results are. Our new approach was confirmed during experiments showing that the precision of this new hybrid system is much better when using these new precision metrics.

International audience

International audience

Due to the increasing need for testing solutions to complex hardware designs, several efforts were made in order to improve high-level synthesis (HLS) techniques. These solutions are conceived in such a way that they had to provide reasonable agreements in terms of design time, resources involved, and performance. Generally speaking, two main constraints should be satisfied for HLS applications. The first constraint consists in the ability to process complex systems at a reasonable cost, whereas the second revolves around considering some test constraints in the first tasks of the HLS flow. To fulfill these two constraints, we treated a case study using HLS for intraprediction, dequantization, and inverse transform decoding blocks of an high efficiency video coding (HEVC) decoder. For this experiment, version 10 was used of the HEVC test model (HM) reference software containing >200 functions and over 8000 lines of code. In addition, the suggested algorithm was implemented in an software/hardware (SW/HW) environment using Xilinx ZC 702-based platform. Finally, taking advantage of HLS optimization methods, the hardware design can process 6, 13, 71, and 285 video frames per second for 1600p, 1080p, 480p, and 240p video resolutions, respectively. Yet, the SW/HW designs can only decode 0.5, 1.5, 4, and 15.2 frames per second for the same video resolutions, i.e., with a gain of 3% in frame rate and 60% in power consumption compared to SW implementation.

International audience; the drastic downscaling of the transistor size along with advances in material sciences allowed the development of low power CMOS technologies with competitive RF figure of merits for millimeter wave applications. In this context, this paper presents the RF characterization (up to 50 GHz) of an advanced 22nm UTBB FDSOI technology developed by Globalfoundries. In addition to the DC performances with a DC transconductance of 1.6 S/mm, this technology presents promising RF characteristics with a F-t/F-max above 330 GHz. Also, it is shown that the device's gate finger width can be decreased down to 0.3 mu m without RF performance degradation. Furthermore, the relaxed contacted poly pitch is shown to have favorable impact on F-max

International audience; This paper presents an FPGA accelerator based on circular buffer unit per orientation for a fast and optimized Gray Level Co-occurrence Matrix (GLCM) and four Texture features computation. The Four texture features namely, contrast, energy, dissimilarity and correlation are computed using Xilinx FPGA. However, the computation of GLCM and four textures features are very complex and consume a lot of execution time. In this paper, an FPGA accelerator for fast computation of GLCM and four texture features are designed and implemented. This architecture was implemented on a Xilinx Zc-702 using Vivado HLS. The obtained results are then compared against other related works. The synthesis results on FPGA prove a significant gain (about 17%) in execution time compared to the previous work.

International audience; Wireless Sensor Networks (WSNs) is a class of low power and Lossy networks (LLN) which are useful to monitor a physical/environmental phenomenon. The Routing Protocol for Low Power and lossy networks (RPL) is a standardized protocol specifically designed to route the data over LLN networks. In particular, to take into account the specific features of LLN the RPL protocol computes the best routes following one or several metrics (e.g., the residual energy of nodes or the link quality) based on the state of the nodes (a.k.a sensors) or links. Nevertheless, RPL was originally designed to handle static networks ; when node(s) move(s), the performances of RPL drop down. This issue has motivated a great deal of interest in ensuring that sensors may route the sensing data even thought they move from place to place, establishing new links and moving away from the previously established links. In this paper, we present RPL and the solutions that permit to deal with mobile nodes. We introduce a simulation-based evaluation of these solutions, which is focused on the energy consumption and the packet losses. The comparison between RPL and MRPL shows that RPL consumes less energy due to many packet losses. In counterpart, RPL does not provide a continuous connectivity to mobile sensor contrary to MRPL that keeps connection.

International audience; Text extraction and character recognition in manuscripts are a very important part of image processing and pattern recognition. The recently proposed Gamma Correction Method (GCM) is a popular method used in the processing of a color image and in particular in the extraction of text from a complex image. However, The GCM consumes a lot of time to extract the text and this is because of the complex calculations of different operations in the different blocks of GCM which is not suitable to real-time applications. In this paper, we propose an efficient Gamma Correction Method acceleration. Our proposal allows to minimize the GCM execution time while ensuring the same reliability of the initial version. The experimental results show an important optimization compared to the literature.

This paper presents an original solution to correct the delay causing by the transmission path delay. This can be corrected through a phase shift provided by coupling Voltage Controlled Oscillators (VCOs). Indeed, the phase constant phase progression in the oscillator array can be obtained by detuning the free-running frequencies of the two outermost oscillators in the array in opposite directions. This technique is applied to compare the Error Vector Modulator (EVM) with the Quadrature Phase Shift Keying (QPSK) and 16-Quadrature Amplitude Modulation (16-QAM). An example with a carrier of 6 GHz and for flow rate equal to 2GHz, shows a correction of the receiving signal lower than 15%.

This paper presents the design and the implementation of a fully integrated active phase shifter for beamforming at 5.8 GHz in a 0.25 µm BiCMOS SiGe:C process. The proposed circuit is able to provide a 360° continuous phase shift range, allowing to control the radiation pattern of a phased antenna array. The required phase shift is synthesized using an Injection-Locked Oscillator (ILO) for fine tuning followed by an in-phase/quadrature (IQ) modulator for coarse tuning. The total current consumption of the circuit is 33.7 mA from a 2.5 V supply voltage. The core size including all the pads is 1.324*1.086mm2.

International audience; The double random phase encryption (DRPE) method is a well-known all-optical architecture which has many advantages especially in terms of encryption efficiency. However, the method presents some vulnerabilities against attacks and requires a large quantity of information to encode the complex output plane. In this paper, we present an innovative hybrid technique to enhance the performance of DRPE method in terms of compression and encryption. An optimized simultaneous compression and encryption method is applied simultaneously on the real and imaginary components of the DRPE output plane. The compression and encryption technique consists in using an innovative randomized arithmetic coder (RAC) that can well compress the DRPE output planes and at the same time enhance the encryption. The RAC is obtained by an appropriate selection of some conditions in the binary arithmetic coding (BAC) process and by using a pseudo-random number to encrypt the corresponding outputs. The proposed technique has the capabilities to process video content and to be standard compliant with modern video coding standards such as H264 and HEVC. Simulations demonstrate that the proposed crypto-compression system has presented the drawbacks of the DRPE method. The cryptographic properties of DRPE have been enhanced while a compression rate of one-sixth can be achieved. FPGA implementation results show the high performance of the proposed method in terms of maximum operating frequency, hardware occupation, and dynamic power consumption.